xtensa: intel_s1000: Add SoC level SYS_INIT
Added a SYS_INIT for SoC level initialization of Intel S1000 Added routines for setting up resource ownership for DMA, I2S Added routine to setup power gating and clock configuration Signed-off-by: Sathish Kuttan <sathish.k.kuttan@intel.com>
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824bcaca52
2 changed files with 127 additions and 61 deletions
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@ -4,6 +4,9 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define SYS_LOG_LEVEL SYS_LOG_LEVEL_INFO
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#define SYS_LOG_DOMAIN "soc/s1000"
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#include <device.h>
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#include <xtensa_api.h>
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#include <xtensa/xtruntime.h>
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@ -11,6 +14,9 @@
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#include <board.h>
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#include <irq_nextlevel.h>
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#include <xtensa/hal.h>
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#include <init.h>
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static u32_t ref_clk_freq;
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void _soc_irq_enable(u32_t irq)
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{
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@ -140,20 +146,26 @@ void _soc_irq_disable(u32_t irq)
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}
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}
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/* Setup DMA ownership registers */
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void setup_ownership_dma0(void)
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static inline void soc_set_resource_ownership(void)
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{
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*(volatile u16_t *)CAVS_DMA0_OWNERSHIP_REG = 0x80FF;
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}
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volatile struct soc_resource_alloc_regs *regs =
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(volatile struct soc_resource_alloc_regs *)
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SOC_RESOURCE_ALLOC_REG_BASE;
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int index;
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void setup_ownership_dma1(void)
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{
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*(volatile u16_t *)CAVS_DMA1_OWNERSHIP_REG = 0x80FF;
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}
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void setup_ownership_dma2(void)
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{
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*(volatile u16_t *)CAVS_DMA2_OWNERSHIP_REG = 0x80FF;
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/* set ownership of DMA controllers and channels */
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for (index = 0; index < SOC_NUM_LPGPDMAC; index++) {
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regs->lpgpdmacxo[index] = SOC_LPGPDMAC_OWNER_DSP;
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}
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/* set ownership of I2S and DMIC controllers */
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regs->dspiopo = SOC_DSPIOP_I2S_OWNSEL_DSP |
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SOC_DSPIOP_DMIC_OWNSEL_DSP;
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/* set ownership of timestamp and M/N dividers */
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regs->geno = SOC_GENO_TIMESTAMP_OWNER_DSP |
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SOC_GENO_MNDIV_OWNER_DSP;
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}
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void dcache_writeback_region(void *addr, size_t size)
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@ -166,41 +178,54 @@ void dcache_invalidate_region(void *addr, size_t size)
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xthal_dcache_region_invalidate(addr, size);
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}
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void setup_ownership_i2s(void)
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{
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u32_t value = I2S_OWNSEL(0) | I2S_OWNSEL(1) |
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I2S_OWNSEL(2) | I2S_OWNSEL(3);
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*(volatile u32_t *)SUE_DSPIOPO_REG |= value;
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value = DSP_RES_ALLOC_GENO_MDIVOSEL;
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*(volatile u32_t *)DSP_RES_ALLOC_GEN_OWNER |= value;
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}
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u32_t soc_get_ref_clk_freq(void)
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{
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u32_t bootstrap;
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static u32_t freq;
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if (freq == 0) {
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/* if bootstraps have not been read before, read them */
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bootstrap = *((volatile u32_t *)SOC_S1000_GLB_CTRL_STRAPS);
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bootstrap &= SOC_S1000_STRAP_REF_CLK;
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switch (bootstrap) {
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case SOC_S1000_STRAP_REF_CLK_19P2:
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freq = 19200000;
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break;
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case SOC_S1000_STRAP_REF_CLK_24P576:
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freq = 24576000;
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break;
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case SOC_S1000_STRAP_REF_CLK_38P4:
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default:
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freq = 38400000;
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break;
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}
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}
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return freq;
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return ref_clk_freq;
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}
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static void soc_set_power_and_clock(void)
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{
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volatile struct soc_dsp_shim_regs *regs =
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(volatile struct soc_dsp_shim_regs *)
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SOC_DSP_SHIM_REG_BASE;
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regs->clkctl |= SOC_CLKCTL_REQ_FAST_CLK | SOC_CLKCTL_OCS_FAST_CLK;
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regs->pwrctl |= SOC_PWRCTL_DISABLE_PWR_GATING_DSP1 |
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SOC_PWRCTL_DISABLE_PWR_GATING_DSP0;
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}
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static void soc_read_bootstraps(void)
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{
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u32_t bootstrap;
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bootstrap = *((volatile u32_t *)SOC_S1000_GLB_CTRL_STRAPS);
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bootstrap &= SOC_S1000_STRAP_REF_CLK;
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switch (bootstrap) {
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case SOC_S1000_STRAP_REF_CLK_19P2:
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ref_clk_freq = 19200000;
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break;
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case SOC_S1000_STRAP_REF_CLK_24P576:
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ref_clk_freq = 24576000;
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break;
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case SOC_S1000_STRAP_REF_CLK_38P4:
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default:
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ref_clk_freq = 38400000;
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break;
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}
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}
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static int soc_init(struct device *dev)
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{
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soc_read_bootstraps();
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ref_clk_freq = soc_get_ref_clk_freq();
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SYS_LOG_INF("Reference clock frequency: %u Hz", ref_clk_freq);
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soc_set_resource_ownership();
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soc_set_power_and_clock();
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return 0;
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}
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SYS_INIT(soc_init, PRE_KERNEL_1, 99);
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@ -82,19 +82,63 @@
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#define SSP_MN_DIV_SIZE (8)
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#define SSP_MN_DIV_BASE(x) (0x00078D00 + ((x) * SSP_MN_DIV_SIZE))
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#define SOC_INTEL_S1000_MCK_XTAL_FREQ_HZ 38400000
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#define PDM_BASE 0x00010000
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/* address of I2S ownership register. We need to properly configure
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* this register in order to access the I2S registers.
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*/
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#define SUE_DSP_RES_ALLOC_REG_BASE 0x00071A60
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#define SUE_DSPIOPO_REG (SUE_DSP_RES_ALLOC_REG_BASE + 0x08)
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#define I2S_OWNSEL(x) (0x1 << (8 + (x)))
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#define SOC_NUM_LPGPDMAC 3
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#define SOC_NUM_CHANNELS_IN_DMAC 8
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/* Address and bit field definition for general ownership register */
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#define DSP_RES_ALLOC_GEN_OWNER (SUE_DSP_RES_ALLOC_REG_BASE + 0x0C)
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#define DSP_RES_ALLOC_GENO_DIOPTOSEL (BIT(2))
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#define DSP_RES_ALLOC_GENO_MDIVOSEL (BIT(1))
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/* SOC Resource Allocation Registers */
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#define SOC_RESOURCE_ALLOC_REG_BASE 0x00071A60
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/* bit field definition for LP GPDMA ownership register */
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#define SOC_LPGPDMAC_OWNER_DSP \
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(BIT(15) | BIT_MASK(SOC_NUM_CHANNELS_IN_DMAC))
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#define SOC_NUM_I2S_INSTANCES 4
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/* bit field definition for IO peripheral ownership register */
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#define SOC_DSPIOP_I2S_OWNSEL_DSP \
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(BIT_MASK(SOC_NUM_I2S_INSTANCES) << 8)
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#define SOC_DSPIOP_DMIC_OWNSEL_DSP BIT(0)
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/* bit field definition for general ownership register */
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#define SOC_GENO_TIMESTAMP_OWNER_DSP BIT(2)
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#define SOC_GENO_MNDIV_OWNER_DSP BIT(1)
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struct soc_resource_alloc_regs {
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union {
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u16_t lpgpdmacxo[SOC_NUM_LPGPDMAC];
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u16_t reserved[4];
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};
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u32_t dspiopo;
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u32_t geno;
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};
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/* SOC DSP SHIM Registers */
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#define SOC_DSP_SHIM_REG_BASE 0x00071F00
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/* SOC DSP SHIM Register - Clock Control */
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#define SOC_CLKCTL_REQ_FAST_CLK BIT(31)
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#define SOC_CLKCTL_REQ_SLOW_CLK BIT(30)
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#define SOC_CLKCTL_OCS_FAST_CLK BIT(2)
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/* SOC DSP SHIM Register - Power Control */
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#define SOC_PWRCTL_DISABLE_PWR_GATING_DSP0 BIT(0)
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#define SOC_PWRCTL_DISABLE_PWR_GATING_DSP1 BIT(1)
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struct soc_dsp_shim_regs {
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u32_t reserved[8];
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u64_t walclk;
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u64_t dspwctcs;
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u64_t dspwct0c;
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u64_t dspwct1c;
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u32_t reserved1[14];
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u32_t clkctl;
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u32_t clksts;
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u32_t reserved2[4];
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u16_t pwrctl;
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u16_t pwrsts;
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u32_t lpsctl;
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u32_t lpsdmas0;
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u32_t lpsdmas1;
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u32_t reserved3[22];
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};
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#define USB_DW_BASE 0x000A0000
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#define USB_DW_IRQ 0x00000806
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extern void _soc_irq_enable(u32_t irq);
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extern void _soc_irq_disable(u32_t irq);
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extern void setup_ownership_dma0(void);
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extern void setup_ownership_dma1(void);
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extern void setup_ownership_dma2(void);
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extern void dcache_writeback_region(void *addr, size_t size);
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extern void setup_ownership_i2s(void);
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extern void dcache_invalidate_region(void *addr, size_t size);
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extern u32_t soc_get_ref_clk_freq(void);
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#endif /* __INC_SOC_H */
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