xtensa: specify which SR to store pointer to _kernel.cpu struct
This allows Kconfig to specify which special register is being used to store the pointer to the _kernel.cpu struct. Since the SoC itself is highly configurable, sometimes MISC0 is not available. So this adds the ability to use other special registers. Signed-off-by: Daniel Leung <daniel.leung@intel.com>
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3 changed files with 21 additions and 4 deletions
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@ -89,4 +89,11 @@ config XTENSA_USE_CORE_CRT1
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SoC or boards might define their own __start by setting this setting
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to false.
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config XTENSA_KERNEL_CPU_PTR_SR
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string
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default "MISC0"
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help
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Specify which special register to store the pointer to
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_kernel.cpus[] for the current CPU.
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endmenu
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@ -236,7 +236,7 @@ _switch_restore_pc:
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*/
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.align 4
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_handle_excint:
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EXCINT_HANDLER MISC0, ___cpu_t_nested_OFFSET, ___cpu_t_irq_stack_OFFSET
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EXCINT_HANDLER CONFIG_XTENSA_KERNEL_CPU_PTR_SR, ___cpu_t_nested_OFFSET, ___cpu_t_irq_stack_OFFSET
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/* Define the actual vectors for the hardware-defined levels with
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* DEF_EXCINT. These load a C handler address and jump to our handler
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@ -11,6 +11,7 @@
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#ifndef _ASMLANGUAGE
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#include <string.h>
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#include <stdbool.h>
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#ifdef __cplusplus
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extern "C" {
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@ -21,6 +22,16 @@ extern "C" {
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#define STACK_ROUND_UP(x) ROUND_UP(x, STACK_ALIGN_SIZE)
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#define STACK_ROUND_DOWN(x) ROUND_DOWN(x, STACK_ALIGN_SIZE)
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#define RSR(sr) \
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({u32_t v; \
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__asm__ volatile ("rsr." sr " %0" : "=a"(v)); \
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v; })
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#define WSR(sr, v) \
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do { \
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__asm__ volatile ("wsr." sr " %0" : : "r"(v)); \
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} while (false)
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extern void FatalErrorHandler(void);
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extern void ReservedInterruptHandler(unsigned int intNo);
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@ -34,7 +45,7 @@ static ALWAYS_INLINE _cpu_t *_arch_curr_cpu(void)
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#ifdef CONFIG_XTENSA_ASM2
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void *val;
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__asm__ volatile("rsr.misc0 %0" : "=r"(val));
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val = (void *)RSR(CONFIG_XTENSA_KERNEL_CPU_PTR_SR);
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return val;
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#else
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@ -68,8 +79,7 @@ static ALWAYS_INLINE void kernel_arch_init(void)
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* this record is a per-CPU thing and having it stored in a SR
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* already is a big win.
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*/
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__asm__ volatile("wsr.MISC0 %0; rsync" : : "r"(cpu0));
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WSR(CONFIG_XTENSA_KERNEL_CPU_PTR_SR, cpu0);
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#endif
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#if !defined(CONFIG_XTENSA_ASM2) && XCHAL_CP_NUM > 0
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