michaelh/zephyr
1
0
Fork 0
Code Releases Activity

intel_adsp: ace30: Bring up ACE 3.0 (WCL)

Browse source 
This commit adds definition of ACE 3.0 Wildcat Lake board

Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
This commit is contained in:
Adrian Bonislawski 2025-05-13 12:34:00 +02:00 • committed by Benjamin Cabé
commit 7918839ddd
11 changed files with 872 additions and 5 deletions
Download patch file Download diff file Expand all files Collapse all files

2
boards/intel/adsp/Kconfig.intel_adsp
View file

@ -10,3 +10,5 @@ config BOARD_INTEL_ADSP
select SOC_INTEL_ACE20_LNL if BOARD_INTEL_ADSP_ACE20_LNL_SIM
select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_PTL
select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_PTL_SIM
select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_WCL
select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_WCL_SIM

10
boards/intel/adsp/board.cmake
View file

@ -1,4 +1,4 @@
# Copyright (c) 2022-2024 Intel Corporation
# Copyright (c) 2022-2025 Intel Corporation
#
# SPDX-License-Identifier: Apache-2.0
@ -47,4 +47,12 @@ elseif(CONFIG_BOARD_INTEL_ADSP_ACE30_PTL OR CONFIG_BOARD_INTEL_ADSP_ACE30_PTL_SI
board_finalize_runner_args(intel_adsp)
elseif(CONFIG_BOARD_INTEL_ADSP_ACE30_WCL OR CONFIG_BOARD_INTEL_ADSP_ACE30_WCL_SIM)
board_set_rimage_target(wcl)
set(RIMAGE_SIGN_KEY "otc_private_key.pem" CACHE STRING "default rimage key")
board_finalize_runner_args(intel_adsp)
endif()

3
boards/intel/adsp/board.yml
View file

@ -17,3 +17,6 @@ boards:
- name: 'ptl'
variants:
- name: 'sim'
- name: 'wcl'
variants:
- name: 'sim'

19
boards/intel/adsp/intel_adsp_ace30_wcl.dts Normal file
View file

@ -0,0 +1,19 @@
/*
* Copyright (c) 2025 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <intel/intel_adsp_ace30_wcl.dtsi>
/ {
model = "intel_adsp_ace30_wcl";
compatible = "intel";
chosen {
zephyr,sram = &sram0;
zephyr,console = &mem_window3;
};
};

10
boards/intel/adsp/intel_adsp_ace30_wcl_defconfig Normal file
View file

@ -0,0 +1,10 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_GEN_ISR_TABLES=y
CONFIG_GEN_IRQ_VECTOR_TABLE=n
CONFIG_BUILD_OUTPUT_BIN=n
CONFIG_DAI_SSP_HAS_POWER_CONTROL=y
CONFIG_DCACHE_LINE_SIZE=64

19
boards/intel/adsp/intel_adsp_ace30_wcl_sim.dts Normal file
View file

@ -0,0 +1,19 @@
/*
* Copyright (c) 2025 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
/dts-v1/;
#include <intel/intel_adsp_ace30_wcl.dtsi>
/ {
model = "intel_adsp_ace30_wcl_sim";
compatible = "intel";
chosen {
zephyr,sram = &sram0;
zephyr,console = &mem_window3;
};
};

13
boards/intel/adsp/intel_adsp_ace30_wcl_sim_defconfig Normal file
View file

@ -0,0 +1,13 @@
# SPDX-License-Identifier: Apache-2.0
CONFIG_INTEL_ADSP_SIM=y
CONFIG_INTEL_ADSP_SIM_NO_SECONDARY_CORE_FLOW=y
CONFIG_GEN_ISR_TABLES=y
CONFIG_GEN_IRQ_VECTOR_TABLE=n
CONFIG_BUILD_OUTPUT_BIN=n
CONFIG_DAI_SSP_HAS_POWER_CONTROL=y
CONFIG_DCACHE_LINE_SIZE=64

14
boards/intel/adsp/twister.yaml
View file

@ -12,6 +12,20 @@ testing:
- bluetooth
- mcumgr
variants:
intel_adsp/ace30/wcl:
toolchain:
- xt-clang
- zephyr
intel_adsp/ace30/wcl/sim:
type: sim
simulation:
- name: custom
exec: acesim
toolchain:
- xt-clang
- zephyr
testing:
timeout_multiplier: 8
intel_adsp/ace30/ptl:
toolchain:
- xt-clang

776
dts/xtensa/intel/intel_adsp_ace30_wcl.dtsi Normal file
View file

@ -0,0 +1,776 @@
/*
* Copyright (c) 2025 Intel Corporation
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <xtensa/xtensa.dtsi>
#include <mem.h>
/ {
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "cdns,tensilica-xtensa-lx7";
reg = <0>;
cpu-power-states = <&d0i3 &d3>;
i-cache-line-size = <64>;
d-cache-line-size = <64>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "cdns,tensilica-xtensa-lx7";
reg = <1>;
cpu-power-states = <&d0i3 &d3>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "cdns,tensilica-xtensa-lx7";
reg = <2>;
cpu-power-states = <&d0i3 &d3>;
};
power-states {
d0i3: idle {
compatible = "zephyr,power-state";
power-state-name = "runtime-idle";
min-residency-us = <200>;
exit-latency-us = <100>;
};
/* PM_STATE_SOFT_OFF can be entered only by calling pm_state_force.
* The procedure is triggered by IPC from the HOST (SET_DX).
*/
d3: off {
compatible = "zephyr,power-state";
power-state-name = "soft-off";
min-residency-us = <0>;
exit-latency-us = <0>;
status = "disabled";
};
};
};
sram0: memory@a0020000 {
device_type = "memory";
compatible = "mmio-sram";
reg = <0xa0020000 DT_SIZE_K(3456)>;
};
sram0virtual: virtualmemory@a0020000 {
device_type = "memory";
compatible = "mmio-sram";
reg = <0xa0020000 DT_SIZE_K(8192)>;
};
sram1: memory@a0000000 {
device_type = "memory";
compatible = "mmio-sram";
reg = <0xa0000000 DT_SIZE_K(64)>;
};
sysclk: system-clock {
compatible = "fixed-clock";
clock-frequency = <38400000>;
#clock-cells = <0>;
};
clkctl: clkctl {
compatible = "intel,adsp-shim-clkctl";
adsp-clkctl-clk-wovcro = <0>;
adsp-clkctl-clk-ipll = <1>;
adsp-clkctl-freq-enc = <0xc 0x4>;
adsp-clkctl-freq-mask = <0x0 0x0>;
adsp-clkctl-freq-default = <1>;
adsp-clkctl-freq-lowest = <0>;
wovcro-supported;
};
audioclk: audio-clock {
compatible = "fixed-clock";
clock-frequency = <24576000>;
#clock-cells = <0>;
};
pllclk: pll-clock {
compatible = "fixed-clock";
clock-frequency = <96000000>;
#clock-cells = <0>;
};
IMR1: memory@A1000000 {
compatible = "intel,adsp-imr";
reg = <0xA1000000 DT_SIZE_M(16)>;
block-size = <0x1000>;
zephyr,memory-region = "IMR1";
};
soc {
l1ccap: l1ccap@3fe80080 {
compatible = "intel,adsp-l1ccap";
reg = <0x3fe80080 0x4>;
};
l1ccfg: l1ccfg@3fe80084 {
compatible = "intel,adsp-l1ccfg";
reg = <0x3fe80084 0x4>;
};
l1pcfg: l1pcfg@3fe80088 {
compatible = "intel,adsp-l1pcfg";
reg = <0x3fe80088 0x4>;
};
hsbcap: hsbcap@71d00 {
compatible = "intel,adsp-hsbcap";
reg = <0x71d00 0x4>;
};
lsbpm: lsbpm@71d80 {
compatible = "intel,adsp-lsbpm";
reg = <0x71d80 0x0008>;
};
hsbpm: hsbpm@17a800 {
compatible = "intel,adsp-hsbpm";
reg = <0x17a800 0x0008>;
};
core_intc: core_intc@0 {
compatible = "cdns,xtensa-core-intc";
reg = <0x00 0x400>;
interrupt-controller;
#interrupt-cells = <3>;
};
hdamlddmic: hdamlddmic@cc0 {
compatible = "intel,adsp-hda-dmic-cap";
reg = <0xcc0 0x40>;
status = "okay";
};
dmic0: dai-dmic0@10100 {
compatible = "intel,dai-dmic";
reg = <0x10100 0x8000>;
shim = <0x10000>;
fifo = <0x0008>;
interrupts = <0x08 0 0>;
interrupt-parent = <&ace_intc>;
power-domains = <&hub_ulp_domain>;
zephyr,pm-device-runtime-auto;
};
dmic1: dai-dmic1@10100 {
compatible = "intel,dai-dmic";
reg = <0x10100 0x8000>;
shim = <0x10000>;
fifo = <0x0108>;
interrupts = <0x08 0 0>;
interrupt-parent = <&ace_intc>;
power-domains = <&hub_ulp_domain>;
zephyr,pm-device-runtime-auto;
};
dmicvss: dmicvss@16000 {
compatible = "intel,adsp-dmic-vss";
reg = <0x16000 0x2000>;
status = "okay";
};
sspbase: ssp_base@28000 {
compatible = "intel,ssp-sspbase";
reg = <0x28000 0x1000>;
};
hdamlssp: hdamlssp@d00 {
compatible = "intel,adsp-hda-ssp-cap";
reg = <0xD00 0x40>;
status = "okay";
};
ssp0: ssp@28100 {
compatible = "intel,ssp";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x00028100 0x1000
0x00079C00 0x200>;
i2svss = <0x00028C00 0x1000>;
interrupts = <0x00 0 0>;
interrupt-parent = <&ace_intc>;
dmas = <&hda_link_out 1
&hda_link_in 1>;
dma-names = "tx", "rx";
ssp-index = <0>;
status = "okay";
ssp00: ssp@0 {
compatible = "intel,ssp-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
reg = <0x0>;
status = "okay";
};
ssp01: ssp@1 {
compatible = "intel,ssp-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
reg = <0x1>;
status = "okay";
};
ssp02: ssp@2 {
compatible = "intel,ssp-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
reg = <0x2>;
status = "okay";
};
ssp03: ssp@3 {
compatible = "intel,ssp-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
reg = <0x3>;
status = "okay";
};
ssp04: ssp@4 {
compatible = "intel,ssp-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
reg = <0x4>;
status = "okay";
};
ssp05: ssp@5 {
compatible = "intel,ssp-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
reg = <0x5>;
status = "okay";
};
ssp06: ssp@6 {
compatible = "intel,ssp-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
reg = <0x6>;
status = "okay";
};
ssp07: ssp@7 {
compatible = "intel,ssp-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
reg = <0x7>;
status = "okay";
};
};
ssp1: ssp@29100 {
compatible = "intel,ssp";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x00029100 0x1000
0x00079C00 0x200>;
i2svss = <0x00029C00 0x1000>;
interrupts = <0x01 0 0>;
interrupt-parent = <&ace_intc>;
dmas = <&hda_link_out 2
&hda_link_in 2>;
dma-names = "tx", "rx";
ssp-index = <1>;
status = "okay";
ssp10: ssp@10 {
compatible = "intel,ssp-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
reg = <0x10>;
status = "okay";
};
ssp11: ssp@11 {
compatible = "intel,ssp-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
reg = <0x11>;
status = "okay";
};
ssp12: ssp@12 {
compatible = "intel,ssp-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
reg = <0x12>;
status = "okay";
};
ssp13: ssp@13 {
compatible = "intel,ssp-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
reg = <0x13>;
status = "okay";
};
ssp14: ssp@14 {
compatible = "intel,ssp-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
reg = <0x14>;
status = "okay";
};
ssp15: ssp@15 {
compatible = "intel,ssp-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
reg = <0x15>;
status = "okay";
};
ssp16: ssp@16 {
compatible = "intel,ssp-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
reg = <0x16>;
status = "okay";
};
ssp17: ssp@17 {
compatible = "intel,ssp-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
reg = <0x17>;
status = "okay";
};
};
ssp2: ssp@2a100 {
compatible = "intel,ssp";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x0002a100 0x1000
0x00079C00 0x200>;
i2svss = <0x0002AC00 0x1000>;
interrupts = <0x02 0 0>;
interrupt-parent = <&ace_intc>;
dmas = <&hda_link_out 3
&hda_link_in 3>;
dma-names = "tx", "rx";
ssp-index = <2>;
status = "okay";
ssp20: ssp@20 {
compatible = "intel,ssp-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
reg = <0x20>;
status = "okay";
};
ssp21: ssp@21 {
compatible = "intel,ssp-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
reg = <0x21>;
status = "okay";
};
ssp22: ssp@22 {
compatible = "intel,ssp-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
reg = <0x22>;
status = "okay";
};
ssp23: ssp@23 {
compatible = "intel,ssp-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
reg = <0x23>;
status = "okay";
};
ssp24: ssp@24 {
compatible = "intel,ssp-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
reg = <0x24>;
status = "okay";
};
ssp25: ssp@25 {
compatible = "intel,ssp-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
reg = <0x25>;
status = "okay";
};
ssp26: ssp@26 {
compatible = "intel,ssp-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
reg = <0x26>;
status = "okay";
};
ssp27: ssp@27 {
compatible = "intel,ssp-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
reg = <0x27>;
status = "okay";
};
};
mic_privacy: mic-prv@71a40 {
compatible = "intel,adsp-mic-privacy";
reg = <0x71a40 0x8000>;
interrupts = <29 0 0>;
interrupt-parent = <&ace_intc>;
status = "okay";
};
mem_window0: mem_window@70200 {
compatible = "intel,adsp-mem-window";
reg = <0x70200 0x8>;
offset = <0x4000>;
memory = <&sram0>;
initialize;
read-only;
};
mem_window1: mem_window@70208 {
compatible = "intel,adsp-mem-window";
reg = <0x70208 0x8>;
memory = <&sram0>;
};
mem_window2: mem_window@70210 {
compatible = "intel,adsp-mem-window";
reg = <0x70210 0x8>;
memory = <&sram0>;
};
mem_window3: mem_window@70218 {
compatible = "intel,adsp-mem-window";
reg = <0x70218 0x8>;
memory = <&sram0>;
read-only;
};
adsp_idc: ace_idc@92000 {
compatible = "intel,adsp-idc";
reg = <0x92000 0x0400>;
interrupts = <24 0 0>;
interrupt-parent = <&ace_intc>;
};
dfpmcch: dfpmcch@71ac0 {
compatible = "intel,adsp-dfpmcch";
reg = <0x00071ac0 0x40>;
};
dfpmccu: dfpmccu@71b00 {
compatible = "intel,adsp-dfpmccu";
reg = <0x71b00 0x100>;
hub_ulp_domain: hub_ulp_domain {
compatible = "intel,adsp-power-domain";
bit-position = <15>;
#power-domain-cells = <0>;
};
ml0_domain: ml0_domain {
compatible = "intel,adsp-power-domain";
bit-position = <12>;
#power-domain-cells = <0>;
};
io1_domain: io1_domain {
compatible = "intel,adsp-power-domain";
bit-position = <9>;
#power-domain-cells = <0>;
};
io0_domain: io0_domain {
compatible = "intel,adsp-power-domain";
bit-position = <8>;
#power-domain-cells = <0>;
};
hub_hp_domain: hub_hpp_domain {
compatible = "intel,adsp-power-domain";
bit-position = <6>;
#power-domain-cells = <0>;
};
hst_domain: hst_domain {
compatible = "intel,adsp-power-domain";
bit-position = <5>;
#power-domain-cells = <0>;
};
};
shim: shim@71f00 {
compatible = "intel,cavs-shim";
reg = <0x71f00 0x100>;
};
tts: tts@72000 {
compatible = "intel,adsp-tts";
reg = <0x72000 0x70>;
status = "okay";
};
ace_rtc_counter: ace_rtc_counter@72008 {
compatible = "intel,ace-rtc-counter";
reg = <0x72008 0x0064>;
};
ace_timestamp: ace_timestamp@72040 {
compatible = "intel,ace-timestamp";
reg = <0x72040 0x0032>;
};
ace_art_counter: ace_art_counter@72058 {
compatible = "intel,ace-art-counter";
reg = <0x72058 0x0064>;
};
hda_host_out: dma@72800 {
compatible = "intel,adsp-hda-host-out";
#dma-cells = <1>;
reg = <0x00072800 0x40>;
dma-channels = <9>;
dma-buf-addr-alignment = <128>;
dma-buf-size-alignment = <32>;
dma-copy-alignment = <32>;
power-domains = <&hst_domain>;
zephyr,pm-device-runtime-auto;
interrupts = <13 0 0>;
interrupt-parent = <&ace_intc>;
status = "okay";
};
hda_host_in: dma@72c00 {
compatible = "intel,adsp-hda-host-in";
#dma-cells = <1>;
reg = <0x00072c00 0x40>;
dma-channels = <11>;
dma-buf-addr-alignment = <128>;
dma-buf-size-alignment = <32>;
dma-copy-alignment = <32>;
power-domains = <&hst_domain>;
zephyr,pm-device-runtime-auto;
interrupts = <12 0 0>;
interrupt-parent = <&ace_intc>;
status = "okay";
};
adsp_host_ipc: ace_host_ipc@73000 {
compatible = "intel,adsp-host-ipc";
status = "okay";
reg = <0x73000 0x30>;
interrupts = <0 0 0>;
interrupt-parent = <&ace_intc>;
};
hda_link_out: dma@79400 {
compatible = "intel,adsp-hda-link-out";
#dma-cells = <1>;
reg = <0x00079400 0x40>;
dma-channels = <9>;
dma-buf-addr-alignment = <128>;
dma-buf-size-alignment = <32>;
dma-copy-alignment = <32>;
power-domains = <&hub_ulp_domain>;
zephyr,pm-device-runtime-auto;
status = "okay";
};
hda_link_in: dma@79800 {
compatible = "intel,adsp-hda-link-in";
#dma-cells = <1>;
reg = <0x00079800 0x40>;
dma-channels = <11>;
dma-buf-addr-alignment = <128>;
dma-buf-size-alignment = <32>;
dma-copy-alignment = <32>;
power-domains = <&hub_ulp_domain>;
zephyr,pm-device-runtime-auto;
status = "okay";
};
/* This is actually an array of per-core designware
* controllers, but the special setup and extra
* masking layer makes it easier for MTL to handle
* this internally.
*/
ace_intc: ace_intc@94000 {
compatible = "intel,ace-intc";
reg = <0x94000 0xc00>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <4 0 0>;
num-irqs = <30>;
interrupt-parent = <&core_intc>;
};
tlb: tlb@17e000 {
compatible = "intel,adsp-mtl-tlb";
reg = <0x17e000 0x1000>;
paddr-size = <12>;
exec-bit-idx = <14>;
write-bit-idx= <15>;
};
timer: timer {
compatible = "intel,adsp-timer";
syscon = <&tts>;
};
};
hdas {
#address-cells = <1>;
#size-cells = <0>;
hda0: hda@0 {
compatible = "intel,hda-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
status = "okay";
reg = <0>;
};
hda1: hda@1 {
compatible = "intel,hda-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
status = "okay";
reg = <1>;
};
hda2: hda@2 {
compatible = "intel,hda-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
status = "okay";
reg = <2>;
};
hda3: hda@3 {
compatible = "intel,hda-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
status = "okay";
reg = <3>;
};
hda4: hda@4 {
compatible = "intel,hda-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
status = "okay";
reg = <4>;
};
hda5: hda@5 {
compatible = "intel,hda-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
status = "okay";
reg = <5>;
};
hda6: hda@6 {
compatible = "intel,hda-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
status = "okay";
reg = <6>;
};
hda7: hda@7 {
compatible = "intel,hda-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
status = "okay";
reg = <7>;
};
hda8: hda@8 {
compatible = "intel,hda-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
status = "okay";
reg = <8>;
};
hda9: hda@9 {
compatible = "intel,hda-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
status = "okay";
reg = <9>;
};
hda10: hda@a {
compatible = "intel,hda-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
status = "okay";
reg = <0x0a>;
};
hda11: hda@b {
compatible = "intel,hda-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
status = "okay";
reg = <0x0b>;
};
hda12: hda@c {
compatible = "intel,hda-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
status = "okay";
reg = <0x0c>;
};
hda13: hda@d {
compatible = "intel,hda-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
status = "okay";
reg = <0x0d>;
};
hda14: hda@e {
compatible = "intel,hda-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
status = "okay";
reg = <0x0e>;
};
hda15: hda@f {
compatible = "intel,hda-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
status = "okay";
reg = <0x0f>;
};
hda16: hda@10 {
compatible = "intel,hda-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
status = "okay";
reg = <0x10>;
};
hda17: hda@11 {
compatible = "intel,hda-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
status = "okay";
reg = <0x11>;
};
hda18: hda@12 {
compatible = "intel,hda-dai";
power-domains = <&io0_domain>;
zephyr,pm-device-runtime-auto;
status = "okay";
reg = <0x12>;
};
};
};

9
soc/intel/intel_adsp/ace/Kconfig.defconfig.ace30
View file

@ -5,15 +5,18 @@
if SOC_INTEL_ACE30
config MP_MAX_NUM_CPUS
default 5
default 5 if BOARD_INTEL_ADSP_ACE30_PTL || BOARD_INTEL_ADSP_ACE30_PTL_SIM
default 3 if BOARD_INTEL_ADSP_ACE30_WCL || BOARD_INTEL_ADSP_ACE30_WCL_SIM
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 442368000 if XTENSA_TIMER
default 614400000 if XTENSA_TIMER && BOARD_INTEL_ADSP_ACE30_WCL
default 442368000 if XTENSA_TIMER && BOARD_INTEL_ADSP_ACE30_PTL
default 1000000 if INTEL_ADSP_SIM
default 38400000 if INTEL_ADSP_TIMER
config XTENSA_CCOUNT_HZ
default 442368000
default 614400000 if BOARD_INTEL_ADSP_ACE30_WCL || BOARD_INTEL_ADSP_ACE30_WCL_SIM
default 442368000 if BOARD_INTEL_ADSP_ACE30_PTL || BOARD_INTEL_ADSP_ACE30_PTL_SIM
config CPU_HAS_MMU
def_bool y

2
soc/intel/intel_adsp/common/clk.c
View file

@ -96,7 +96,7 @@ void adsp_clock_init(void)
} else {
platform_lowest_freq_idx = ADSP_CPU_CLOCK_FREQ_IPLL;
}
#if CONFIG_SOC_INTEL_ACE30
#if defined(CONFIG_BOARD_INTEL_ADSP_ACE30_PTL) || defined(CONFIG_BOARD_INTEL_ADSP_ACE30_PTL_SIM)
/* Set the Cardinal clock divider to 18 to get 24.576MHz */
ACE_DfPMCCU.dfcrodiv &= ACE_CRODIV_CARCDS_MASK;
ACE_DfPMCCU.dfcrodiv |= ACE_CRODIV_CARCDS(0x12);