intel_adsp: ace30: Bring up ACE 3.0 (WCL)
This commit adds definition of ACE 3.0 Wildcat Lake board Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
This commit is contained in:
parent
a045eaebad
commit
7918839ddd
11 changed files with 872 additions and 5 deletions
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@ -10,3 +10,5 @@ config BOARD_INTEL_ADSP
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select SOC_INTEL_ACE20_LNL if BOARD_INTEL_ADSP_ACE20_LNL_SIM
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select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_PTL
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select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_PTL_SIM
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select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_WCL
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select SOC_INTEL_ACE30 if BOARD_INTEL_ADSP_ACE30_WCL_SIM
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@ -1,4 +1,4 @@
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# Copyright (c) 2022-2024 Intel Corporation
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# Copyright (c) 2022-2025 Intel Corporation
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#
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# SPDX-License-Identifier: Apache-2.0
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@ -47,4 +47,12 @@ elseif(CONFIG_BOARD_INTEL_ADSP_ACE30_PTL OR CONFIG_BOARD_INTEL_ADSP_ACE30_PTL_SI
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board_finalize_runner_args(intel_adsp)
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elseif(CONFIG_BOARD_INTEL_ADSP_ACE30_WCL OR CONFIG_BOARD_INTEL_ADSP_ACE30_WCL_SIM)
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board_set_rimage_target(wcl)
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set(RIMAGE_SIGN_KEY "otc_private_key.pem" CACHE STRING "default rimage key")
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board_finalize_runner_args(intel_adsp)
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endif()
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@ -17,3 +17,6 @@ boards:
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- name: 'ptl'
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variants:
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- name: 'sim'
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- name: 'wcl'
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variants:
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- name: 'sim'
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19
boards/intel/adsp/intel_adsp_ace30_wcl.dts
Normal file
19
boards/intel/adsp/intel_adsp_ace30_wcl.dts
Normal file
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@ -0,0 +1,19 @@
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/*
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* Copyright (c) 2025 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <intel/intel_adsp_ace30_wcl.dtsi>
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/ {
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model = "intel_adsp_ace30_wcl";
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compatible = "intel";
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chosen {
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zephyr,sram = &sram0;
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zephyr,console = &mem_window3;
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};
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};
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10
boards/intel/adsp/intel_adsp_ace30_wcl_defconfig
Normal file
10
boards/intel/adsp/intel_adsp_ace30_wcl_defconfig
Normal file
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@ -0,0 +1,10 @@
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_GEN_ISR_TABLES=y
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CONFIG_GEN_IRQ_VECTOR_TABLE=n
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CONFIG_BUILD_OUTPUT_BIN=n
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CONFIG_DAI_SSP_HAS_POWER_CONTROL=y
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CONFIG_DCACHE_LINE_SIZE=64
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19
boards/intel/adsp/intel_adsp_ace30_wcl_sim.dts
Normal file
19
boards/intel/adsp/intel_adsp_ace30_wcl_sim.dts
Normal file
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@ -0,0 +1,19 @@
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/*
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* Copyright (c) 2025 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/dts-v1/;
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#include <intel/intel_adsp_ace30_wcl.dtsi>
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/ {
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model = "intel_adsp_ace30_wcl_sim";
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compatible = "intel";
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chosen {
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zephyr,sram = &sram0;
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zephyr,console = &mem_window3;
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};
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};
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13
boards/intel/adsp/intel_adsp_ace30_wcl_sim_defconfig
Normal file
13
boards/intel/adsp/intel_adsp_ace30_wcl_sim_defconfig
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@ -0,0 +1,13 @@
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_INTEL_ADSP_SIM=y
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CONFIG_INTEL_ADSP_SIM_NO_SECONDARY_CORE_FLOW=y
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CONFIG_GEN_ISR_TABLES=y
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CONFIG_GEN_IRQ_VECTOR_TABLE=n
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CONFIG_BUILD_OUTPUT_BIN=n
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CONFIG_DAI_SSP_HAS_POWER_CONTROL=y
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CONFIG_DCACHE_LINE_SIZE=64
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@ -12,6 +12,20 @@ testing:
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- bluetooth
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- mcumgr
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variants:
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intel_adsp/ace30/wcl:
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toolchain:
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- xt-clang
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- zephyr
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intel_adsp/ace30/wcl/sim:
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type: sim
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simulation:
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- name: custom
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exec: acesim
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toolchain:
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- xt-clang
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- zephyr
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testing:
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timeout_multiplier: 8
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intel_adsp/ace30/ptl:
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toolchain:
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- xt-clang
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776
dts/xtensa/intel/intel_adsp_ace30_wcl.dtsi
Normal file
776
dts/xtensa/intel/intel_adsp_ace30_wcl.dtsi
Normal file
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@ -0,0 +1,776 @@
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/*
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* Copyright (c) 2025 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <xtensa/xtensa.dtsi>
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#include <mem.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "cdns,tensilica-xtensa-lx7";
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reg = <0>;
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cpu-power-states = <&d0i3 &d3>;
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i-cache-line-size = <64>;
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d-cache-line-size = <64>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "cdns,tensilica-xtensa-lx7";
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reg = <1>;
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cpu-power-states = <&d0i3 &d3>;
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};
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cpu2: cpu@2 {
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device_type = "cpu";
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compatible = "cdns,tensilica-xtensa-lx7";
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reg = <2>;
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cpu-power-states = <&d0i3 &d3>;
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};
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power-states {
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d0i3: idle {
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compatible = "zephyr,power-state";
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power-state-name = "runtime-idle";
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min-residency-us = <200>;
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exit-latency-us = <100>;
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};
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/* PM_STATE_SOFT_OFF can be entered only by calling pm_state_force.
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* The procedure is triggered by IPC from the HOST (SET_DX).
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*/
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d3: off {
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compatible = "zephyr,power-state";
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power-state-name = "soft-off";
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min-residency-us = <0>;
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exit-latency-us = <0>;
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status = "disabled";
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};
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};
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};
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sram0: memory@a0020000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0xa0020000 DT_SIZE_K(3456)>;
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};
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sram0virtual: virtualmemory@a0020000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0xa0020000 DT_SIZE_K(8192)>;
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};
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sram1: memory@a0000000 {
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device_type = "memory";
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compatible = "mmio-sram";
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reg = <0xa0000000 DT_SIZE_K(64)>;
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};
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sysclk: system-clock {
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compatible = "fixed-clock";
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clock-frequency = <38400000>;
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#clock-cells = <0>;
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};
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clkctl: clkctl {
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compatible = "intel,adsp-shim-clkctl";
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adsp-clkctl-clk-wovcro = <0>;
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adsp-clkctl-clk-ipll = <1>;
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adsp-clkctl-freq-enc = <0xc 0x4>;
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adsp-clkctl-freq-mask = <0x0 0x0>;
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adsp-clkctl-freq-default = <1>;
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adsp-clkctl-freq-lowest = <0>;
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wovcro-supported;
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};
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audioclk: audio-clock {
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compatible = "fixed-clock";
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clock-frequency = <24576000>;
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#clock-cells = <0>;
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};
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pllclk: pll-clock {
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compatible = "fixed-clock";
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clock-frequency = <96000000>;
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#clock-cells = <0>;
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};
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IMR1: memory@A1000000 {
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compatible = "intel,adsp-imr";
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reg = <0xA1000000 DT_SIZE_M(16)>;
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block-size = <0x1000>;
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zephyr,memory-region = "IMR1";
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};
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soc {
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l1ccap: l1ccap@3fe80080 {
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compatible = "intel,adsp-l1ccap";
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reg = <0x3fe80080 0x4>;
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};
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l1ccfg: l1ccfg@3fe80084 {
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compatible = "intel,adsp-l1ccfg";
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reg = <0x3fe80084 0x4>;
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};
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l1pcfg: l1pcfg@3fe80088 {
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compatible = "intel,adsp-l1pcfg";
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reg = <0x3fe80088 0x4>;
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};
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hsbcap: hsbcap@71d00 {
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compatible = "intel,adsp-hsbcap";
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reg = <0x71d00 0x4>;
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};
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lsbpm: lsbpm@71d80 {
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compatible = "intel,adsp-lsbpm";
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reg = <0x71d80 0x0008>;
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};
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hsbpm: hsbpm@17a800 {
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compatible = "intel,adsp-hsbpm";
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reg = <0x17a800 0x0008>;
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};
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core_intc: core_intc@0 {
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compatible = "cdns,xtensa-core-intc";
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reg = <0x00 0x400>;
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interrupt-controller;
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#interrupt-cells = <3>;
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};
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hdamlddmic: hdamlddmic@cc0 {
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compatible = "intel,adsp-hda-dmic-cap";
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reg = <0xcc0 0x40>;
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status = "okay";
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};
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dmic0: dai-dmic0@10100 {
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compatible = "intel,dai-dmic";
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reg = <0x10100 0x8000>;
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shim = <0x10000>;
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fifo = <0x0008>;
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interrupts = <0x08 0 0>;
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interrupt-parent = <&ace_intc>;
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power-domains = <&hub_ulp_domain>;
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zephyr,pm-device-runtime-auto;
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};
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dmic1: dai-dmic1@10100 {
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compatible = "intel,dai-dmic";
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reg = <0x10100 0x8000>;
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shim = <0x10000>;
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fifo = <0x0108>;
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interrupts = <0x08 0 0>;
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interrupt-parent = <&ace_intc>;
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power-domains = <&hub_ulp_domain>;
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zephyr,pm-device-runtime-auto;
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};
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dmicvss: dmicvss@16000 {
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compatible = "intel,adsp-dmic-vss";
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reg = <0x16000 0x2000>;
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status = "okay";
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};
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sspbase: ssp_base@28000 {
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compatible = "intel,ssp-sspbase";
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reg = <0x28000 0x1000>;
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};
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hdamlssp: hdamlssp@d00 {
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compatible = "intel,adsp-hda-ssp-cap";
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reg = <0xD00 0x40>;
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status = "okay";
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};
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ssp0: ssp@28100 {
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compatible = "intel,ssp";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x00028100 0x1000
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0x00079C00 0x200>;
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i2svss = <0x00028C00 0x1000>;
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interrupts = <0x00 0 0>;
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interrupt-parent = <&ace_intc>;
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dmas = <&hda_link_out 1
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&hda_link_in 1>;
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dma-names = "tx", "rx";
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ssp-index = <0>;
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status = "okay";
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ssp00: ssp@0 {
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compatible = "intel,ssp-dai";
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power-domains = <&io0_domain>;
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zephyr,pm-device-runtime-auto;
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reg = <0x0>;
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status = "okay";
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};
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ssp01: ssp@1 {
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compatible = "intel,ssp-dai";
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power-domains = <&io0_domain>;
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zephyr,pm-device-runtime-auto;
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reg = <0x1>;
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status = "okay";
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};
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ssp02: ssp@2 {
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compatible = "intel,ssp-dai";
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power-domains = <&io0_domain>;
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zephyr,pm-device-runtime-auto;
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reg = <0x2>;
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status = "okay";
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};
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ssp03: ssp@3 {
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compatible = "intel,ssp-dai";
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power-domains = <&io0_domain>;
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zephyr,pm-device-runtime-auto;
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reg = <0x3>;
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status = "okay";
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};
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ssp04: ssp@4 {
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compatible = "intel,ssp-dai";
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power-domains = <&io0_domain>;
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zephyr,pm-device-runtime-auto;
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reg = <0x4>;
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status = "okay";
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};
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ssp05: ssp@5 {
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compatible = "intel,ssp-dai";
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power-domains = <&io0_domain>;
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zephyr,pm-device-runtime-auto;
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reg = <0x5>;
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status = "okay";
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};
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ssp06: ssp@6 {
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compatible = "intel,ssp-dai";
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power-domains = <&io0_domain>;
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zephyr,pm-device-runtime-auto;
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reg = <0x6>;
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status = "okay";
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};
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ssp07: ssp@7 {
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compatible = "intel,ssp-dai";
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power-domains = <&io0_domain>;
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zephyr,pm-device-runtime-auto;
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reg = <0x7>;
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status = "okay";
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};
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};
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ssp1: ssp@29100 {
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compatible = "intel,ssp";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x00029100 0x1000
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0x00079C00 0x200>;
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i2svss = <0x00029C00 0x1000>;
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interrupts = <0x01 0 0>;
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interrupt-parent = <&ace_intc>;
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dmas = <&hda_link_out 2
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&hda_link_in 2>;
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dma-names = "tx", "rx";
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ssp-index = <1>;
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status = "okay";
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ssp10: ssp@10 {
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compatible = "intel,ssp-dai";
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power-domains = <&io0_domain>;
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zephyr,pm-device-runtime-auto;
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reg = <0x10>;
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status = "okay";
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};
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ssp11: ssp@11 {
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compatible = "intel,ssp-dai";
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power-domains = <&io0_domain>;
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zephyr,pm-device-runtime-auto;
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reg = <0x11>;
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status = "okay";
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};
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ssp12: ssp@12 {
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compatible = "intel,ssp-dai";
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power-domains = <&io0_domain>;
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zephyr,pm-device-runtime-auto;
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reg = <0x12>;
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status = "okay";
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};
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ssp13: ssp@13 {
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compatible = "intel,ssp-dai";
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power-domains = <&io0_domain>;
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zephyr,pm-device-runtime-auto;
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reg = <0x13>;
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status = "okay";
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};
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ssp14: ssp@14 {
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compatible = "intel,ssp-dai";
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power-domains = <&io0_domain>;
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zephyr,pm-device-runtime-auto;
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reg = <0x14>;
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status = "okay";
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};
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ssp15: ssp@15 {
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compatible = "intel,ssp-dai";
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power-domains = <&io0_domain>;
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zephyr,pm-device-runtime-auto;
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reg = <0x15>;
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status = "okay";
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};
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ssp16: ssp@16 {
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compatible = "intel,ssp-dai";
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power-domains = <&io0_domain>;
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zephyr,pm-device-runtime-auto;
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reg = <0x16>;
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status = "okay";
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};
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ssp17: ssp@17 {
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compatible = "intel,ssp-dai";
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power-domains = <&io0_domain>;
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zephyr,pm-device-runtime-auto;
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reg = <0x17>;
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status = "okay";
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};
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};
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ssp2: ssp@2a100 {
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||||
compatible = "intel,ssp";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x0002a100 0x1000
|
||||
0x00079C00 0x200>;
|
||||
i2svss = <0x0002AC00 0x1000>;
|
||||
interrupts = <0x02 0 0>;
|
||||
interrupt-parent = <&ace_intc>;
|
||||
dmas = <&hda_link_out 3
|
||||
&hda_link_in 3>;
|
||||
dma-names = "tx", "rx";
|
||||
ssp-index = <2>;
|
||||
status = "okay";
|
||||
|
||||
ssp20: ssp@20 {
|
||||
compatible = "intel,ssp-dai";
|
||||
power-domains = <&io0_domain>;
|
||||
zephyr,pm-device-runtime-auto;
|
||||
reg = <0x20>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ssp21: ssp@21 {
|
||||
compatible = "intel,ssp-dai";
|
||||
power-domains = <&io0_domain>;
|
||||
zephyr,pm-device-runtime-auto;
|
||||
reg = <0x21>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ssp22: ssp@22 {
|
||||
compatible = "intel,ssp-dai";
|
||||
power-domains = <&io0_domain>;
|
||||
zephyr,pm-device-runtime-auto;
|
||||
reg = <0x22>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ssp23: ssp@23 {
|
||||
compatible = "intel,ssp-dai";
|
||||
power-domains = <&io0_domain>;
|
||||
zephyr,pm-device-runtime-auto;
|
||||
reg = <0x23>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ssp24: ssp@24 {
|
||||
compatible = "intel,ssp-dai";
|
||||
power-domains = <&io0_domain>;
|
||||
zephyr,pm-device-runtime-auto;
|
||||
reg = <0x24>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ssp25: ssp@25 {
|
||||
compatible = "intel,ssp-dai";
|
||||
power-domains = <&io0_domain>;
|
||||
zephyr,pm-device-runtime-auto;
|
||||
reg = <0x25>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ssp26: ssp@26 {
|
||||
compatible = "intel,ssp-dai";
|
||||
power-domains = <&io0_domain>;
|
||||
zephyr,pm-device-runtime-auto;
|
||||
reg = <0x26>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ssp27: ssp@27 {
|
||||
compatible = "intel,ssp-dai";
|
||||
power-domains = <&io0_domain>;
|
||||
zephyr,pm-device-runtime-auto;
|
||||
reg = <0x27>;
|
||||
status = "okay";
|
||||
};
|
||||
};
|
||||
|
||||
mic_privacy: mic-prv@71a40 {
|
||||
compatible = "intel,adsp-mic-privacy";
|
||||
reg = <0x71a40 0x8000>;
|
||||
interrupts = <29 0 0>;
|
||||
interrupt-parent = <&ace_intc>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mem_window0: mem_window@70200 {
|
||||
compatible = "intel,adsp-mem-window";
|
||||
reg = <0x70200 0x8>;
|
||||
offset = <0x4000>;
|
||||
memory = <&sram0>;
|
||||
initialize;
|
||||
read-only;
|
||||
};
|
||||
|
||||
mem_window1: mem_window@70208 {
|
||||
compatible = "intel,adsp-mem-window";
|
||||
reg = <0x70208 0x8>;
|
||||
memory = <&sram0>;
|
||||
};
|
||||
|
||||
mem_window2: mem_window@70210 {
|
||||
compatible = "intel,adsp-mem-window";
|
||||
reg = <0x70210 0x8>;
|
||||
memory = <&sram0>;
|
||||
};
|
||||
|
||||
mem_window3: mem_window@70218 {
|
||||
compatible = "intel,adsp-mem-window";
|
||||
reg = <0x70218 0x8>;
|
||||
memory = <&sram0>;
|
||||
read-only;
|
||||
};
|
||||
|
||||
adsp_idc: ace_idc@92000 {
|
||||
compatible = "intel,adsp-idc";
|
||||
reg = <0x92000 0x0400>;
|
||||
interrupts = <24 0 0>;
|
||||
interrupt-parent = <&ace_intc>;
|
||||
};
|
||||
|
||||
dfpmcch: dfpmcch@71ac0 {
|
||||
compatible = "intel,adsp-dfpmcch";
|
||||
reg = <0x00071ac0 0x40>;
|
||||
};
|
||||
|
||||
dfpmccu: dfpmccu@71b00 {
|
||||
compatible = "intel,adsp-dfpmccu";
|
||||
reg = <0x71b00 0x100>;
|
||||
|
||||
hub_ulp_domain: hub_ulp_domain {
|
||||
compatible = "intel,adsp-power-domain";
|
||||
bit-position = <15>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
ml0_domain: ml0_domain {
|
||||
compatible = "intel,adsp-power-domain";
|
||||
bit-position = <12>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
io1_domain: io1_domain {
|
||||
compatible = "intel,adsp-power-domain";
|
||||
bit-position = <9>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
io0_domain: io0_domain {
|
||||
compatible = "intel,adsp-power-domain";
|
||||
bit-position = <8>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
hub_hp_domain: hub_hpp_domain {
|
||||
compatible = "intel,adsp-power-domain";
|
||||
bit-position = <6>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
hst_domain: hst_domain {
|
||||
compatible = "intel,adsp-power-domain";
|
||||
bit-position = <5>;
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
shim: shim@71f00 {
|
||||
compatible = "intel,cavs-shim";
|
||||
reg = <0x71f00 0x100>;
|
||||
};
|
||||
|
||||
tts: tts@72000 {
|
||||
compatible = "intel,adsp-tts";
|
||||
reg = <0x72000 0x70>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
ace_rtc_counter: ace_rtc_counter@72008 {
|
||||
compatible = "intel,ace-rtc-counter";
|
||||
reg = <0x72008 0x0064>;
|
||||
};
|
||||
|
||||
ace_timestamp: ace_timestamp@72040 {
|
||||
compatible = "intel,ace-timestamp";
|
||||
reg = <0x72040 0x0032>;
|
||||
};
|
||||
|
||||
ace_art_counter: ace_art_counter@72058 {
|
||||
compatible = "intel,ace-art-counter";
|
||||
reg = <0x72058 0x0064>;
|
||||
};
|
||||
|
||||
hda_host_out: dma@72800 {
|
||||
compatible = "intel,adsp-hda-host-out";
|
||||
#dma-cells = <1>;
|
||||
reg = <0x00072800 0x40>;
|
||||
dma-channels = <9>;
|
||||
dma-buf-addr-alignment = <128>;
|
||||
dma-buf-size-alignment = <32>;
|
||||
dma-copy-alignment = <32>;
|
||||
power-domains = <&hst_domain>;
|
||||
zephyr,pm-device-runtime-auto;
|
||||
interrupts = <13 0 0>;
|
||||
interrupt-parent = <&ace_intc>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
hda_host_in: dma@72c00 {
|
||||
compatible = "intel,adsp-hda-host-in";
|
||||
#dma-cells = <1>;
|
||||
reg = <0x00072c00 0x40>;
|
||||
dma-channels = <11>;
|
||||
dma-buf-addr-alignment = <128>;
|
||||
dma-buf-size-alignment = <32>;
|
||||
dma-copy-alignment = <32>;
|
||||
power-domains = <&hst_domain>;
|
||||
zephyr,pm-device-runtime-auto;
|
||||
interrupts = <12 0 0>;
|
||||
interrupt-parent = <&ace_intc>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
adsp_host_ipc: ace_host_ipc@73000 {
|
||||
compatible = "intel,adsp-host-ipc";
|
||||
status = "okay";
|
||||
reg = <0x73000 0x30>;
|
||||
interrupts = <0 0 0>;
|
||||
interrupt-parent = <&ace_intc>;
|
||||
};
|
||||
|
||||
hda_link_out: dma@79400 {
|
||||
compatible = "intel,adsp-hda-link-out";
|
||||
#dma-cells = <1>;
|
||||
reg = <0x00079400 0x40>;
|
||||
dma-channels = <9>;
|
||||
dma-buf-addr-alignment = <128>;
|
||||
dma-buf-size-alignment = <32>;
|
||||
dma-copy-alignment = <32>;
|
||||
power-domains = <&hub_ulp_domain>;
|
||||
zephyr,pm-device-runtime-auto;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
hda_link_in: dma@79800 {
|
||||
compatible = "intel,adsp-hda-link-in";
|
||||
#dma-cells = <1>;
|
||||
reg = <0x00079800 0x40>;
|
||||
dma-channels = <11>;
|
||||
dma-buf-addr-alignment = <128>;
|
||||
dma-buf-size-alignment = <32>;
|
||||
dma-copy-alignment = <32>;
|
||||
power-domains = <&hub_ulp_domain>;
|
||||
zephyr,pm-device-runtime-auto;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* This is actually an array of per-core designware
|
||||
* controllers, but the special setup and extra
|
||||
* masking layer makes it easier for MTL to handle
|
||||
* this internally.
|
||||
*/
|
||||
ace_intc: ace_intc@94000 {
|
||||
compatible = "intel,ace-intc";
|
||||
reg = <0x94000 0xc00>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <3>;
|
||||
interrupts = <4 0 0>;
|
||||
num-irqs = <30>;
|
||||
interrupt-parent = <&core_intc>;
|
||||
};
|
||||
|
||||
tlb: tlb@17e000 {
|
||||
compatible = "intel,adsp-mtl-tlb";
|
||||
reg = <0x17e000 0x1000>;
|
||||
paddr-size = <12>;
|
||||
exec-bit-idx = <14>;
|
||||
write-bit-idx= <15>;
|
||||
};
|
||||
|
||||
timer: timer {
|
||||
compatible = "intel,adsp-timer";
|
||||
syscon = <&tts>;
|
||||
};
|
||||
};
|
||||
|
||||
hdas {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
hda0: hda@0 {
|
||||
compatible = "intel,hda-dai";
|
||||
power-domains = <&io0_domain>;
|
||||
zephyr,pm-device-runtime-auto;
|
||||
status = "okay";
|
||||
reg = <0>;
|
||||
};
|
||||
hda1: hda@1 {
|
||||
compatible = "intel,hda-dai";
|
||||
power-domains = <&io0_domain>;
|
||||
zephyr,pm-device-runtime-auto;
|
||||
status = "okay";
|
||||
reg = <1>;
|
||||
};
|
||||
hda2: hda@2 {
|
||||
compatible = "intel,hda-dai";
|
||||
power-domains = <&io0_domain>;
|
||||
zephyr,pm-device-runtime-auto;
|
||||
status = "okay";
|
||||
reg = <2>;
|
||||
};
|
||||
hda3: hda@3 {
|
||||
compatible = "intel,hda-dai";
|
||||
power-domains = <&io0_domain>;
|
||||
zephyr,pm-device-runtime-auto;
|
||||
status = "okay";
|
||||
reg = <3>;
|
||||
};
|
||||
hda4: hda@4 {
|
||||
compatible = "intel,hda-dai";
|
||||
power-domains = <&io0_domain>;
|
||||
zephyr,pm-device-runtime-auto;
|
||||
status = "okay";
|
||||
reg = <4>;
|
||||
};
|
||||
hda5: hda@5 {
|
||||
compatible = "intel,hda-dai";
|
||||
power-domains = <&io0_domain>;
|
||||
zephyr,pm-device-runtime-auto;
|
||||
status = "okay";
|
||||
reg = <5>;
|
||||
};
|
||||
hda6: hda@6 {
|
||||
compatible = "intel,hda-dai";
|
||||
power-domains = <&io0_domain>;
|
||||
zephyr,pm-device-runtime-auto;
|
||||
status = "okay";
|
||||
reg = <6>;
|
||||
};
|
||||
hda7: hda@7 {
|
||||
compatible = "intel,hda-dai";
|
||||
power-domains = <&io0_domain>;
|
||||
zephyr,pm-device-runtime-auto;
|
||||
status = "okay";
|
||||
reg = <7>;
|
||||
};
|
||||
hda8: hda@8 {
|
||||
compatible = "intel,hda-dai";
|
||||
power-domains = <&io0_domain>;
|
||||
zephyr,pm-device-runtime-auto;
|
||||
status = "okay";
|
||||
reg = <8>;
|
||||
};
|
||||
hda9: hda@9 {
|
||||
compatible = "intel,hda-dai";
|
||||
power-domains = <&io0_domain>;
|
||||
zephyr,pm-device-runtime-auto;
|
||||
status = "okay";
|
||||
reg = <9>;
|
||||
};
|
||||
hda10: hda@a {
|
||||
compatible = "intel,hda-dai";
|
||||
power-domains = <&io0_domain>;
|
||||
zephyr,pm-device-runtime-auto;
|
||||
status = "okay";
|
||||
reg = <0x0a>;
|
||||
};
|
||||
hda11: hda@b {
|
||||
compatible = "intel,hda-dai";
|
||||
power-domains = <&io0_domain>;
|
||||
zephyr,pm-device-runtime-auto;
|
||||
status = "okay";
|
||||
reg = <0x0b>;
|
||||
};
|
||||
hda12: hda@c {
|
||||
compatible = "intel,hda-dai";
|
||||
power-domains = <&io0_domain>;
|
||||
zephyr,pm-device-runtime-auto;
|
||||
status = "okay";
|
||||
reg = <0x0c>;
|
||||
};
|
||||
hda13: hda@d {
|
||||
compatible = "intel,hda-dai";
|
||||
power-domains = <&io0_domain>;
|
||||
zephyr,pm-device-runtime-auto;
|
||||
status = "okay";
|
||||
reg = <0x0d>;
|
||||
};
|
||||
hda14: hda@e {
|
||||
compatible = "intel,hda-dai";
|
||||
power-domains = <&io0_domain>;
|
||||
zephyr,pm-device-runtime-auto;
|
||||
status = "okay";
|
||||
reg = <0x0e>;
|
||||
};
|
||||
hda15: hda@f {
|
||||
compatible = "intel,hda-dai";
|
||||
power-domains = <&io0_domain>;
|
||||
zephyr,pm-device-runtime-auto;
|
||||
status = "okay";
|
||||
reg = <0x0f>;
|
||||
};
|
||||
hda16: hda@10 {
|
||||
compatible = "intel,hda-dai";
|
||||
power-domains = <&io0_domain>;
|
||||
zephyr,pm-device-runtime-auto;
|
||||
status = "okay";
|
||||
reg = <0x10>;
|
||||
};
|
||||
hda17: hda@11 {
|
||||
compatible = "intel,hda-dai";
|
||||
power-domains = <&io0_domain>;
|
||||
zephyr,pm-device-runtime-auto;
|
||||
status = "okay";
|
||||
reg = <0x11>;
|
||||
};
|
||||
hda18: hda@12 {
|
||||
compatible = "intel,hda-dai";
|
||||
power-domains = <&io0_domain>;
|
||||
zephyr,pm-device-runtime-auto;
|
||||
status = "okay";
|
||||
reg = <0x12>;
|
||||
};
|
||||
};
|
||||
};
|
|
@ -5,15 +5,18 @@
|
|||
if SOC_INTEL_ACE30
|
||||
|
||||
config MP_MAX_NUM_CPUS
|
||||
default 5
|
||||
default 5 if BOARD_INTEL_ADSP_ACE30_PTL || BOARD_INTEL_ADSP_ACE30_PTL_SIM
|
||||
default 3 if BOARD_INTEL_ADSP_ACE30_WCL || BOARD_INTEL_ADSP_ACE30_WCL_SIM
|
||||
|
||||
config SYS_CLOCK_HW_CYCLES_PER_SEC
|
||||
default 442368000 if XTENSA_TIMER
|
||||
default 614400000 if XTENSA_TIMER && BOARD_INTEL_ADSP_ACE30_WCL
|
||||
default 442368000 if XTENSA_TIMER && BOARD_INTEL_ADSP_ACE30_PTL
|
||||
default 1000000 if INTEL_ADSP_SIM
|
||||
default 38400000 if INTEL_ADSP_TIMER
|
||||
|
||||
config XTENSA_CCOUNT_HZ
|
||||
default 442368000
|
||||
default 614400000 if BOARD_INTEL_ADSP_ACE30_WCL || BOARD_INTEL_ADSP_ACE30_WCL_SIM
|
||||
default 442368000 if BOARD_INTEL_ADSP_ACE30_PTL || BOARD_INTEL_ADSP_ACE30_PTL_SIM
|
||||
|
||||
config CPU_HAS_MMU
|
||||
def_bool y
|
||||
|
|
|
@ -96,7 +96,7 @@ void adsp_clock_init(void)
|
|||
} else {
|
||||
platform_lowest_freq_idx = ADSP_CPU_CLOCK_FREQ_IPLL;
|
||||
}
|
||||
#if CONFIG_SOC_INTEL_ACE30
|
||||
#if defined(CONFIG_BOARD_INTEL_ADSP_ACE30_PTL) || defined(CONFIG_BOARD_INTEL_ADSP_ACE30_PTL_SIM)
|
||||
/* Set the Cardinal clock divider to 18 to get 24.576MHz */
|
||||
ACE_DfPMCCU.dfcrodiv &= ACE_CRODIV_CARCDS_MASK;
|
||||
ACE_DfPMCCU.dfcrodiv |= ACE_CRODIV_CARCDS(0x12);
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue