dts: arm: silabs: change siwg917 board ram start address
The first 1 KB is reserved for the NWP (Network Coprocessor). This change also resolves the null pointer error issue, as a .data or a _ramfunc might get the address 0x0. Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
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2 changed files with 22 additions and 12 deletions
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@ -27,19 +27,28 @@
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};
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};
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sram0: memory@0 {
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/* The first 1KB of SRAM is reserved for the NWP (Network Processor).
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* It also protects against null pointer exceptions.
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*/
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nwp_reserved: memory@0 {
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compatible = "zephyr,memory-region","mmio-sram";
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reg = <0x00000000 DT_SIZE_K(1)>;
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zephyr,memory-region = "NWP_RESERVED_RAM";
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};
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sram0: memory@400 {
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compatible = "mmio-sram";
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/* siwx91x has 672kB of SRAM shared between the Cortex-M4
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/* siwx91x has 671kB of SRAM shared between the Cortex-M4
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* (Zephyr) and the NWP (Network Processor). 3 memory
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* configurations are
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* possible:
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* - 196kB
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* - 256kB
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* - 320kB
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* - 195kB
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* - 255kB
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* - 319kB
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* Less memory is allocated to Zephyr, more memory is allocated
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* to NWP, better are the WiFi and BLE performances.
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*/
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reg = <0x00000000 DT_SIZE_K(256)>;
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reg = <0x00000400 DT_SIZE_K(255)>;
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};
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sram_dma1: memory-dma@24061c00 {
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@ -22,9 +22,9 @@
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LOG_MODULE_REGISTER(siwx91x_nwp);
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BUILD_ASSERT(DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(196) ||
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DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(256) ||
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DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(320));
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BUILD_ASSERT(DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(195) ||
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DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(255) ||
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DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(319));
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int siwg91x_get_nwp_config(int wifi_oper_mode, sl_wifi_device_configuration_t *get_config)
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{
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@ -49,11 +49,12 @@ int siwg91x_get_nwp_config(int wifi_oper_mode, sl_wifi_device_configuration_t *g
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__ASSERT(get_config, "get_config cannot be NULL");
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if (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(196)) {
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/* The size does not match exactly because 1 KB is reserved at the start of the RAM */
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if (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(195)) {
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boot_config->ext_custom_feature_bit_map |= SL_SI91X_EXT_FEAT_480K_M4SS_192K;
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} else if (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(256)) {
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} else if (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(255)) {
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boot_config->ext_custom_feature_bit_map |= SL_SI91X_EXT_FEAT_416K_M4SS_256K;
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} else if (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(320)) {
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} else if (DT_REG_SIZE(DT_CHOSEN(zephyr_sram)) == KB(319)) {
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boot_config->ext_custom_feature_bit_map |= SL_SI91X_EXT_FEAT_352K_M4SS_320K;
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} else {
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k_panic();
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