Add a common part for AMD board ACP_6_0_ADSP.
Add support for ACP_6_0_ADSP BOARD,
which represents ACP_6_0 soc.
This has a 1 Xtensa HiFi5 core, with 200-800MHz
1.75 MB HP SRAM / 512 KB IRAM/DRAM,
1 x SP (I2S, PCM), 1 x BT (I2S, PCM), 1 x HS(I2S, PCM), DMIC as
audio interfaces.
Signed-off-by: DineshKumar Kalva <DineshKumar.Kalva@amd.com>
DCDC regulator on nRF54L may not always works as intended.
Tune the fix addressing that.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
DCDC regulator on nRF54L may not always works as intended.
Apply a fix addressing that.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
To configure APPROTECT on nRF54L15 different set of MDK symbols
must be used. Additionally, nRF54L15 does not support loading
APPROTECT configuration from the UICR in runtime.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
The nrfx_gppi module is an abstraction over nrfx_ppi and nrfx_dppi
drivers. It now has a Kconfig option that is separate from nrfx_dppi and
by default it enables all PPI/DPPI instances, if available.
Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
The hal_nordic revision was updated to bring in NRFX v3.8.0.
Aligned the uses of single-instance API to use multi-instance instead.
Signed-off-by: Rafał Kuźnia <rafal.kuznia@nordicsemi.no>
This commit enables the TPIU clock source in Apollo3 and
Apollo4 soc initialization if LOG_BACKEND_SWO is used.
Signed-off-by: Aaron Ye <aye@ambiq.com>
What is changed?
Use CMSIS SystemCoreClock via a dedicated flag instead of using
soc flags.
Why do we need this change?
This change is part of cleaning soc specific code out of arch folder.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
The production version of the nRF54H20 SoC is now available, so remove
the initial Engineering B (EngB) preview version.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Nordic SoCs implement an event system, for which the system can
optimize for low latency/high power or low power.
Add soc level implementation of reference counted API which will
optimize for low latency if any part of the system requires it.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Before that fix the names for UDMA could be misleading.
With that fix the namespace is clear and easy to follow.
Same applies for peripheral addresses and pad config.
Signed-off-by: Sven Ginka <s.ginka@sensry.de>
Refactor out the `soc_early_init_hook()` function from `pma.c` to
`soc.c` which is always compiled so that it can be extended to run
other init functions easily in the future. Then, restore the function
in `pma.c` to `pma_init()`.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
The function `pma_init_per_core()`, as its name suggest, should be
run from every core, so call it from `soc_per_core_init_hook()`
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
The `soc_per_core_init_hook()` function now has `void` type after
da118b9, so it should just return without any value.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Replace hardcoded register addresses and values in
asm_memory_management.h with Devicetree (DT) macros for LPSRAM
power-down operations. This change ensures that register addresses and
bank counts are dynamically obtained from the Devicetree, improving code
portability and reducing the risk of errors due to manual updates.
- Removed hardcoded LSPGCTL address definitions.
- Updated m_ace_lpsram_power_down_entire macro to use DT_NODELABEL to
fetch LPSRAM bank count and control register address
- Adjusted bit field extraction logic to align with the updated register
information from the Devicetree.
This commit aligns with the ongoing effort to utilize Devicetree for
hardware abstraction and to facilitate easier maintenance and updates to
the codebase.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Remove the m_ace_hpsram_power_change macro from asm_memory_management.h
as it is no longer used after refactoring the power_down function to
utilize the new m_ace_hpsram_power_down_entire macro. This cleanup helps
to reduce code complexity and maintainability.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Refactor the power_down function to utilize the newly introduced
m_ace_hpsram_power_down_entire macro for shutting down the entire
HPSRAM. This change simplifies the power-down process by replacing the
previous segment-based power gating mask approach with a single boolean
flag that indicates whether the entire HPSRAM should be disabled.
The function signature of power_down has been updated to accept the new
boolean flag, and the corresponding call sites have been modified to
pass the flag based on the CONFIG_ADSP_POWER_DOWN_HPSRAM Kconfig option.
Additionally, the assembly code has been cleaned up to remove the
now-obsolete hpsram_mask array and related logic.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Introduce a new assembly macro, m_ace_hpsram_power_down_entire, which
utilizes Zephyr Devicetree macros to power down the entire HPSRAM on
Intel ADSP ACE platforms.
This macro dynamically retrieves the HPSRAM bank count and control
register address from the Devicetree, streamlining the power-down
process. The macro is designed to iterate over all HPSRAM banks and
issue a power down command to each, ensuring a complete shutdown of the
HPSRAM when required by the system's power management policy.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This commit introduces the L2 Memory Capabilities (hsbcap) register node
to the Devicetree specifications for Intel ADSP ACE platforms. The
hsbcap register provides information on the general capabilities
associated with the L2 memory, which is critical for system
configuration and resource management. The hsbcap node has been added to
the Devicetree source files for ACE 1.5 (MTPM), ACE 2.0 (LNL), and ACE
3.0 (PTL) platforms.
In addition, the DFL2MM_REG macro in adsp_memory.h has been updated to
use the Devicetree node label for hsbcap, ensuring a consistent and
maintainable approach to accessing this register across the codebase.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This commit improves the readability of the power_down.S assembly file
by standardizing the indentation of the preprocessor definitions.
No functional changes have been made; this is purely a cosmetic update
to the code formatting.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
This commit addresses an issue on platforms with an MMU where a
LoadStoreTLBMissCause exception occurs when accessing hardware registers
during the power-down process. The exception arises when attempting to
access the IPC register after HPSRAM has been powered down, leading to a
double exception: LoadStoreTLBMissCause followed by
InstrPIFDataErrorCause.
To resolve this, we preload the IPC register before shutting down
LPSRAM. This change prevents the double exception by ensuring that the
page table entries are correctly managed in the TLB before HPSRAM is
powered down and allowing the power-down sequence to complete
successfully.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
-Update formatting and contents of index.rst for cy8ckit_062s4
-Update formatting and contents of index.rst for cy8ckit_064s0s2_4343w
-Update formatting and contents of index.rst for cy8cproto_062_4343w
-Update formatting and contents of index.rst for cy8cproto_063_ble
-Update formatting and contents of index.rst for xmc45_relax_kit
-Update formatting and contents of index.rst for xmc47_relax_kit
-Change all instances of "PSoC" to "PSOC" for infineon platforms
Signed-off-by: McAtee Maxwell <maxwell.mcatee@infineon.com>
The linker script for this SoC was not including the LLEXT section
definitions when CONFIG_LLEXT was enabled. This patch adds the
necessary include directive to the linker script and fixes the build
issue identified by CI.
Signed-off-by: Luca Burelli <l.burelli@arduino.cc>
The linker script for this SoC was not including the LLEXT section
definitions when CONFIG_LLEXT was enabled. This patch adds the
missing include directive to the linker script.
Signed-off-by: Luca Burelli <l.burelli@arduino.cc>
Fix missing input/output enable flags on pinctrl macro, which
wouldn't allow for driver to see and apply flags configuration
made in the device tree.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Updates and fixes to support APPCPU.
- fix ld scripts
- fix and update memory layout
- fix build issues
- fix sysbuild
Signed-off-by: Marek Matej <marek.matej@espressif.com>
The FRDM_MCXW71 Platform has a reserved IRQ as its
last IRQ, this test was using this IRQ to
test an interrupt and would not fire. This change
ensures the test does not use the reserved IRQ.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
When option ARM_MPU is disabled exclude soc\nxp\imxrt\mpu_regions.c.
It is needed to remove constraints of SRAM and FLASH size.
Fixes#70920
Signed-off-by: Grixa Yrev <GrixaYrev@yandex.ru>
Busy-waiting for the result of the nrfs service calls can stall, so
let's use a callback that flags a semaphore instead. Since the API is
supposed to be callable in the context of pre-kernel, fallback to
busy-wait on that scenario.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
As for the IMX SOCs all the lines removed in this commit were
actually commented out so there's basically no change in code
behavior expected here.
The only affected SOCs family is therefore the Kinetis one.
Signed-off-by: Valerio Setti <vsetti@baylibre.com>
