Commit graph

5973 commits

Author SHA1 Message Date
Marek Matej
930000d3b3 soc: espressif: Rename common/psram.c
Rename psram.c -> esp_psram.c to align with the naming conventions.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-12-16 20:49:10 +01:00
Marek Matej
e62f6651a0 soc: esp32s3: Fix WiFi allocation to SPIRAM
Fix the allocations if the SPIRAM and WiFi alloc to SPIRAM
are both enabled.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-12-16 20:49:10 +01:00
Marek Matej
cf73e90acd soc: esp32: Fix WiFi allocations to SPIRAM
Fix allocations of large buffers if SPIRAM and WiFi alloc
to SPIRAM are both enabled.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-12-16 20:49:10 +01:00
Martin Hoff
5d3221bdf8 soc: silabs: add dma support in soc kconfig
Update Kconfig to support LDMA.

Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
2024-12-16 18:24:51 +01:00
Gang Li
b4994ee2b9 soc: rw61x: enable IEEE802154 for NXP_FW_LOADER and NXP_RF_IMU
Enable IEEE802154 for NXP_FW_LOADER and NXP_RF_IMU

Signed-off-by: Gang Li <gang.li_1@nxp.com>
2024-12-13 03:02:13 +01:00
Marcio Ribeiro
cdbb1ddbad soc: esp32: change SRAM1_IRAM_START macro definition
Changes the SRAM1_IRAM_START macro definition for:
- esp32c2
- esp32c3

Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
2024-12-12 19:59:44 +01:00
Marek Matej
c69ecabc7a soc: esp32s3: update APPCPU code
Updates for AMP targets

- use common AMP Kconfig
- update APPCPU linker script
- place AMP common area in the reserved space

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-12-12 11:38:22 +01:00
Marek Matej
322ab2a86e soc: esp32: fixes and updates for AMP
Multiple AMP related updates:

- use common AMP Kconfig
- rework the APPCPU linker script
- use MCUboot image format for APPCPU image
- fix multi-processing startup code

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2024-12-12 11:38:22 +01:00
Nhut Nguyen
25ed9c9d99 drivers: pinctrl: Add support for RZ/G3S
This is the initial commit to support pinctrl driver for Renesas RZ/G3S

Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
2024-12-12 11:12:22 +01:00
Tien Nguyen
e535f9e253 soc: renesas: Add support for Renesas RZ/G3S
This adds minimal support for a new SoC Renesas RZ/G3S

Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Binh Nguyen <binh.nguyen.xw@renesas.com>
2024-12-12 11:12:22 +01:00
Jeff Daly
371ca13c6d drivers: adc: microchip: Different channels per package type
LJ packages have 16 ADC channels vs 8 for SZ packages.  Enhance
devicetree to account for this as well as conditional defines/code.

Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
2024-12-11 21:35:49 +01:00
Sercan Erat
662d9c75d0 soc: ambiq: apollo3x: Flash-controller reconfigured for mcuboot
Due to Apollo3's internal bootloader, zephyr build is not able
to create correct flash address on linker.cmd while using
mcuboot. The PR configures flash-controller start address
to solve this problem.

Test board: rakwireless/rak11720
Test project: samples/subsys/mgmt/mcumgr/smp_svr

Signed-off-by: Sercan Erat <sercanerat@gmail.com>
2024-12-11 21:35:18 +01:00
Emilio Benavente
a8647d3af9 soc: nxp: mcx: Updating Clock Code
Updating clock code to mcxw71.
Adding some missing clock setups.

Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
2024-12-11 21:27:51 +01:00
Manuel Argüelles
f85f8ee88e dts: bindings: rename nxp,kinetis-lpuart compatible
Rename "nxp,kinetis-lpuart" compatible to "nxp,lpuart" to remove the
device family from its name.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2024-12-11 08:00:30 +01:00
Krzysztof Chruściński
d1bd45739a logging: frontends: stmesp: Move zephyr_custom_log.h to the unique path
Logging with STMESP frontend is using custom logging header feature.
Put that specific header file in a custom path which is added to the
build only if that logging frontend is used.

Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
2024-12-10 20:37:22 +01:00
Axel Le Bourhis
5dfd41e51a nxp: combine MONOLITHIC_BT and MONOLITHIC_IEEE802154
Combine BLE and 802.15.4 monolithic build under a single config to make
it less error prone.
The choice between a BLE/802.15.4 combo firmware and a BLE only firmware
is done depending on the Soc (like RW610 vs RW612).

Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
2024-12-10 11:11:38 +01:00
Krzysztof Chruściński
752f8b0176 logging: frontends: stmesp: Add optimized short logs
Add 'turbo' logging feature. When enabled, short logs (no argument
or one numeric, 32 bit argument) are handled in a special way that
is much faster than the default one (5-10x faster). Additionally,
there is an option to remove all other logs from the system which
allows to not include almost any logging framework code in the
binary (~170 bytes of code is needed). It may be especially
valueable for memory constraint targets (ppr, flpr) where with
only 170 byte of code (+code for each log message) we can provide
limited formatted string logging support.

'Turbo' logging is using following to achieve that:
- logging strings are put into a memory section and additional
memory section is created which holds addresses of those strings.
Index in that array is used to identify a string (32 bit address
is encoded into a smaller number, 15 bits is more than enough).
This index is used for a STMESP register set (there are 2^16
available). So STMESP channel encodes string.
- Logging level is stringified and prepended to a string
- Source ID is encoded by using DM16 (so far not used).
- Log without arguments is written as DMTS16
- Log with one argumetn is written as DM16+DMTS32

Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
2024-12-10 11:09:55 +01:00
Nikodem Kastelik
a96b3e3d5d soc: nordic: nrf54l: add preliminary workaround for nRF54L anomaly 31
This workaround will be replaced with a variant
executed at SystemInit() level, once MDK implements it.

Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
2024-12-10 11:08:49 +01:00
Nikodem Kastelik
2d378a19fe soc: nordic: nrf54l: remove configuration of DCDC regulator
Since nrfx 3.9 integration, configuration is executed
in MDK SystemInit().

Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
2024-12-10 11:08:49 +01:00
Andrej Butok
e669bf8d3d soc: nxp: mcx: Add flash runner configuration
- Adds a flash runner configuration for mcxn/c/a/w
  used for sysbuild multi-image projects.
- Solves sysbuild issue with multiple resets and mass erases.

Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
2024-12-09 22:05:40 +00:00
Sylvio Alves
fc7cacc983 soc: esp32: fix smp_log usage
smp_log usage should be only used when SMP is enabled.
This is currently causing build issues after the fix
provided by #82377

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2024-12-09 22:05:23 +00:00
Krzysztof Chruściński
e8a5ecc160 soc: nordic: common: mram_latency: Add option to auto request no latency
Add CONFIG_MRAM_LATENCY_AUTO_REQ. When option is enabled then module
requests no latency during the initialization. This option might be
useful for cases where we want to achieve maximum performance and
want to avoid controlling MRAM in the code.

Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
2024-12-09 22:05:17 +00:00
Marcio Ribeiro
7f13961884 soc: esp32: replace hard-coded addresses and sizes by DT macros
Replaces hard-coded memory addresses and sizes with macros that retrieve
such values from the device tree.

Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
2024-12-07 11:02:46 +01:00
Raymond Lei
0db1c07bf0 soc: nxp: imxrt11xx: select CONFIG_HAS_MCUX_ADC_ETC
On NXP RT1170 SOC, ADC ETC exists but it can not be enabled because
of dependency on HAS_MCUX_ADC_ETC.
Also, ADC ETC should only work with ADC together, there is no use
case to run it standalone.
Fixes:#81466

Signed-off-by: Raymond Lei <raymond.lei@nxp.com>
2024-12-07 02:03:45 +01:00
Daniel DeGrasse
04dd110881 soc: nxp: imxrt: fix PDRV field setting for drive strength
In the IOMUXC controller, the PDRV field uses 0b0 to set the pin drive
to high, and 0b1 to set the pin to normal drive. Fix the pinctrl_soc.h
definitions for the iMXRT11xx parts to use the correct setting for this
register, based on the documentation for the pin control binding

Note that for PDRV type pins, this commit effectively switches their
drive strength setting.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2024-12-07 02:03:07 +01:00
Manuel Argüelles
87798f9e16 arch: arm: rename CPU_HAS_NXP_MPU to align with binding
Following the binding rename to "nxp,sysmpu", update the Kconfig
option to align with the binding name and to better reflect the
option's purpose.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2024-12-06 22:23:06 +01:00
Neil Chen
dbf1d58691 soc: mcxa156: update systick clock frequency to 96MHz
MCXA156 max frequeny is 96MHz

Signed-off-by: Neil Chen <cheng.chen_1@nxp.com>
2024-12-06 22:21:54 +01:00
Michał Stasiak
4c96cbb79b soc: nordic: nrf54l: remove redundant ELV code
Removed dead ELV code from nRF54L soc.

Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
2024-12-06 15:16:29 +01:00
Lucien Zhao
523d68420e dts: arm: nxp: add tpm instances for RT1180
add 6 tpm instances for RT1180
Enable clock for tpm

Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
2024-12-06 12:13:54 +01:00
Andy Ross
0632873fb3 soc/mt8196: Add interrupt routing support
The MT8196 device has a newer interrupt controller that acts like the
legacy ones once initialized (see intc_mtk_adsp.c).  But it has some
(only slightly) more complicated routing control that must be
initialized on reset, as the default is "don't deliver any interrupts
at all".  Previous versions of the device integration worked becuase
they relied on a SOF binary to be loaded at boot, but obviously that
doesn't work for a Zephyr-based SOF firmware image.

Signed-off-by: Andy Ross <andyross@google.com>
2024-12-05 22:08:55 +01:00
Andy Ross
6309c1b1a5 soc/mediatek/mbox: Enable IRQ
This driver forgot to enable its interrupt, but has been working
becuase Zephyr apps were always run in a context where the interrupt
controller had been initialized by a SOF binary at boot.

Signed-off-by: Andy Ross <andyross@google.com>
2024-12-05 22:08:55 +01:00
Andy Ross
4d6655983c soc/mediatek/mtk_adsp: Set XTENSA_CCOUNT_HZ
This got missed. Set it correctly for hygiene, though very few things
use it. There is a spot in SOF where it's helpful to have a number for
"fasted cpu clock rate" and this is the best candidate.

Signed-off-by: Andy Ross <andyross@google.com>
2024-12-05 22:08:55 +01:00
Andy Ross
1ec2b1c68f soc/mediatek: Add back SOF-only entry point
I thought I was being clever letting the linker place the entry point
arbitrarily (since the hardware can set it to any value).

But it turns out that the upstream Linux SOF loader code is hard-wired
to start the DSP only at the first byte of SRAM, always, no matter
what entry point is listed in the rimage file.  So until/unless this
is fixed, we need to add a trampoline at the start of SRAM (and
frustratingly that needs to be 1024 bytes long becuase of the
alignment requirements of the vector table that follows it, sigh...)

Signed-off-by: Andy Ross <andyross@google.com>
2024-12-05 22:08:55 +01:00
Andy Ross
00417b36bc soc/mediatek/adsp: Build zephyr.ri using rimage when available
This is mostly a cut/paste copy of similar code in intel_adsp and imx,
which sadly can't be shared given the way the design works.  Also
includes a bonus, slightly-passive-aggressive description of why that
is.

Signed-off-by: Andy Ross <andyross@google.com>
2024-12-05 22:08:55 +01:00
Andy Ross
b07a0972be soc/mt8196: Set SDK toolchain name
This is in sdk-ng upstream now (not in the current release yet), so
set it up.

Signed-off-by: Andy Ross <andyross@google.com>
2024-12-05 22:08:55 +01:00
Gerard Marull-Paretas
253af41150 soc: telink: tlsr: tlsr951x: remove PINCTRL defconfig
Relevant drivers now select this option.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-12-05 15:17:47 +01:00
Nikodem Kastelik
da76859054 soc: nordic: nrf54l: fix APPROTECT handling
APPROTECT symbols were already aligned to nRF54L15,
but did not take into account similar SoCs like nRF54L05 or L10.

Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
2024-12-05 12:30:37 +01:00
Neil Chen
7e69eed446 soc: nxp: mcxn: Remove HAS_MCUX_CACHE for MCXN236
MCXN236 don't support cache64

Signed-off-by: Neil Chen <cheng.chen_1@nxp.com>
2024-12-05 07:44:46 +01:00
Manuel Argüelles
1428fd02a2 dts: bindings: rename nxp,imx-lpi2c compatible
Rename "nxp,imx-lpi2c" compatible to "nxp,lpi2c" to remove the
device family from its name.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2024-12-04 14:15:52 -05:00
Gerard Marull-Paretas
a3d5036198 soc: nxp: imx*: remove redundant pinctrl defconfig
Many NXP socs had the following defconfig:

```
config PINCTRL_IMX
	default y if HAS_IMX_IOMUXC
	depends on PINCTRL
```

However, the PINCTRL_IMX option already has:

```
config PINCTRL_IMX
	bool "Pin controller driver for iMX MCUs"
	depends on DT_HAS_NXP_IMX_IOMUXC_ENABLED
	depends on HAS_MCUX_IOMUXC || HAS_IMX_IOMUXC
	default y
	help
	  Enable pin controller driver for NXP iMX series MCUs
```

So the soc level defconfigs are redundant.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-12-04 12:09:41 +01:00
Arif Balik
3b5003de18 soc: espressif: fix missing spinlock definition
This definition is deleted in the follwoing commit;
8233b70
as a part of "cleanup", however this definition is
used by smp_log

Signed-off-by: Arif Balik <arifbalik@outlook.com>
2024-12-03 23:29:46 +00:00
Jamie McCrae
486fd37de9 soc: nordic: Select symbol properly
Correctly selects the Kconfig symbols for viper CPU clusters
instead of having a reverse hwmv1 setup where the symbol has
a choice

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2024-12-03 15:48:37 +00:00
Kyra Lengfeld
51957c8858 soc: nordic: Default enable Power Management on nRF54H20 radio core
Adds CONFIG_PM=y to Radio core in the nRF54H20 SoC on the nRF54H20 DK
soc defconf.

Signed-off-by: Kyra Lengfeld <kyra.lengfeld@nordicsemi.no>
2024-12-03 15:47:48 +00:00
Fabrice DJIATSA
c666c4db1b soc: st: stm32: stm32g0x: add soc configs for i2c shared irq
check if multiples UART instances with same irq are enabled
at same time then enable shared_interrupt handler.

set the default value of SHARED_IRQ_MAX_NUM_CLIENTS config if
we have more than 2 usarts instances enabled.

Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
2024-12-03 10:16:55 +01:00
Hao Luo
5d4353dc9a drivers: timer: ambiq: add clock source selection for stimer
Add clock source selection for stimer and make it configurable

Signed-off-by: Hao Luo <hluo@ambiq.com>
2024-12-03 04:01:45 +01:00
Manuel Argüelles
4ab9172c92 dts: bindings: rename nxp,imx-lpspi compatible
Rename "nxp,imx-lpspi" compatible to "nxp,lpspi" to remove the
device family from its name.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2024-12-02 22:06:47 +00:00
McAtee Maxwell
3024392d35 SOC: Remove config PINCTRL from xmc4xxx soc
- Move selection of CONFIG_PINCTRL from soc to individual
	  drivers
	- in accordance with issue #78619

Signed-off-by: McAtee Maxwell <maxwell.mcatee@infineon.com>
2024-12-02 22:05:16 +00:00
Torsten Rasmussen
35625c146a boards: samples: remove CONFIG_BUILD_NO_GAP_FILL=y and similar
Gap filling in hex files are now disabled per default, and therefore
there is no reason to explicitly disable gap filling.

It has never been possible to disable gap filling in binary files.
Disabling gap filling would just result in the binary file to be gap
filled with the tool's default value, objcopy=0x00.

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2024-12-02 11:14:09 +01:00
Jamie McCrae
d7d636d1f2 soc: expressif: esp32c3: Fix wrong placement of Kconfig
Fixes a wrong placement of a Kconfig which was put into the
wrong file and was bleeding through to every board

Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
2024-11-30 09:36:07 +01:00
Tomasz Leman
c0a01d33e3 Revert "soc: intel_adsp/ace30: do not map 0x0"
This reverts commit 3d3ffa2c05.

The original commit aimed to prevent NULL pointer accesses by moving the
MMU mapping starting point one page later. However, this change has
caused a regression on PTL. Our DSP has registers with addresses lower
than 0x1000, and the firmware uses addresses starting from 0xC40. For
instance, the HDAMLDMICL register is located at 0xCC0, which is now
inaccessible due to the change.

Reverting this commit restores access to these critical registers and
resolves the regression issue.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2024-11-29 19:27:53 -05:00