drivers: pinctrl: npcx: add pinctrl driver support for npck3
As title. Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
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5 changed files with 41 additions and 2 deletions
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@ -3,7 +3,6 @@
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# Copyright (c) 2022 Nuvoton Technology Corporation.
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# SPDX-License-Identifier: Apache-2.0
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config PINCTRL_NPCX
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bool "Nuvoton NPCX embedded controller (EC) pin controller driver"
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default y
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@ -11,3 +10,9 @@ config PINCTRL_NPCX
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help
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This option enables the pin controller driver for NPCX family of
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processors.
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config PINCTRL_NPCX_EX
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bool "Extended NPCX driver support"
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default y if DT_HAS_NUVOTON_NPCX_PINCTRL_NPCKN_ENABLED
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help
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This option enables the extended driver for NPCKN variant of processors.
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@ -139,11 +139,24 @@ static void npcx_psl_input_detection_configure(const pinctrl_soc_pin_t *pin)
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}
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/* Configure detection mode of PSL input pads */
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#if defined(CONFIG_PINCTRL_NPCX_EX)
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if (pin->flags.psl_in_mode == NPCX_PSL_IN_MODE_EDGE) {
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inst_glue->PSL_CTS3 |= BIT(psl_in->port);
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} else {
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inst_glue->PSL_CTS3 &= ~BIT(psl_in->port);
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}
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/* Clear event bits */
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inst_glue->PSL_CTS |= BIT(psl_in->port);
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inst_glue->PSL_IN_POS |= BIT(psl_in->port);
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inst_glue->PSL_IN_NEG |= BIT(psl_in->port);
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#else
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if (pin->flags.psl_in_mode == NPCX_PSL_IN_MODE_EDGE) {
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inst_glue->PSL_CTS |= NPCX_PSL_CTS_MODE_BIT(psl_in->port);
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} else {
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inst_glue->PSL_CTS &= ~NPCX_PSL_CTS_MODE_BIT(psl_in->port);
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}
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#endif /* CONFIG_PINCTRL_NPCX_EX */
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}
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static void npcx_device_control_configure(const pinctrl_soc_pin_t *pin)
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@ -56,7 +56,7 @@
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* Then, the user can override the pin control options at the board level.
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*/
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pinctrl: pinctrl {
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compatible = "nuvoton,npcx-pinctrl";
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compatible = "nuvoton,npcx-pinctrl", "nuvoton,npcx-pinctrl-npckn";
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status = "okay";
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};
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9
dts/bindings/pinctrl/nuvoton,npcx-pinctrl-npckn.yaml
Normal file
9
dts/bindings/pinctrl/nuvoton,npcx-pinctrl-npckn.yaml
Normal file
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@ -0,0 +1,9 @@
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# Copyright (c) 2025 Nuvoton Technology Corporation.
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# SPDX-License-Identifier: Apache-2.0
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description: |
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Nuvoton npcx pinctrl for npckn variant
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compatible: "nuvoton,npcx-pinctrl-npckn"
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include: nuvoton,npcx-pinctrl.yaml
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@ -98,6 +98,7 @@ void npcx_pinctrl_i2c_port_sel(int controller, int port)
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{
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struct glue_reg *const inst_glue = HAL_GLUE_INST();
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/* Set SMB_SEL bit to select port 1, otherwise select port 0 */
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if (port != 0) {
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inst_glue->SMB_SEL |= BIT(controller);
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} else {
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@ -138,10 +139,17 @@ int npcx_pinctrl_flash_write_protect_set(void)
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{
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struct scfg_reg *inst_scfg = HAL_SFCG_INST();
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#if defined(CONFIG_PINCTRL_NPCX_EX)
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inst_scfg->DEV_CTL3 |= BIT(NPCX_DEV_CTL3_WP_IF);
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if (!IS_BIT_SET(inst_scfg->DEV_CTL3, NPCX_DEV_CTL3_WP_IF)) {
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return -EIO;
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}
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#else
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inst_scfg->DEV_CTL4 |= BIT(NPCX_DEV_CTL4_WP_IF);
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if (!IS_BIT_SET(inst_scfg->DEV_CTL4, NPCX_DEV_CTL4_WP_IF)) {
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return -EIO;
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}
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#endif
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return 0;
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}
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@ -150,7 +158,11 @@ bool npcx_pinctrl_flash_write_protect_is_set(void)
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{
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struct scfg_reg *inst_scfg = HAL_SFCG_INST();
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#if defined(CONFIG_PINCTRL_NPCX_EX)
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return IS_BIT_SET(inst_scfg->DEV_CTL3, NPCX_DEV_CTL3_WP_IF);
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#else
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return IS_BIT_SET(inst_scfg->DEV_CTL4, NPCX_DEV_CTL4_WP_IF);
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#endif
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}
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void npcx_host_interface_sel(enum npcx_hif_type hif_type)
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