The SK-AM62 and SK-AM62B-P1 board variants both use the AM6254
SoC, not AM6234. Update board configuration to reference the
correct SoC variant.
This changes the board identifiers from sk_am62/am6234/* to
sk_am62/am6254/* for both M4 and A53 cores.
Documentation updated to mention both board variants:
- SK-AM62 (base variant)
- SK-AM62B-P1 (variant with integrated PMIC)
Signed-off-by: Soumya Tripathy <s-tripathy@ti.com>
added SOC_AMEBA_NP_IMAGE to handle ameba blobs to run a different
architecture CPU inside the SOC.
Signed-off-by: zjian zhang <zjian_zhang@realsil.com.cn>
Adds a common-place for Kconfigs needed by TF-M instead of
mass-duplicating them in every board that uses these SoCs
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Since the audio DSP is not using the architecture boot path,
the BSS is not cleared/zeroed at boot. So we need to manually
zero out the BSS via arch_bss_zero().
Also, the _bss_table_start/_end symbols are no longer needed
since we are not using the arch boot code. Saves a few bytes.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Removing cpu0 reference from mcxw72 target
as only cpu0 should be targeted on this device.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
Change logic from the offset to the absolute address as the
DT_REG_ADDR(..) macro now returns the absolute address and cannot be
compared with the value of the CONFIG_FLASH_LOAD_ADDRESS.
Signed-off-by: Tomasz Chyrowicz <tomasz.chyrowicz@nordicsemi.no>
If MCUboot is enabled, the start address of the radio core firmware is
offset by MCUboot header.
Normally, the header is accounted for by setting the
CONFIG_ROM_START_OFFSET value to match the header size.
Signed-off-by: Tomasz Chyrowicz <tomasz.chyrowicz@nordicsemi.no>
Workaround has been reverted and different approach is taken.
Removing UART_NRFX_UARTE_SPURIOUS_RXTO_WORKAROUND from nrf54lm20a
Kconfig.defconfig.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
The base address was written to an incorrect register, which caused
incorrect data to be read from the I2C target. This has been fixed by
writing to the correct register.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Fix macros/symbols that broke after changes were merged to get the
absolute address through ranges property
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Correct GIC addresses to match ARM Cortex-R8 TRM PERIPHBASE specification.
GIC must be at fixed offsets from PERIPHBASE (0xAE000000)
- Distributor: 0xAE001000 (PERIPHBASE + 0x1000)
- CPU Interface: 0xAE000100 (PERIPHBASE + 0x100)
Updated device tree, MPU regions, and Renode configuration to use
correct addresses and add required memory protection.
Signed-off-by: Raja Shahzaib <rshahzaib077@gmail.com>
We updated the SoC Microchip MEC common helper and headers.
Add helper routines to manipulate PCR sleep enable bits, etc.
Add miscellaneous helper routines.
Add QMSPI register definitions to be used by SPI and MSPI drivers.
Create a common header containing includes of all other
common headers to prevent changing each chip's soc.h
Note, we must add build logic to handle naming difference of eSPI
SAF/TAF nodes. Intel changed name of SAF to TAF. MEC15xx and MEC172x
older driver still use SAF in DT node naming.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
sl_wifi_performance_profile_t is deprecated. The migration to
sl_wifi_performance_profile_v2_t is pretty easy, so there is not reason to
delay it (in fact, the two versions only differ in binary compatibility,
the API is still compatible).
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
- Improve the universality of the 118x series SoC and
decouple the dependencies that point to specific parts.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
The BCM2711 GPIO controller provides 58 GPIO pins (0-57) that can be
configured for various functions including GPIO input/output and
alternate functions for peripherals like SPI, I2C, UART, PWM, etc.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
Without this change, the fix introduced in commit 189fa5f4d8e ("modules:
silabs: Force sli_mv_m4_app_from_flash_to_ram() to be in RAM") is not
active.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Add SB_CONFIG_SOC_RA_START_SECOND_CORE for Renesas RA8P1
SoC to support building a minimal launcher image that
starts the second core on Renesas RA SoCs via sysbuild
Signed-off-by: Khai Cao <khai.cao.xk@renesas.com>
Below warning is reported in Zephyr upstream weekly CI after
34985a73b836b7f44b3314854fc760270e38fb26 was merged:
```
ld.bfd: warning: orphan section .TEXT.pm_s2ram_mark_check_and_clear'
from zephyr/libzephyr.a(s2ram_marking.S.obj)' being placed in section
`.TEXT.pm_s2ram_mark_check_and_clear'
```
Fix the warning by adding the appropriate headers.
Signed-off-by: Anjali Kashyap <anjkas23@gmail.com>
Adds these properties which are missing, and fixes instances of
wrongly using relative addresses when they are already absolute
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Sleeptimer must be initialized before sl_power_manager since
SiSDK 2025.12, as it's no longer done internally in the power
manager.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Add NRF_TRUSTZONE_X_REGION_SIZE for mpc region size alignment.
fix missing include of soc header file.
Signed-off-by: Travis Lam <travis.lam@nordicsemi.no>
- Define the entire SMU2 as a single memory region so it represents only
one entry in the MPU.
- Clean up linker.ld and sections.ld to remove obsolete/unused symbols
- Declare the "shmem_fwk" section in SMU2 used by connectivity framework
- Rearrange the rpmsg shared memory relatively to the entire SMU2 range
- Provide necessary symbols for the connectivity framework to locate its
shared memory section within SMU2
This is preparatory work for upcoming connectivity framework
integration and mcxw70 ble enablement.
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
The previous NUM_IRQS value of 256 was incorrect for the Versal2
RPU platform. Increase to 288 to ensure all hardware interrupt
lines are properly supported by the GIC driver.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
Fix case where absolute event was registered. In that case PPI wake
up was never used.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
nrf_sys_event_unregister was missing an immediate return when PPI
was used by the handle. It was stepping into non-PPI case where
an assert might have been triggered.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Following recent updates, the bootloader dram segment length must be
increased to compile mcuboot on esp32.
Signed-off-by: Joel Guittet <joelguittet@gmail.com>
Use the zephyr,code-partition chosen node to determine the flash
partition offset for IROM/DROM mapping. This enables Direct-XIP
mode support where the slot1 variant image needs a different flash
offset than slot0.
Falls back to slot0_partition if zephyr,code-partition is not defined,
maintaining backward compatibility with existing configurations.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Fixes the Kconfig name of this so that it matches the value from
soc.yml, and deprecates the old name - this is required to support
future build system features. Additionally, it fixes an issue in
Kconfigs of this SoC of duplicating existing symbols
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
In WCH chips entering idle via `wfi` will break ongoing DMA
transactions. This adds PM state to prevent `wfi` idle in specific drivers.
Signed-off-by: James Bennion-Pedley <james@bojit.org>
