Add ITM to common device tree and set the correct clock config
when using SWO as a logging backend
Signed-off-by: Henrik Grunmach <henrik.grunmach@rohde-schwarz.com>
- create 'mcxe' as family and 'mcxe24x' as series
- add pinctrl_soc.h
- add soc.c/.h to do system initialization
- Support flash boot if CONFIG_MCXE_FLASH_CONFIG==1
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Adds HPPASS SAR ADC driver and HPPASS Analog driver files to support
ADC conversion for the PSOC C3 family of MCUs.
Signed-off-by: John Batch <john.batch@infineon.com>
This allows adding the CPU ID to the number of NOPs in
the custom arch_spin_relax(). With the same number of NOPs
for all CPUs, it is possible to have them all doing RCW
transactions at the same time over and over again if they
enter and exit the spin relax loop at the same time.
This behavior has been observed when doing lots of context
switching, like in the SMP switching stress test. So adds
a new kconfig to fine tune the relax loop behavior if
needed. The new kconfig allows adding the CPU ID to
the number of NOPs which will add some minimal offsetting
to workaround the above mentioned situation.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
MAX32658 is the 1.8V variant of MAX32657. From a software perspective,
both SoCs are functionally equivalent. Reuse the existing MAX32657
backend for MAX32658 to enable support with minimal changes.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Adds initial SoC-level support for the Microchip
PIC32CZ CA80/9x series, including SoC definition files.
Signed-off-by: Mohamed Azhar <mohamed.azhar@microchip.com>
When the XDMAC is activated in the DT, configure it's register region
with strong ordered, read and write access.
Signed-off-by: Tony Han <tony.han@microchip.com>
Product URL: https://www.microchip.com/en-us/product/SAMA7D65
The files under 'soc/microchip/sam/sama7/' will be used for both
sama7d5 and sama7d65 SoCs after the directory structure for sama7g5
is reorganized.
Signed-off-by: Tony Han <tony.han@microchip.com>
Replace the array size for sama7g5 registered clocks with macros and
put the macros to soc.h with descriptions.
Signed-off-by: Tony Han <tony.han@microchip.com>
Change the location of the names for programable clocks from the
stack to "static struct clk_programmable" array.
Signed-off-by: Tony Han <tony.han@microchip.com>
We added ECIA GIRQ get/set/clear functions avaiable for
all MEC parts. Drivers can make use of these functions
to get, set, and clear GIRQ status and enables for
their peripheral. In cases where code requires 8/16 bit
access to these or other SoC registers we added inline
helpers modeled after Zephyr's 32-bit sys_read/write/test
routines. This commit is part of a long term goal to share
drivers among all the MEC parts.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
When the PWM is activated in the DT, configure it's register region
with strong ordered, read and write access.
Signed-off-by: Tony Han <tony.han@microchip.com>
Adds initial SoC-level support for the Microchip
PIC32CX SG series, including SoC definition files.
Signed-off-by: Muhammed Asif <muhammed.asif@microchip.com>
Take it from the chosen flash node parent (MPI controller) 'nor'
register, which contains the memory mapped address for the NOR flash.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Move interrupt controller selection from SOC_FAMILY_QEMU_VIRT_RISCV
to individual SoC configurations.
This follows Zephyr best practices where hardware capabilities should
be selected at the most specific level possible (SoC porting guide).
This enables conditional selection of mutually exclusive interrupt
controllers within the same SoC.
Changes:
- Remove 'select RISCV_HAS_PLIC' from SOC_FAMILY_QEMU_VIRT_RISCV
- Add 'select RISCV_HAS_PLIC' to each individual SoC:
* SOC_QEMU_VIRT_RISCV32
* SOC_QEMU_VIRT_RISCV32E
* SOC_QEMU_VIRT_RISCV64
No functional change - all existing QEMU RISC-V boards continue to
use PLIC as before.
Signed-off-by: Afonso Oliveira <afonsoo@synopsys.com>
Add support for the battery backup (VBAT) functionality on
Renesas RA8 family. This allows the RTC to retain timekeeping
data when the main power supply is lost by switching to the
VBAT domain automatically. This commit add support for these
SoC series: ra8m1, ra8p1, ra8d1
Signed-off-by: Khoa Tran <khoa.tran.yj@bp.renesas.com>
uicr/zephyr/zephyr.hex needs to be built after all other zephyr
images.
Instead of adding a dependency on uicr, we check the sysbuild_images
property to find images.
Also, we check it as late possible by using the cmake_language(DEFER
DIRECTORY feature. Which will ensure that running this code will be
one of the last things that the CMake sysbuild program does at
Configure time.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Relocate the initialization of the gpio-q group and the elpm
module to early SoC preparation hook. The elpm xlpout signal
is connected to the main power rail and is driven by firmware
after bootup. Initializing these modules early ensures that
the power rail remains stable and does not drop.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Add ethernet DMA buffer/descriptor region (sram2) and read only
flash region 0x08FFF800 with unique device ID registers to MPU region
list. The unique device ID is used to create a random mac address by
the ethernet driver. Ethernet DMA buffer/descriptor memory section is
also added to linker script.
Signed-off-by: Thomas Decker <decker@jb-lighting.de>
Provide default values for common kconfig symbols for main, idle and
isr stack sizes, which apply on all STM32 MCU families with low RAM
memory(less than 8 KiB).
These kconfig symbols help reduce kernel sizes to fit within
limited RAM.
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
This commit addresses an issue where the IMU interrupt is enabled too
early by the nxp_nbu driver, this leads to a race condition where the
interrupt can be triggered even though the IMU driver is not fully
initialized.
The interrupt shall not be enabled at Zephyr level since this will
be done by the low level driver in the hal_nxp.
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
Add initial support for Nuvoton NuMaker-M333x SoC series,
including basic initialization and device tree includes.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
The goal of this patch is to switch from the nwp.c and nwp.h soc files
to the new nwp driver. During this transition, we also renamed
CONFIG_WISECONNECT_NETWORK_STACK to CONFIG_SILABS_SIWX91X_NWP which are
a better naming to let the user knows that the network coprocessor files
will be added to the compilation.
The switch from a soc file to a driver device introduce a notion of nwp
device that allows us to check for good initialization and ressources
allocation.
Before this patch, it is not possible to know if the nwp have booted
successfully or not. We can now check if the device driver is ready
or not before trying to do operation related to the nwp.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
In power management, add support to take into account the alarms
set in RTC. Alarm from RTC is processed like any other from SYSTIM.
This prevents from missing interrupts.
Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com>
Add conditonal definition for RTC and SYSTIM with different
values for both of them respecting clock speed and ticks
per minute.
Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com>
1. update hal_nxp to mcux sdk 25.09.00
2. Updated imxrt7xx part numbers to align with SDK.
3. Fixed typo in member of dsi_transfer_t structure. The sendDscCmd
and dscCmd shall be sendDcsCmd and dcsCmd.
4. Remove the call to the function 'CLOCK_OSC_GateOscRc400M'. This
function has been removed from the SDK.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Add the description of NPU Cache (aka cacheaxi) to allow configuring
them in NPU Cache driver.
I intentionally chose this over creating a new dedicated node as
the exclusive user is NPU Cache and this could be done as part of
NPU driver initialization.
Update the NPU driver to take those into account as part of its init
routine.
Signed-off-by: Mickael Guene <mickael.guene@st.com>
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Add DMA nodes for MCXW7X SOC DTS.
This SOC used TRIGMUX instead of DMAMUX.
Enable EDMAv3 for the frdm_mcxw71 and frdm_mcxw72
platforms.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Co-authored-by: Declan Snyder <declan.snyder@nxp.com>
This commit adds the following functionality support:
1. More baudrate setting.
2. 7 bit data moded.
3. Tx (CR_SOUT) and Rx (CR_SIN) signal invert.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Some platforms do not have flash memory. The flash mpu region cannot
be created in case CONFIG_FLASH_SIZE is zero.
Signed-off-by: Yanqin Wei <yanqin.wei@arm.com>
Signed-off-by: Divin Raj <divin.raj@arm.com>
