The litex bootloader doesn't support XIP by default,
so remove it. In the board it was already deactivated.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Switch from OS timer-only approach to dual-timer strategy for improved
low power timing precision, especially for connectivity applications.
The previous approach used OS timer for both system ticks and low power
wakeup. With low tick rates, sleep time calculations lacked
precision, causing premature wakeups before BLE events, increasing power
consumption.
This rework uses high-precision SYSTICK during operation and switches
to OS timer for low power wakeup and coordination with link layer
event scheduling.
Signed-off-by: Yassine El Aissaoui <yassine.elaissaoui@nxp.com>
Add PM support for nrf92 series products
by making power management implementation common
to all Haltium platform
Signed-off-by: Pasi Liimatainen <pasi.liimatainen@nordicsemi.no>
The function `z_isr_install()` is used during the rtl87x2g SoC init,
necessitating `GEN_ISR_TABLES`.
Enabling this config also correctly causes the `arch.arm.irq_vector_table`
testcase to be filtered out (skipped). This is expected behavior as that
test is intended for configurations without `GEN_ISR_TABLES`.
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
Integrate support for a minimal driver for IronSide SE IPC which is
thread-unsafe, uses busy waiting, and assumes that the IPC region
is uncached. The driver is included in the IronSide interface code
itself, and is enabled by defining IRONSIDE_SE_CALL_MINIMAL.
This is primarily intended to be used by MCUboot but can be used by
e.g. resource constrained single-threaded firmware.
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
Add support to the UICR generator image for the new features
in the IronSide support package:
Split blob generation options like GEN_UICR_PERIPHCONF
into GEN_UICR_PERIPHCONF and GEN_UICR_GENERATE_PERIPHCONF to
allow configuring the blob address independently from generating
the blob itself.
Add support for generating a UICR MPCCONF blob by extracting a table of
entries from an image ELF file. The mechanism works mostly the same
as the UICR PERIPHCONF blob generation. When the UICR generator image
finds another image that has CONFIG_NRF_MPCCONF_SECTION=y, it will
extract the data from the section named 'mpcconf_entry' and include it
in build/uicr/zephyr.hex and either build/uicr/mpcconf.hex
or build/uicr/secondary_mpcconf.hex.
Add support to the UICR generator image for setting the
POLICY_MPCCONFSTAGE field via Kconfig. Setting this to INIT is
required to make use of the new ironside_se_mpcconf_write() API
added with IronSide SE v23.4.0+27, which is used to configure
global domain MPCs.
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
Use the more appropriate KERNEL_DEVICE priority as default for the NPU
instead of KERNEL_DEFAULT. While at it, also clean up the NPU-specific
Kconfig file by using an `if` block to gate symbols.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Set DCACHE_LINE_SIZE and ICACHE_LINE_SIZE configdefaults to 64 bytes
for the APU (Cortex-A) configurations on Versal, Versal2, and
Versalnet SoCs.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
Enable CACHE_MANAGEMENT for both RPU and APU configurations
on AMD Versal2 SoC.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
The Kconfig.defconfig file was using incorrect syntax for setting
default configuration values. Lines like "CONFIG_CACHE_MANAGEMENT=y"
are .config/prj.conf fragment syntax, not valid Kconfig language.
This caused the Kconfig parser to silently ignore these lines,
resulting in CACHE_MANAGEMENT not being enabled by default for
VersalNet APU builds.
Fix by using proper Kconfig syntax with "config" block and
"default y" statement. Also remove the duplicate CONFIG_CACHE_MANAGEMENT
line and the redundant ARM_ARCH_TIMER setting which is already enabled
by the top-level Kconfig.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
sys_cache_instr_enable() calls into the Zephyr cache driver
(cache_nrf.c), which is not compiled as part of the TF-M platform
build. When CONFIG_CACHE_MANAGEMENT and CONFIG_ICACHE are both
enabled, this produces an undefined reference at link time.
Use nrf_cache_enable() directly via the nrfx HAL for TF-M builds,
which is already available in the TF-M platform. Zephyr builds are
unaffected and continue to use the driver abstraction.
Signed-off-by: Dag Erik Gjørvad <dag.erik.gjorvad@nordicsemi.no>
- Fix lp_gpio Kconfig dependency to use proper
DT_HAS_ESPRESSIF_ESP32_LPGPIO_ENABLED symbol instead of
SOC_ESP32C6_LPCORE, and separate GPIO_ESP32 from LPGPIO_ESP32
- fix lp_gpio compatible string to espressif,esp32-lpgpio to
match the corrected Kconfig dependency
- enable global LP core interrupts at startup via
ulp_lp_core_intr_enable() in lp_core_startup(); the LP core
has no interrupt allocator so this must be done once for any
peripheral using the single interrupt vector
- enable lp_gpio in gpio_wakeup sample overlay
- fix ESP_CONSOLE_UART_NUM default for LP HP UART console
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Implement comprehensive Memory Protection Unit (MPU) support for
Xilinx Versal RPU with the following enhancements:
MPU Region Configuration:
- Add arm_mpu_regions.c with MPU region definitions supporting
multiple memory layouts:
* TCM-only layout
* Contiguous DDR layout
* Non-contiguous DDR layout for Linux shared memory scenarios
- Configure memory regions for PL, PS peripherals, and DDR with
appropriate memory attributes (Normal, Device, Strongly-ordered)
SoC Initialization:
- Add soc_early_init_hook() for instruction and data cache
enablement during early boot
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
Remove the unused CRL_RST_TTC register address definition from soc.h.
This macro is not referenced anywhere in the codebase.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
Regroup the Kconfig.defconfig.<soc> files of various series which have
identical contents for all SoCs into the per-series root file instead
(stm32XXx/Kconfig.defconfig). This reduces the number of files and is
easier to understand.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Add DT helper file for PIC32CM-PL family devices to support
SoC-specific device tree definitions and utilities.
Signed-off-by: Arunprasath P <arunprasath.p@microchip.com>
Add CONFIG_SOC_NRF71_WIFI_BOOT, so that ns sample does not start Wi-Fi,
this is because wicr and lmac is initialised to some gibberish value
when it is not loaded this breaks the CI.
Signed-off-by: Travis Lam <travis.lam@nordicsemi.no>
On siwx91x, no data cache is associated with the main flash. Therefore,
all accesses to data stored in flash penalizes performances (22 CPU cycles
for 1 data access). This patch allow the user to enable
CONFIG_SLOW_FLASH_DATA
The benefit of this option depends of the workload. Some kernel benchmarks
(tests/benchmarks/app_kernel/) run up to 300% faster, while the typical
improvement is around 10-50%.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
RAIL depends on the LDMA and TIMER peripherals when Bluetooth Channel
Sounding support has been enabled, so be sure to include those in the
build for such configurations.
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
The clock initialization for RX devices is not appropriate when it is
placed under the root clock node. Without an external fixed clock on the
board, the clock is never initialized. Therefore, the clock
setup must be handled inside soc_early_init_hook.
Signed-off-by: Y Huynh <y.huynh.xw@renesas.com>
Add BLEPLAT_AesCcmCrypt() function required by
the stm32wba ble library in the release
STM32Cube_FW_WBA_V1.8.0
Signed-off-by: Vincent Tardy <vincent.tardy@st.com>
Kconfig enhancement for mcx series
MCXN: adds comments + begins splitting MCXN547 vs MCXN547_CPU0
(to reflect per-core feature differences similarly).
MCXW2xx: adds new part number MCXW235BIHNAR,
and moves CPU feature selects into the series Kconfig.
Signed-off-by: Hake Huang <hake.huang@nxp.com>
The NUM_IRQS value for MCXW2xx was incorrectly set to 63. According to
the device reference manual, the correct number of interrupts is 61.
Fixes: #98279
Signed-off-by: Jason Yu <zejiang.yu@nxp.com>
Includes file for mapping DFP macros to follow a common
macro name for sercom uart g1 driver
Signed-off-by: Fabin V Martin <Fabinv.Martin@microchip.com>
Add config SOC_RA_DYNAMIC_INTERRUPT_NUMBER to indicate the SoC
support the dynamic interrupt number assignment feature.
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Add DT helper file for PIC32CM-JH family devices to support
SoC-specific device tree definitions and utilities.
Signed-off-by: Arunprasath P <arunprasath.p@microchip.com>
Add support for configuring lfxo external clock source based on
lfxo configuration in devicetree. The addition both selects
bypass mode if external-clock-source is set, and adds a build
assert to catch invalid configuration of internal load capacitors
in case external-clock-source is used.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Add support for the Ensemble E4 series and the AE402FA0E5597LE0
SoC within this series. The SoC contains two Cortex-M55 cores:
one configured to maximize power efficiency (RTSS-HE - High
Efficiency Real Time Subsystem) and the other to maximize compute
performance (RTSS-HP - High Performance Real Time Subsystem).
The E4 series uses SOC_FAMILY_ENSEMBLE_RTSS helper symbol
introduced earlier to share the CPU architecture configuration
with the E6 and E8 series.
Link: https://alifsemi.com/products/ensemblegenai/
Link: https://alifsemi.com/ensemble-e4-series/
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Add support for the Ensemble E6 series and the AE612FA0E5597LS0
SoC within this series. The SoC contains two Cortex-M55 cores:
one configured to maximize power efficiency (RTSS-HE - High
Efficiency Real Time Subsystem) and the other to maximize compute
performance (RTSS-HP - High Performance Real Time Subsystem).
The E6 series uses SOC_FAMILY_ENSEMBLE_RTSS helper symbol
introduced earlier to share the CPU architecture configuration
with the E8 series.
Link: https://alifsemi.com/products/ensemblegenai/
Link: https://alifsemi.com/ensemble-e6-series/
Signed-off-by: Silesh C V <silesh@alifsemi.com>
All RTSS cores in the E4, E6 and E8 series SoCs in the Alif
Ensemble family share identical Cortex-M55 CPU configuration.
Introduce SOC_FAMILY_ENSEMBLE_RTSS helper symbol at the family
level to avoid duplicating these selects across series Kconfigs.
The helper will be reused by the E4 and E6 series being added in
subsequent patches.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
When the received data is less than expected, DMA timeout error may occur.
This happens because the DMA transfer is not completed and the TC
(Transfer Complete) flag is never set.
This change adds support for handling cases where the received data length
is smaller than the requested length, preventing false timeout errors.
The CL covers the following scenarios:
1. received < expected (e.g. requested 10 bytes, got 9 bytes)
2. received = expected (e.g. requested 10 bytes, got 10 bytes)
3. received > expected
(e.g. requested 10 bytes, got 10 bytes, but more data is coming, T-bit = 1)
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
- Adds missing flash runner configuration for mcxn/e/w
used for sysbuild multi-image projects.
- Avoids sysbuild multiple resets and mass erases.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
The nrf54l soc init configures power and clock properties like
applying trims, capacitance and setting up regulators. This must
precede the grtc driver initializing the sys clock, as it depends
on these clocks being initialized on the nrf54l series socs.
Update the nrf54l soc init to be EARLY 0, and set grtc sys clock
driver init to EARLY 1. Additionally add comments explaining why
these specific init levels where chosen.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
