Fixes various issues with how these have been used:
- Reserved memory was wrongfully used to describe an RRAM area
for a CPU
- Reserved memory was wrongfully used to describe an SRAM area
for a CPU
- A partition described using reserved memory did not have the
required NVM erase size and write size parameters set for it
- RRAM partitions were not correctly setting ranges properties
- RRAM validation wrongly took the "base flash controller" into
considering because it was not using unit addresses
- RRAM partitions incorrect set up so that they collided with
one another for different cores
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Move camera XCLK setup from DVP driver (POST_KERNEL) to esp_lcd_cam.c
(PRE_KERNEL_2) to ensure the image sensor receives clock before its
I2C initialization. This fixes a race condition where sensors like
ov2640 would fail to respond during probe because XCLK wasn't yet
configured.
Also adds timestamp to captured video buffers and removes a noisy
error log for set_selection when the source returns -ENOSYS.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The `.resource_table` section was not declared anywhere, leading to an
"orphan section" linker warning when OpenAMP was used with the resource
table enabled.
Fix it by adding the missing section to the SoC-specific linker script.
(the section is identical to the one defined for STM32MP1x series)
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Move ble-controller integration to mcux-sdk-ng to make future release
integration easier. Based on 25.09.00 release, same as the existing
version.
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
The value os board qualifiers in CMake and Kconfig differs.
CMake has a leading '/', as example:
CMake: BOARD_QUALIFIERS=/nrf52840
Kconfig: BOARD_QUALIFIERS=nrf52840
This was also discussed in
https://github.com/zephyrproject-rtos/zephyr/pull/69740
This commit aligns the value of the CMake variable BOARD_QUALIFIERS to
the value of BOARD_QUALIFIERS (CONFIG_BOARD_QUALIFIERS) in Kconfig.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
The TCM ECC is enabled by default after reset, so must initialize
the entire DTCM with word-aligned writes to generate vaild ECC bits
before any byte or halfword access, otherwise ECC faults will occur.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
The cmsis_dsp tests were failing on the m55 due to incorrect
instructions being generated. Enabling Helium (MVEI/MVEF)
fixes the issue and most of the tests now pass.
Several tests are still failing unfortunately but no longer are
the tests failing on an vld1.16 instruction.
Signed-off-by: Tom Burdick <thomas.burdick@infineon.com>
Add initial support for the Versal SoC APU, which is based on
the Arm Cortex-A72 processor. It includes basic wiring for memory
regions, UART, interrupt controller, and timer.
This commit introduces the SoC definition and MMU configuration
required for APU-based development on the Versal platform.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
Enable WDT_DISABLE_AT_BOOT by default for MCXE24X SoC series to prevent
unexpected system resets during initialization and development.
Signed-off-by: Yves Wang <zhengjia.wang@nxp.com>
The synchronous send helper intel_adsp_ipc_send_message_sync() had
inverted logic for determining when to wait for host acknowledgment.
Before this fix, the function would:
- Return immediately (without waiting) when send succeeded (ret == 0)
- Try to wait on semaphore when send failed (ret < 0)
This is backwards. The correct behavior is to wait for the host ACK
semaphore only when the message was successfully queued for
transmission.
The inverted logic caused multiple test failures:
- HDA tests received -EBUSY on subsequent sends because tx_ack_pending
remained true when no wait occurred
- Smoke IPC tests timed out waiting for msg_flag/done_flag because
messages were sent without waiting for host responses
- Clock calibration tests failed because timestamp responses were never
received
This aligns the SoC glue implementation with the test-local helper
implementations and restores the original pre-refactoring behavior.
Related to: #102103
Related to: #102106
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Add initial support for the Versal Gen 2 SoC APU, which is based on
the Arm Cortex-A78 processor. It includes basic wiring for memory
regions, UART, interrupt controller, and timer.
The versal2_apu.dtsi file defines peripherals shared across the SoC,
while versal2_a78.dtsi captures peripherals private to the Cortex-A78
processor. These device trees lay the groundwork for further APU-based
development on the Versal Gen 2 platform.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
Implement cyw20829 SoC specific flash power down before
entering deep sleep and power up on wake. This reduces
the overall power consumption during deep sleep
Signed-off-by: Merin George <merin.george@infineon.com>
The new node is called "npu_cache".
This way a possibility is offered to choose - thru an overlay - if to
enable the NPU cache or not.
This new node has a dependency with node "npu", so the NPU cache's
status is taken into account only in case node "npu" has status "okay".
Default status value of "npu_cache" is "okay"
(i.e. enable the NPU cache).
Signed-off-by: Wolfgang Betz <wolfgang.betz@st.com>
Remove inclusion of files already included by the arch linker script from
the SoC-specific linker script.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
STM32MP1 series used a custom SOC_LINKER_SCRIPT, but all it did was
include the main Cortex-M script, unnecessarily re-include headers already
included by the main script(!) and add a custom section.
Get rid of the custom SOC_LINKER_SCRIPT but keep the custom section by
moving it to a linker script snippet file, added to the build system using
CMake directives.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
SYSTEM_WORKQUEUE_STACK_SIZE KConfig is setting to 1024 in case of
BT_TX_PROCESSOR_THREAD is enabled, else 2048.
BT_TX_PROCESSOR_STACK_SIZE KConfig is setting to 2048 in case of
BT_TX_PROCESSOR_THREAD is enabled.
Signed-off-by: Vincent Tardy <vincent.tardy@st.com>
Due to multiple customer requests we are deprecating the MEC5 HAL.
Customers prefer all code to be in the main Zephyr tree. They do
not want a dependency on an outside SoC HAL. These changes remove
the MEC5_HAL select from MEC165xB, MEC174x, and MEC175x. The SoC
code calling the HAL for debug configuration was replaced with
a small amount of code common to all SoC's. We also moved all
the common header includes into a common SoC header to prevent
changing multiple files if new common headers are added.
Note: the in-tree drivers: kernel timer, GPIO, PINCTRL, and UART
are all non-HAL.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Add initial support for the PSOC 4100S Max series, starting
with the CY8C4149AZI-S598 (100-TQFP package) used on the
CY8CKIT-041S-MAX development board.
The infrastructure supports adding additional part numbers
in the future as needed.
Signed-off-by: Braeden Lane <Braeden.Lane@infineon.com>
Provide some information on how to find the command that is used for
generating the UICR hex file so that its easier for users to
know what command to use.
Signed-off-by: Håkon Amundsen <haakon.amundsen@nordicsemi.no>
Remove the root clock control early initialization because it has
already been done in the soc_reset_hooks()
Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
This commit updates the source files for Renesas RA initialization:
- The SoC reset/init now uses generic hooks from the
"soc/renesas/ra/common" instead of SoC-specific initialization hooks.
- Add soc_reset_hooks() to perform the early reset code.
- Battery-backup domain initialization has been removed from
soc_early_init() and reallocated to soc_reset_hooks().
Signed-off-by: The Nguyen <the.nguyen.yf@renesas.com>
Signed-off-by: Khoa Tran <khoa.tran.yj@bp.renesas.com>
Select KERNEL_NO_LTO only when LTO is enabled. This ensures proper
handling when kernel code is placed in RAM.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
