Commit graph

2589 commits

Author SHA1 Message Date
David Ullmann
bcc7499684 drivers: rt6xx ctimer pwm driver
using ctimer to implement pwm api
Signed-off-by: David Ullmann <davidu@meta.com>
2023-08-03 12:39:06 -04:00
Nicolas Pitre
9a748371eb timer: allow for configuring it out
Some configurations have the system timer driver hardwired in.
Let's make them compatible with CONFIG_SYS_CLOCK_EXISTS=n.

Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
2023-08-03 10:29:46 +02:00
Manuel Argüelles
12627d329e soc: nxp_s32: s32k344: add EMAC support
This device has a single instance of EMAC (a 100Mbps version of GMAC).
TCP/UDP checksum calculation is offloaded.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-08-03 10:28:20 +02:00
Ioannis Karachalios
34ce476ce6 soc: smartbond: da1469x: Support Global Foundries silicon
Add support for the GF silicon variant.

Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
2023-08-02 14:00:39 +02:00
Manuel Argüelles
c7200cac00 soc: nxp_s32: add LPSPI to S32K344
Reuse existing NXP LPSPI binding for this SoC since the hardware block
for this device is the same as the one supported for other NXP devices.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-08-01 09:51:16 +02:00
Henrik Brix Andersen
de656c1169 drivers: can: sam: do not select cache management
Do not select CONFIG_CACHE_MANAGEMENT in the Microchip SAM CAN driver
Kconfig but rather leave it up to the SoC/platform Kconfig to enable it as
needed and enable CACHE_MANAGEMENT by default for the Atmel SAM E70/V71 SoC
series.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2023-07-31 19:38:22 +00:00
Antoine Bout
dbea999347 soc/arm/silabs: Kconfig: add SOC_GECKO_USE_RAIL kconfig option
Currently on zephyr, RAIL is used only for bluetooth. RAIL library is
needed to use efr32 radio regardless of the protocol used. We add
SOC_GECKO_USE_RAIL kconfig option to indicate if we use radio.
FPU is needed when using RAIL, we configure it if SOC_GECKO_USE_RAIL
is set.

Signed-off-by: Antoine Bout <antoine.bout@silabs.com>
2023-07-31 09:05:17 +00:00
Gerard Marull-Paretas
0b49b86f06 soc: arm: st_stm32: remove redundant PM_STATE_ACTIVE case
pm_state_exit_post_ops() will never be called with PM_STATE_ACTIVE.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-07-28 09:09:01 +00:00
David Ullmann
724a5cd54f board: add cy8ckit 062 pioneer
Tested with hello_world and blinky projects
Signed-off-by: David Ullmann <davidl.ullmann@gmail.com>
2023-07-27 15:26:40 -04:00
Cong Nguyen Huu
3d1285bc40 drivers: i2c_mcux: update to compatible with S32K344
Update to shim driver compatible with the hardware block
in S32K344. Configure the pins before initializing I2C
to avoid happening bus busy.

Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
2023-07-27 12:32:07 -05:00
Cong Nguyen Huu
36d63e132d boards: arm: mr_canhubk3: enable support for FlexCAN
Reuse existing MCUX-based shim driver for FlexCAN.
Enable flexcan0 for Zephyr canbus to run tests.

Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
2023-07-27 11:06:45 -05:00
Carles Cufi
acb8f6bf0b soc: nordic_nrf: Add nRF52833 QDAA variant
This variant has fewer pins.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2023-07-27 08:47:35 +00:00
Carles Cufi
b140963557 soc: nordic_nrf: Add nRF52840 QFAA variant
This variant has fewer pins.

Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
2023-07-27 08:47:35 +00:00
Andriy Gelman
d8f955e375 drivers: pwm: Add driver for xmc4xxx using ccu8 module
Adds driver for pwm on xmc4xxx using Capture Compare Unit 8 (CCU8)
module. There are two CCU8 nodes with each one having four slices.
Each slice has two output channels.

Unlike CCU4, this module can generate complementary high-side/low-side
signals for each output channel. A variable dead time can be added
during the off to on transitions to make sure that the
high-side/low-side signals are not on at the same time.

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2023-07-26 15:09:41 +02:00
Andriy Gelman
23b6e4f507 drivers: pwm: Add driver for xmc4xxx using ccu4 module
Adds driver for pwm on xmc4xxx using Capture Compare Unit 4 (CCU4)
module. There are four CCU4 with each one having four channels
Thus it's possible to have up to 16 pwm output signals. The output of
each channel can only be connected to a specific port/pin. The possible
connection and gpio configurations are defined using pinctrl.

The CCU4 module also has a capture mode. Capture support will be added
in the future.

Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
2023-07-26 15:09:41 +02:00
Wojciech Sipak
69d0f03ebd soc: quicklogic_eos_s3: remove unneeded code
Pinmuxing is now done by a pinctrl driver, not by board.c,
so the code used previously for pinmuxing can be removed.

Fixes #59186.

Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
2023-07-26 14:59:59 +02:00
Wojciech Sipak
bff69f5384 drivers: pinctrl: add driver for EOS S3
This adds a new pinctrl driver for Quicklogic EOS S3 SoC

Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
2023-07-26 14:59:59 +02:00
Wojciech Sipak
40fa96506b drivers: pinctrl: Add pinctrl driver for Gecko Series 1
This adds a new pinctrl driver for EFM32.

Co-authored-by: Todd Dust <Todd.Dust@silabs.com>
Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
2023-07-26 14:33:03 +02:00
Florian Grandel
d34709121f drivers: cc13xx_cc26xx: pinctrl: support edge detection
Introduces support for SoC-specific input-edge-detect configuration to
the CC13/26xx pinctrl driver.

Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
2023-07-26 14:32:53 +02:00
Florian Grandel
0dcbb22265 drivers: cc13xx_cc26xx: pinctrl: support drive strength
Introduces support for drive-strength configuration to the CC13/26xx
pinctrl driver.

Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
2023-07-26 14:32:53 +02:00
Florian Grandel
31fb5f53d2 drivers: cc13xx_cc26xx: pinctrl: fix header conflict
CC13/26xx's pinctrl_cc13xx_cc26xx.c driver included ioc.h and
(indirectly) pinctrl_soc.h which contained duplicate defines.

This change removes the header conflict and redundant definitions.

This prepares for subsequent changes in this change set that add
additional flags to the pinctrl driver which would otherwise trigger the
header conflict.

Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
2023-07-26 14:32:53 +02:00
Andrzej Głąbek
fa609e5844 drivers: spi: nrfx: Clean up driver instantiation
- use CONFIG_HAS_HW_NRF_* symbols consistently in nRF multi-instance
  drivers when creating particular driver instances
- remove unnecessary hidden Kconfig options that indicated the type of
  peripheral to be used by a given instance (e.g. SPI, SPIM, or SPIS)
  and enabled proper nrfx driver instance; instead, use one option per
  peripheral type and include the corresponding shim driver flavor into
  compilation basing on that option (not the one that enables the nrfx
  driver as it was incorrectly done so far in some cases)

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2023-07-25 13:41:51 +02:00
Carlo Caione
15e84cbfac dts: Move to 'zephyr,memory-attr'
Move to 'zephyr,memory-attr' and use the newly introduced helpers.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2023-07-25 11:22:10 +02:00
Fabio Baltieri
e065e5c600 soc: silabs_exx32: define an empty pm_state_exit_post_ops
Some EFR32 build broke after 3d2194f11e with:

pm.c:152: undefined reference to `pm_state_exit_post_ops'

Add an extra empty function to make this one build again.

Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
2023-07-25 10:43:33 +02:00
Wojciech Sipak
e9613856cb boards: arm: add efm32gg_sltb009a board
- Add Silabs SLTB009A board
- Add Silabs EFM32GG12B SoC

Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
2023-07-25 09:11:11 +02:00
Mathieu Anquetin
3e2765cc0d dts: arm: st: Add dts and soc additions for stm32f105xb
Added dts additions for stm32f105xb cpu which is the same as existing
stm32f105xc with less flash.

Signed-off-by: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
2023-07-24 14:15:42 +00:00
Peter van der Perk
6971865d01 soc: nxp_imx: rt11xx enable xbar driver
Add bindings to nxp,mcux-bar dirver

Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
2023-07-24 08:29:21 -05:00
Grant Ramsay
c0d144b3cd soc: arm64: add comments expanding the K3 acronym
This may be useful to users who do not know what K3 means

Signed-off-by: Grant Ramsay <gramsay@enphaseenergy.com>
2023-07-24 09:10:09 +00:00
Derek Snell
e44314aeee soc: nxp_imx: rt5xx: fix part numbers in WLCSP
Dropped R from part numbers to match MCUXpresso SDK

Signed-off-by: Derek Snell <derek.snell@nxp.com>
2023-07-21 09:09:55 -05:00
Mulin Chao
f34fff91bc driver: flash: npcx: introduce npcx flash driver
This CL attempts to implement npcx's flash driver instead of the
original one (npcx spi driver plus spi_nor flash driver).

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2023-07-20 16:22:47 +02:00
Mulin Chao
7411fbcb5b pinctrl: npcx: add DEV_CTLx configuration support
Add a new pinctrl type to control peripheral modules' specific IO
characteristics such as tri-state, the power supply type selection (3.3V
or 1.8V), and so on. In NPCX series, the corresponding registers/fields
are irregular. This CL wraps these definitions to dt nodes and put them
in pinctrl property if needed.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2023-07-20 16:22:47 +02:00
Gerard Marull-Paretas
55f5a75c58 pm: remove unnecessary __weak from pm_state_set/pm_exit_post_ops
Remove unnecessary __weak attribute from power management functions.
These functions are now defined once, globally, and mandatory for
systems that support CONFIG_PM.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-07-20 10:33:00 +00:00
Gerard Marull-Paretas
3d2194f11e pm: introduce HAS_PM
Add a new Kconfig option that has to be selected by SoCs providing PM
hooks. This option will be now required to enable CONFIG_PM. Before this
change, CONFIG_PM could always be enabled, regardless of SoC providing
any kind of low-power support.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-07-20 10:33:00 +00:00
Gerard Marull-Paretas
26bf349ab1 pm: drop HAS_NO_PM
Remove HAS_NO_PM option, in preparation for a new HAS_PM option
(inverted logic).

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-07-20 10:33:00 +00:00
Wojciech Sipak
c811a4f430 drivers: adc: add ADC driver for EFM32
This adds a driver for ADCs available on EFM32

Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
2023-07-18 11:05:39 +00:00
Emilio Benavente
c6e3bac4f2 soc: arm: lpc55xxx: Updated clock init
Updated the clock init to reflect the sdk also
updated the clock frequencies to reflect the
respective soc clock values, this file originally
contained unexpected clock values, updated comments
to reflect changes and got rid of doxygen style
comments

Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
2023-07-17 13:05:44 -05:00
L Lakshmanan
71244acd22 board: ti_am62x_sk_m4: Added board files for TI AM62X SK
Added configuration and documentation files for the AM62x board
M4 core.

Signed-off-by: L Lakshmanan <l-lakshmanan@ti.com>
2023-07-16 07:33:34 -04:00
L Lakshmanan
0e97c9d14d soc: ti_k3: Added SoC files for Cortex M4F on ti_am62x_sk
Added SoC support files for the Cortex M4F core on the TI AM62X SK EVM.

Signed-off-by: L Lakshmanan <l-lakshmanan@ti.com>
2023-07-16 07:33:34 -04:00
Guillaume Gautier
8432081f51 soc: arm: st_stm32: stm32wba: Add LPTIM to Kconfig
For STM32WBA, enable LPTIM if Power management is enabled

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2023-07-12 11:48:10 +02:00
Guillaume Gautier
38722ce9d0 soc: arm: st_stm32: stm32wba: Add Power support
Add Power support

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2023-07-12 11:48:10 +02:00
Guillaume Gautier
3bd3f8d1c6 soc: arm: st_stm32: stm32wba: Add soc config for STM32WBA
Add soc config for STM32WBA SoC series

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2023-07-11 15:05:05 +02:00
Bill Waters
541482ff20 driver: i2c: infineon: Adding XMC4 I2C driver
- This includes the driver, test app, and sample app
- Only the boards\arm\xmc47_relax_kit board is supported for now

Signed-off-by: Bill Waters <bill.waters@infineon.com>
2023-07-11 09:43:19 +02:00
Florian Grandel
38e2eb8fe6 soc: ti: cc13/26xx: clean up include hierarchy
Removes duplicate code and inconsistencies in the naming of the
cc13xx_cc26xx devicetree and RTC driver hierarchy and alignes it with
the actual TI product series naming hierarchy.

Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
2023-07-07 18:46:24 -04:00
Andrzej Kuros
abd90085ac soc: arm: nrf53: workaround pop lr after wfi crash
On nRF5340 net core it was observed that when `wfi` instruction was
followed by `pop {r0, lr}` in the `arch_cpu_idle` function,
the value of `lr` sometimes got read as 0 from memory despite
having correct value stored in the memory.

This commit inserts additional `nop` instruction after waking up
to delay access to the memory.

Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
2023-07-07 14:32:27 +02:00
Marc Desvaux
4293835192 soc : arm: st_stm32: stm32h5: add linker for STM32H5X
add some modifications for linker

Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
2023-07-07 10:06:54 +00:00
Mulin Chao
2cf3caa11c driver: wdt: npcx: add WDT_OPT_PAUSE_HALTED_BY_DBG support.
This CL adds WDT_OPT_PAUSE_HALTED_BY_DBG support by enabling freeze mode.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2023-07-07 09:19:50 +02:00
Manuel Arguelles
405160ca62 boards: mr_canhubk3: enable LPUART serial driver
Reuse existing MCUX-based shim driver for LPUART that is compatible with
the hardware block in S32K344. DMA is not yet supported.

Use the board's debug connector (P6 / LPUART2) as default console.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-07-06 14:19:23 -05:00
Manuel Arguelles
00125a4d1e soc: nxp_s32: generalize pinctrl header for all family
Unify the pinctrl_soc.h header for all the NXP S32 family by using
the HAL macros that expose the features supported on specific
devices. This approach still need a different binding for each device to
expose in DT different properties and allowed values.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-07-06 14:19:23 -05:00
Manuel Arguelles
8a47dd5ff8 soc: nxp: s32k3: enable clock control
Enable clock control by default on S32K344 SoCs and add clock
definitions.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-07-06 14:19:23 -05:00
Manuel Arguelles
b22f1162f3 soc: nxp: s32k: support minimal power and reset
Introduce minimal power initialization for NXP S32 SoCs and allow to
reset the SoC through the sys_reboot() API.

Presently only S32K3 SoCs is supported but it can be extended later to
other NXP S32 SoCs, hence it's placed in a common directory.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-07-06 14:19:23 -05:00