Commit graph

2589 commits

Author SHA1 Message Date
Manuel Arguelles
d2985f118a soc: arm: introduce support for NXP S32K344
The S32K3 MCUs are 32-bit Arm Cortex-M7-based microcontrollers with a
focus on automotive and industrial applications. The S32K344 features
a lock-step core, internal flash, RAM and TCM with ECC.

Co-authored-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Co-authored-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-07-06 14:19:23 -05:00
Benedikt Schmidt
42051fc2d4 dts: arm: st: add STM32L451
Add the MCU STM32L451.

Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
2023-07-06 09:46:14 +00:00
Gerard Marull-Paretas
fcaa259e22 soc: arm: remove all unnecessary NMI_INIT() calls
NMI_INIT() is now a no-op, so remove it from all SoC code. Also remove
the irq lock/unlock pattern as it was likely a cause of copy&paste when
NMI_INIT() was called.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-07-05 09:15:36 +02:00
Sumit Batra
0ae7010946 soc: rt10xx: fix the sequence of Enet2 ref clk enablement
This patch sets ENET2 ref clock to be generated by External OSC

ENET2 ref clock direction as output

ENET2 ref clk frequency to 50MHz

Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
2023-07-03 15:24:00 -05:00
Manimaran A
f6eeb9dc84 soc: MEC1701: Removed Microchip MEC1701
Removed MEC1701 SOC specific sources

Signed-off-by: Manimaran A <manimaran.a@microchip.com>
2023-07-01 12:38:07 +02:00
Manuel Argüelles
c651dfbb2b soc: nuvoton_numaker: add guard in defconfg
It must be guarded so the option selection doesn't appear at root level.

Fixes #59876

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-06-30 16:47:51 +02:00
cyliang tw
51d57f612d drivers: pinctrl: add pin group for NuMaker pinctrl
Update Nuvoton numaker series pinctrl, let support pin group.

Signed-off-by: cyliang tw <cyliang@nuvoton.com>
2023-06-28 06:49:38 +00:00
Florian Grandel
b245012ca2 drivers: ieee802154: cc13/26xx_subg: R-to-P link workaround
A known issue exists that does not allow a CC13/26x2R device to
establish a link to a CC13/26x2P device unless the capacitor array is
tuned to a non-default value in the P device.

See SimpleLink(TM) cc13xx_cc26xx SDK 6.20+ Release Notes, Known Issues.

Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
2023-06-23 09:20:55 +02:00
Florian Grandel
c6c93e394d soc: cc13x2_cc26x2 series: enable RTT support
All Cortex-M processors can support RTT by default. This change enables
RTT support for the cc13xx/cc26xx SoC series (tested in hardware on
CC1352R).

Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
2023-06-21 20:02:50 -04:00
Huifeng Zhang
c1ecb8faaa arch: arm: enable FPU and FPU sharing for v8r aarch32
This commit is to enable FPU and FPU_SHARING for v8r aarch32.

Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
2023-06-21 16:06:08 +02:00
cyliang tw
c448dceb57 drivers: reset: add support for NuMaker series reset
Add Nuvoton numaker series reset controller support.

Signed-off-by: cyliang tw <cyliang@nuvoton.com>
2023-06-21 09:26:00 +00:00
cyliang tw
4ad399d54d drivers: clock_control: add support for Nuvoton numaker series CLK
Add Nuvoton numaker series clock controller support, including:
1.  Do system clock initialization in z_arm_platform_init().
2.  Support peripheral clock control API equivalent to BSP
    CLK_EnableModuleClock()/CLK_SetModuleClock().

Signed-off-by: cyliang tw <cyliang@nuvoton.com>
2023-06-21 09:26:00 +00:00
cyliang tw
5879810137 drivers: pinctrl: add support for NuMaker series pinctrl
Add Nuvoton numaker series pinctrl support.

Signed-off-by: cyliang tw <cyliang@nuvoton.com>
2023-06-21 09:26:00 +00:00
cyliang tw
512371b75b soc: arm: add support for nuvoton numaker m46x series
Add initial support for nuvoton numaker m46x SoC series including
basic init.

Signed-off-by: cyliang tw <cyliang@nuvoton.com>
2023-06-21 09:26:00 +00:00
Piotr Wojnarowski
ff9fe7271a soc: arm64: fvp_aemv8: Move GIC version to DT
Move the GIC version to the device tree for fvp_aemv8{a,r}
to improve readability

Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
2023-06-17 08:01:46 -04:00
Piotr Wojnarowski
fc29f73a29 soc: arm: xilinx_zynqmp: Move GIC version to DT
Move the GIC version to the device tree for xilinx_zynqmp
to improve readability

Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
2023-06-17 08:01:46 -04:00
Piotr Wojnarowski
0835a99fac soc: arm: renesas_rcar: Move GIC version to DT
Move the GIC version to the device tree for renesas_rcar
to improve readability

Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
2023-06-17 08:01:46 -04:00
Piotr Wojnarowski
48ba2aec6a soc: arm: cyclonev: Move GIC version to DT
Move the GIC version to the device tree for cyclonev
to improve readability

Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
2023-06-17 08:01:46 -04:00
Piotr Wojnarowski
bca43d3eaf soc: arm: nxp_s32: Move GIC version to DT
Move the GIC version to the device tree for nxp_s32
to improve readability

Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
2023-06-17 08:01:46 -04:00
Piotr Wojnarowski
95c1a7e83f soc: arm: xilinx_zynq7000: Move GIC version to DT
Move the GIC version to the device tree for xilinx_zynq7000
to improve readability

Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
2023-06-17 08:01:46 -04:00
Manimaran A
0f6cb5edcd drivers: ps2: microchip: Low power and wakeup enabled
ps2 driver updated to support low power and wakeup.

Signed-off-by: Manimaran A <manimaran.a@microchip.com>
2023-06-17 07:59:07 -04:00
Marcin Zapolski
f9baca493c soc: arm: stm32l4: Add STM32L4Q5 support
Add STM32L4Q5 to the list of supported SOCs.
Fix copy-paste error in STM32L4P5 SOC file.

Signed-off-by: Marcin Zapolski <mz4pol@gmail.com>
2023-06-17 07:56:49 -04:00
Gerard Marull-Paretas
c0bc9f974f drivers: pinctrl: add TI CC32XX driver
Add a new pinctrl driver for TI CC32XX SoC. The driver has not been
tested, just implemented following datasheet specs and checked that it
compiles. Consider this as a best-effort driver to remove custom pinmux
code in board files.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-06-17 07:55:43 -04:00
Daniel DeGrasse
9c6853c42f soc: arm: nxp_imx: do not enable RT boot header for CM4 core
Disable RT boot header for CM4 core. This will ensure the boot header is
not present when building an application targeting RAM on the CM4.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-06-17 07:50:46 -04:00
Carlo Caione
7a48ad34d9 nordic: Rely on internal busy_wait implementation for QEMU
The Nordic board are selecting CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT by
default and rely on some HAL code to implement a cycle accurate busy
delay loop.

This is in general fine for real hardware but when QEMU and emulation is
taken into account, a cycle accurate busy wait implementation based on
delay in executing machine code can be misleading.

Let's take for example qemu_cortex_m0 (that is based on the nRF51
chipset) and this code:

  uint32_t before, after;

  while (1) {
      before = k_cycle_get_32();
      k_busy_wait(1000 * 1000);
      after = k_cycle_get_32();
      printk("diff cycles: %d\n", after - before);
  }

With CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1000000 this diff cycles should
be always around 1000000, in reality when executed with:

  qemu-system-arm -cpu cortex-m0 -machine microbit -nographic
      -kernel build/zephyr/zephyr.elf

This results in something like this:

  diff cycles: 22285
  diff cycles: 24339
  diff cycles: 21483
  diff cycles: 21063
  diff cycles: 21116
  diff cycles: 19633

This is possibly due to the fact that the cycle accurate delay busy loop
is too fast in emulation.

When dealing with QEMU let's use the reliable busy loop implementation
based on k_cycle_get_32() instead.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2023-06-05 20:20:54 -04:00
Mahesh Mahadevan
0602ef8647 soc: nxp_lpc: Add USBFS support
1. Add support for the USB Full Speed controller
2. Add a Kconfig to specify if a dedicated USB
   RAM is available in the SoC.

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2023-05-26 17:53:37 -04:00
Daniel DeGrasse
ac0ae62b58 soc: arm: nxp_imx: add FLEXSPI1 and FLEXSPI2 memory sections for RT5xx
Add FLEXSPI1 and FLEXSPI2 memory sections for RT5xx SOC. These sections
can be used by the user's application as part of a custom linker script,
if the application needs to relocate a buffer to external SRAM connected
to FLEXSPI1 or FLEXSPI2

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-05-26 10:21:34 -05:00
Filip Kokosinski
c590f62613 soc/arm/silabs_ex32/efr32bg27: select CONFIG_SOC_GECKO_SE
This commits selects the `CONFIG_SOC_GECKO_SE` option for the BG27 SoC
series. This is required for BLE support, as it enables the inclusion of
the `sl_protocol_crypto` component from SiLabs HAL.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2023-05-26 05:54:40 -04:00
Niek Ilmer
abf9e4d1f4 scripts: runners: ezflashcli: Add support to flash images for MCUboot
Internal bootloader will only run application image if valid product
header is present on flash. This means product header is required for
application that are not linked to code partition. Other applications
that are linked to code partition are meant to be run by MCUboot and
should not touch product header, with the exception of MCUboot itself
which is also run by internal bootloader so requires product header.

Default flash load offset for applications not linked to code partition
is set to 0x2400 as this is where internal bootloader looks for an
application image to run based on product header written by flasher.

Flash load offset for MCUboot is set from boot partition.

Valid product header is added by ezFlashCLI when using "flash_image"
command.

Co-authored-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Niek Ilmer <niek.ilmer.aj@renesas.com>
2023-05-26 05:53:02 -04:00
Niek Ilmer
ffdbf05a47 soc: arm: smartbond: Reconfigure cache on init
Applications that are run from MCUboot should reconfigure cache to
ensure they run from cached ared on flash. Initial cache configuration
is done by internal bootloader and is valid for MCUboot only.

Cache is configured once at boot, then new configuration is applied by
triggering SW reset.

Co-authored-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Niek Ilmer <niek.ilmer.aj@renesas.com>
2023-05-26 05:53:02 -04:00
Niek Ilmer
d39ada2248 soc: arm: smartbond: Set flash base address
Flash address is updated to 0x16000000, i.e. actual location instead of
remapped one. FLASH_BASE_ADDRESS is now set via dts.

Co-authored-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Niek Ilmer <niek.ilmer.aj@renesas.com>
2023-05-26 05:53:02 -04:00
Roman Dobrodii
a2d9f6fcbe soc/arm/silabs: bugfix - disable PMGR if no DEV_INIT
sl_power_manager can only be used if HAL services infrastructure
is enabled, and that is controlled by SOC_GECKO_DEV_INIT kconfig option.
Therefore, SOC_GECKO_PM_BACKEND_PMGR may not be enabled without
SOC_GECKO_DEV_INIT.

Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
2023-05-25 13:34:18 +00:00
Roman Dobrodii
defb159ab1 soc/arm/silabs: support BLE with PM in Series 2 SoCs
Using EM2 or deeper sleep states (where HF clocks are off) requires
special care if BLE radio is used, since BLE radio relies on that clock,
and its power/clock requirements need to be taken into account
On SiLabs, radio PM is implemented as part of RAIL blob, which relies
on sl_power_manager HAL service. I've implemented SoC PM
state changes using sl_power_manager instead of emlib, and added
call to RAIL PM initialization in Gecko HCI driver.

Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
2023-05-24 13:31:44 -04:00
Carlo Caione
6f3a13d974 barriers: Move __ISB() to the new API
Remove the arch-specific ARM-centric __ISB() macro and use the new
barrier API instead.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2023-05-24 13:13:57 -04:00
Carlo Caione
cb11b2e84b barriers: Move __DSB() to the new API
Remove the arch-specific ARM-centric __DSB() macro and use the new
barrier API instead.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2023-05-24 13:13:57 -04:00
Jeppe Odgaard
eed2de8c03 soc: rt10xx: add flexspi clock functions
Add SOC specific function to set the flexspi clock divider and get the
flexspi clock frequency.

Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
2023-05-22 10:15:03 +02:00
Kamil Serwus
632704e04b sam: can: CAN driver for SAM0 socs
Driver was based on can_sam. SAMC21 has only 1 interrupt for one
can "output", so can interrupt has to executes two lines of
interrupts.
CAN is configured to use OSC48M clock via GLCK7. GLCK7 is set
by divider configured from dts.

Signed-off-by: Kamil Serwus <kserwus@gmail.com>
2023-05-22 08:03:58 +00:00
Sumit Batra
7dce14632d soc: arm: nxp_imx: support enet2 interface on RT106x series
This patch enables the PLL clock output and PLL ref clock
for second ethernet module in NXP's i.MxRT106x SoCs

Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
2023-05-18 14:08:06 -05:00
Mike J. Chen
7c0784db36 mimxrt595_evk: add i3c
Add i3c to device tree and the clock init to soc.c

Signed-off-by: Mike J. Chen <mjchen@google.com>
2023-05-17 09:34:31 -05:00
Mulin Chao
9da9c90639 intc: miwu: npcx: improve interrupt latency of miwu input events
To reduce the interrupt latency of MIWU events, the driver prepares a
dedicated callback function item list for each MIWU group in this PR. We
needn't check the MIWU table and group of the event in ISR. And the
maximum item number of each list is also limited to 8. After applying
this PR, the interrupt latency reduces to ~10us consistently.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2023-05-17 09:48:54 +02:00
Sreeram Tatapudi
ea591e2899 drivers: bluetooth: Add Infineon Bluetooth driver
Add initial version of the Bluetooth driver for
the cy8cproto_063_ble board

Signed-off-by: Sreeram Tatapudi <sreeram.praveen@infineon.com>
2023-05-17 09:59:36 +03:00
Manimaran A
f8c8ee65be drivers: pinctrl: Microchip XEC PINCTRL glitch fix
Glitches were observed if a GPIO pin was configured by
ROM to a non-default state and then Zephyr PINCTRL
reconfigured the pin. The fix involves using the correct
PINCTRL YAML output enable and state flags. Reading the
current spin state and reflecting into new pin configuration
if the pin is output and the drive low/high properties are
not present. We also take advantage of GPIO hardware reflecing
the alternate output value in the parallel output bit before
enabling parallel output mode. Interpret boolean flags with
both enable and disable as do not touch if neither flag is
present. We give precedence to enable over disable if both
flags mistakenly appear. Note, PINCTRL always clears the
GPIO control input pad disable bit.

Signed-off-by: Manimaran A <manimaran.a@microchip.com>
2023-05-16 18:52:44 -04:00
Mahesh Mahadevan
df26e99637 pm: rt5xx: Enable OS Timer as wakeup source
1. Enable os_timer as a wakeup-source in the board
   dts file.
2. Enable PM_DEVICE when PM is enabled.

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2023-05-16 18:19:35 +02:00
Oliver King
a13858e132 soc: stm32wl: Added logging declaration to soc.c
Added logging declaration to soc.c of stm32wl, which resolves build
errors when using this SOC with DEBUG logging level

Fixes: #57655

Signed-off-by: Oliver King <oliver.king@steadconnect.com>
2023-05-15 09:59:22 +00:00
Yves Vandervennet
0f87666126 i2s : mimxrt595_evk_cm33: enablement of driver
board:

 - update device tree to use flexcomm devices to the chip design
 - enable clocks (soc init file)
 - setup connections for loopback test in system controller (board init
   file)

tests:

 - update board files (overlay, conf)

Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
2023-05-12 13:50:33 -05:00
Daniel DeGrasse
b3fd44a4ac soc: arm: nxp_imx: add KConfig definitions for RT1042
Add Kconfig defintions for RT1042 SOC, including part numbers and SOC
feature selections.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-05-11 10:35:40 -05:00
Daniel DeGrasse
746758d1f6 drivers: display: update MCUX ELCDIF driver to use new lcdif binding
Update MCUX ELCDIF driver to use new LCDIF bindings. This
update also adds support for configuring the root clock of
the ELCDIF module based on the pixel-clock property to the
RT11xx SOC clock init, as this SOC series has this IP block

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-05-11 10:04:24 +02:00
Daniel DeGrasse
a4afa7d164 drivers: update DCNANO LCDIF IP to use shared LCDIF binding
Update DCNANO LCDIF IP to use shared lcd interface binding. This
requires changes to the RT5xx SOC and RT595 EVK, as this SOC
uses the LCDIF IP, and configures the clock for it based off
the new pixel-clock property.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-05-11 10:04:24 +02:00
Daniel DeGrasse
98408b1733 dts: mipi_dsi: introduce phy-clock property
Introduce phy-clock property, which is used by MIPI devices to determine
the target clock frequency for the MIPI PHY. This property can vary
depending on the attached display and target framerate.

Update the MIPI DSI MCUX driver to utilize this property to configure
the MIPI host, and update the RT500 clock initialization to configure
the MIPI root clock based on this property.

Remove dphy-clk-div property from the MIPI DSI 2L binding, as it
is redundant with this change.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-05-11 10:04:24 +02:00
Maxime Vincent
012663f178 soc: arm: nxp: add lpc55s16jbd64
Add support for lpc55s16jbd64 chip variant

Signed-off-by: Maxime Vincent <maxime@veemax.be>
2023-05-10 10:15:14 +02:00