Commit graph

2589 commits

Author SHA1 Message Date
Gerard Marull-Paretas
d7a0b4fa93 soc: arm: st_stm32: u5: add support for sys_poweroff
Add support for the sys_poweroff hook, re-using code from the SOFT_OFF
state.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-31 10:18:07 +02:00
Gerard Marull-Paretas
b97b17a4f5 soc: arm: st_stm32: wb: add support for sys_poweroff
Implement the sys_poweroff() hook. The hsem locking is not part of the
implementation, it doesn't seem necessary after
https://github.com/zephyrproject-rtos/zephyr/pull/42409 but I may be
wrong. Needs verification.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-31 10:18:07 +02:00
Gerard Marull-Paretas
643383b060 soc: arm: st_stm32: l4: add support for sys_poweroff
Convert SOFT_OFF handler to sys_poweroff hook.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-31 10:18:07 +02:00
Gerard Marull-Paretas
11242691cd soc: arm: st_stm32: l0: remove unsupported state
SOFT_OFF state (which translates to standby) doesn't seem to be
supported according to the L0 DT files. Also, by definition soft off
implies context loss, ie boot from scratch, but the implementation
expected a call to the PM exit hook.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-31 10:18:07 +02:00
Gerard Marull-Paretas
00ff421129 soc: arm: nxp_imx: rt10xx: s/device.h/init.h
File was not using any device.h API, but init.h.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-30 11:53:50 +02:00
Gerard Marull-Paretas
b3b8a19e02 soc: arm: nuvoton_npcx: common: s/device.h/init.h
File was not using any device.h API, but init.h (SYS_INIT).

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-30 11:53:35 +02:00
Tristen Pierson
1f2180e8ff drivers: adc: adc_sam0: fix c20 and c21 reference not setting
drivers: adc: adc_sam0: fix c20 and c21 reference not setting

On c20 and c21 variants, the adc_sam0 driver is failing to honor the
enable-protected status of the REFCTRL register when writing the channel
config's reference into it. This causes the reference to never be set
when adc_sam0_channel_setup is called since the ADC is not disabled
prior to the write. Fix it by adding the
ADC_SAM0_REFERENCE_ENABLE_PROTECTED definition to the c20 and c21 soc.h
files. This effectively disables the ADC during writes to the REFCTRL
register, thus honoring the enable-protected behavior of this register.
I'm assuming ADC_SAM0_REFERENCE_ENABLE_PROTECTED exists for this type
of situation and therefore this was the approach taken. After making
the change, I was able to verify proper ADC readings by measuring
voltage on an ADC pin and observing correct values. Reverting back prior
to this change, running the same test yields reading 0's.

Fixes: #61975

Signed-off-by: Tristen Pierson <tpierson@bitconcepts.tech>
2023-08-30 10:21:15 +02:00
Francois Ramu
66caf58265 soc: arm: stm32h7x mapping system memory region
System memory declared by the MPU as 'Strongly Ordered'
with region attributes which will inhibit the speculative fetch,
preventing the Flash RDSERR.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2023-08-30 10:17:39 +02:00
Gerard Marull-Paretas
f88d21cdb9 soc: arm: nordic_nrf: nrf53: sync_rtc: add missing init.h
File was using SYS_INIT, from init.h.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-29 14:35:45 +01:00
Mulin Chao
f942b44c56 soc: arm: npcx: move workaround methods for npcx series to its soc.c
Move workaround methods for npcx series to soc init functions. If
there's no workaround for this series, drop its soc.c file directly.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2023-08-28 08:22:10 +01:00
Maximilian Deubel
4cde3ea70f soc: arm: nordic_nrf: nrf91: rename nRF9161 SICA to LACA
This patch corrects the name of the nRF9161,
which is LACA, not SICA.

Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
2023-08-25 13:48:17 +02:00
Maximilian Deubel
dc954977b7 soc: arm: nordic_nrf: nrf91: add nRF9131 LACA
This patch adds definitions for the nRF9131,
which is software-compatible with nRF9161.

Signed-off-by: Maximilian Deubel <maximilian.deubel@nordicsemi.no>
2023-08-25 11:56:12 +02:00
Mateusz Sierszulski
be149593c9 drivers: pinctrl: Add more config options for Ambiq Apollo4
This commits add more configuration options
for Ambiq Apollo4 pinctrl driver.

Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
2023-08-25 10:31:58 +02:00
Marcin Niestroj
19d7b26238 soc: arm: stm32h5: support SWO
In case of stm32h5 both LL_DBGMCU_EnableTraceClock() and
LL_DBGMCU_SetTracePinAssignment() need to be called in order to properly
configure SWO output.

Select HAS_SWO, so that logging over SWO can be enabled.

Tested with ST's fork of openocd [1].

[1] https://github.com/STMicroelectronics/OpenOCD

Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
2023-08-24 18:21:52 -05:00
Daniel DeGrasse
905512438e soc: arm: nxp_imx: update iMX RT boot header to handle CONFIG_XIP=n
Update iMX RT boot header to support CONFIG_XIP=n, when the image is not
linked into the flash space. Also, update the boot header to correctly
calculate the flash used size within the boot data header. This field is
used by the iMX boot ROM to determine how much data to copy when running
from RAM, so using the correct size fixes an issue where the ROM would
copy more data than needed.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-08-24 22:09:01 +01:00
Gerard Marull-Paretas
94a4d38ed9 cmsis: remove unnecessary includes
Some files included <cmsis_core.h> for nothing, delete it.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-08-24 13:20:21 +02:00
Gerard Marull-Paretas
9c961571a2 modules: cmsis: move glue code to modules/cmsis
The CMSIS module glue code was part of arch/ directory. Move it to
modules/cmsis, and provide a single entry point for it: cmsis_core.h.
This entry header will include the right CMSIS header (M or A/R).

To make this change possible, CMSIS module Kconfig/CMake are declared as
external, allowing us to add a new Zephyr include directory.

All files including CMSIS have been updated.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-08-24 13:20:21 +02:00
Jun Lin
df0646ed6e driver: flash: npcx: add support for npcx4 series
This CL introduces new Flash Interface Unit (FIU) hardware in npcx4
series. The different operations of npcx9 and npcx4 FIU include:

1. 4-byte mode support for DRA mode move to SPI_DEV reg
2. To access the second flash in DRA mode, we need to configure
   SPI_DEV_SEL field in BURST_CFG additionally.

Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
2023-08-24 10:42:33 +01:00
Mulin Chao
5c7ab5c2bf driver: clock_control: npcx: add support for npcx4 series
This CL introduces new clock architectures in npcx4 series and wraps
clock configurations of different series by device tree files.

For example, the PWDWN_CTLx reg initialization relies on `pwdwn-ctl-val`
prop of pcc DT node now.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2023-08-24 10:42:33 +01:00
Mulin Chao
8ae0bb8b70 soc: npcx: add soc drivers for npcx4 series
This CL adds the soc drivers for npcx4 series. Besides adding npcx4m3f
and npcx4m8f support, we also modified the register offset of
LV_GPIO_CTL and PUPD_EN for npcx4 series.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2023-08-24 10:42:33 +01:00
Jeff Daly
f868d391ec Samples: Fix XEC clock control sample code for MEC172x using new GPIOs.
The XEC clock control driver sample code uses enum indexes to offset to
the desired GPIO CTRL register of the package.  These enums are only
used in this example code and are being removed in favor of calculated
indexing into the specific GPIO register memory map.

Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
2023-08-23 10:06:13 +02:00
Moritz Fischer
9e8a8b4e85 soc: arm: common: cortex_m: Move arm_mpu_mem_cfg.h
Move arm_mpu_mem_cfg header to common include directory.

The benefits are two-fold:
- Allow for out of tree SoC definitions to use them to
  define mpu_regions.
- Remove odd relative include path

Signed-off-by: Moritz Fischer <moritzf@google.com>
2023-08-16 14:56:06 +02:00
Manuel Argüelles
298f028d20 soc: nxp_s32: rename family to SOC_FAMILY_NXP_S32
Rename NXP S32 device's family to SOC_FAMILY_NXP_S32 to avoid ambiguity.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-08-16 10:21:26 +02:00
Manuel Argüelles
acbdf1f53c modules: rename S32 to NXP_S32
Rename module from `S32` to `NXP_S32` to avoid ambiguity.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-08-16 10:21:26 +02:00
Henrik Brix Andersen
cafcf9a474 soc: arm: nxp: lpc55xxx: Change PLL1 frequency to 144 MHz
Reduce the main clock frequency from 150MHz to 144MHz which allows meeting
the full range of CAN bitrates.

Fixes: #60811

Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
2023-08-16 10:20:44 +02:00
Ederson de Souza
91450a4358 soc/arm/microchip_mec/mec17x: Initialise GPIO after ECIA
Since bb590b5b6e, which enforces a more consistent ordering of
initialisation for devices, the ECIA initialisation was happening after
GPIO initialisation. This caused interrupts to stop working on GPIO
input.

This patch fixes that by increasing the default GPIO initialisation
priority, so that it happens after ECIA.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2023-08-15 10:13:37 -07:00
Ederson de Souza
0295edf834 soc/arm/microchip_mec/mec1501: Initialise GPIO after interrupts
Since bb590b5b6e, which enforces a more consistent ordering of
initialisation for devices, the SOC initialisation was happening after
GPIO initialisation. This caused interrupts to stop working on GPIO
input.

This patch fixes that by increasing the default GPIO initialisation
priority, so that it happens after SOC.

Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
2023-08-15 10:13:37 -07:00
Tanmay Shah
33a25371b6 soc: zynqmp: increase SRAMP_PRIV MPU region size
openamp shared memory regions can be anywhere in DDR memory
withing 2G range. Current SRAM_PRIV region is 64M which
prevents access of shared memory (vrings) by RPU (cortex-r5)
if it is out of 64M range. This patch allows vrings to be in DDR within
2G address space.

Developed-by: Dan Millea
Commited by: Tanmay Shah

Signed-off-by: Dan Milea <dan.milea@windriver.com>
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
2023-08-15 11:23:04 +00:00
Benjamin Lemouzy
35849319e0 soc: arm: imx_rt10xx: support enet1 external clock
Configure ENET_REF_CLK direction as input when
CONFIG_ETH_MCUX_RMII_EXT_CLK is set to allow Ethernet external clock
usage.

Signed-off-by: Benjamin Lemouzy <blemouzy@centralp.fr>
2023-08-14 08:21:26 -05:00
Markus Fuchs
4fd5a9cee1 boards: efr32_radio: Add PM support using BURTC timer
Add power management support running in EM1 and EM2 from BURTC timer.

Signed-off-by: Markus Fuchs <markus.fuchs@ch.sauter-bc.com>
2023-08-09 08:24:52 +00:00
Markus Fuchs
536894bb31 boards: efr32_radio: Enable sleep timer
Enable sleep timer (stimer0) node for the efr32_radio_brd4187c board.

Signed-off-by: Markus Fuchs <markus.fuchs@ch.sauter-bc.com>
2023-08-09 08:24:52 +00:00
Markus Fuchs
27af62603c drivers: counter: gecko: Add SYSRTC stimer support
SiLabs' sleeptimer driver supports several hardware peripherals, of
which the counter driver so far only supports the RTCC-based variant.

This patch adds support for the SYSRTC-based sleeptimer implementation,
which is required for Gecko SoCs that do not have an RTCC module.

Signed-off-by: Markus Fuchs <markus.fuchs@ch.sauter-bc.com>
2023-08-09 08:24:52 +00:00
Gerard Marull-Paretas
b990082bef soc: arm: nordic_nrf: fix poweroff for nrf53/91
nRF53/91 require usage of nrf_regulators_system_off, so the API is not
common with nRF51/52. This was an oversight during the conversion.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-09 08:21:34 +00:00
Benjamin Perseghetti
109d91aaf8 board: Add NXP VMU RT1170 board support package
Adds support for the NXP VMU RT1170 board. This Vehicle
Management Unit based on the i.MX RT1176 brings a fantastic
combination of sensors and IO all on one board for development
of various systems. It is also the featured board for
CogniPilot's Cerebri - VMU autopilot software based on Zephyr.

Co-authored-by: Peter van der Perk <peter.vanderperk@nxp.com>
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
2023-08-08 12:09:10 -05:00
Daniel DeGrasse
c3dfc2220a soc: arm: nxp_imx: rt: Remove CONFIG_OCRAM_NOCACHE setting
Remove CONFIG_OCRAM_NOCACHE setting, as this is now possible to achieve
using devicetree linker regions, and there is no point in having a
specific Kconfig for one memory region on the RT series like this.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-08-04 16:11:37 -05:00
Daniel DeGrasse
7e646b56a1 soc: arm: nxp_imx: rt: enable SOC fixed MPU regions, add SDRAM0 region
Enable SOC fixed MPU regions by default for the RT10xx/RT11xx SOC lines.

Additionally, add code to handle defining the SDRAM0 region as
device type (non cacheable, non shareable). This behavior can
be disabled with CONFIG_NXP_IMX_EXTERNAL_SDRAM=y. Set this Kconfig
for all boards in tree using SDRAM.

This will resolve an issue present on the RT11xx series where
the core may execute speculative prefetches to the SDRAM region when
no SDRAM is present on the board, resulting in the system faulting.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-08-04 16:11:37 -05:00
Daniel DeGrasse
c85d3dd828 soc: arm: nxp_imx: don't default CONFIG_DEVICE_CONFIGURATION_DATA=y
Don't default CONFIG_DEVICE_CONFIGURATION_DATA to enabled for iMX RT
SOCs, as this configuration block is only used when the board needs
peripherals like the external memory controller setup from reset by the
bootrom.

Enable this feature on all in tree boards that will require it,
and document the change to the default value in release notes.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-08-04 16:11:37 -05:00
Gerard Marull-Paretas
2e3bc500a9 soc: arm: nxp_imx: rt5xx: drop SOFT_OFF
SOFT_OFF is now handled via sys_shutdown() API.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-04 16:59:36 +02:00
Gerard Marull-Paretas
b5d05e9670 soc: arm: nxp_imx: rt5xx: add support for power off
Implement support for sys_poweroff(). Code re-used from the PM SOFT_OFF
implementation.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-04 16:59:36 +02:00
Gerard Marull-Paretas
96b3827313 soc: arm: nordic_nrf: drop PM hooks
Nordic SoCs do all power management automagically when going to idle (ie
k_cpu_idle()). The only extra state, system off, is now handled via
sys_shutdown(), so there's no need to support the PM subsystem.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-04 16:59:36 +02:00
Gerard Marull-Paretas
526a7bb20d soc: arm: nordic_nrf: add support for poweroff
Implement the z_sys_poweroff() hook and select HAS_POWEROFF.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2023-08-04 16:59:36 +02:00
Manuel Argüelles
ab346c08b5 drivers: nxp_s32_netc: fix init priorities
So far the init priories were:
enetc_psi0=60 < enetc_vsin=61 < emdio=70 < ethernet-phy=80
because the Ethernet PSI driver was doing global initialization for the
whole NETC complex, including enabling MDIO function (due to the way
the HAL works).

Change to use the default init priorities:
mdio=60 < phy=70 < eth=enetc_psi0=80 < enetc_vsin=81
by executing at an early stage the NETC global initialization. This also
allows to match the DT hierarchy representation of NETC with the
effective priorities assigned.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-08-04 13:55:45 +00:00
Maciej Sobkowski
1d45065e8a soc: arm: ambiq: apollo4x: configure STIMER
Disable SysTick when STIMER is in use and configure
SYS_CLOCK_HW_CYCLES_PER_SEC setting for it.

Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
2023-08-04 10:48:58 +02:00
Maciej Sobkowski
8a670d0713 drivers: pinctrl: Add pinctrl driver for Apollo4
This commit addst pinctrl support for Apollo4 SoCs.

Co-authored-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
2023-08-04 10:48:58 +02:00
Maciej Sobkowski
0118886624 soc: arm: ambiq: apollo4: Add support for Apollo4 Plus SoC
Add all required parts (new SoC family/series, device tree) for
the Ambiq Apollo4 Plus SoC.

Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
2023-08-04 10:48:58 +02:00
Gerson Fernando Budke
ee15b1ff05 soc: atmel: same5x: Disable cache
The sam0 CMCC configure Cortex-M cache controller. However, it is not
clear how the cache management should be performed. It is nor clear if
instructions like SCB_EnableICache can be used. In this case, if cache
management should be made only by CMCC it may require a dedicated
implementation.

Besides above, the CPU_CORTEX_M4 do not define cache by default which
can signal a bad configuration in tree since the SOC_SERIES_SAME54 do
not define which caches should be available.

This force cache controller disable to avoid issues.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2023-08-04 10:46:03 +02:00
Gerson Fernando Budke
ea24dd40eb soc: atmel: sam: Fix cache management
The current platform initialization do not take in consideration cache
management for historic reasons. This fixes any miss configuration and
allow users to enable/disable caches at board definition. The default
value is cache disabled and the below examples are for SAMV71 which
have both I/D Cache available:

I Cache only:
CONFIG_CACHE_MANAGEMENT=y
CONFIG_DCACHE=n

D Cache only:
CONFIG_CACHE_MANAGEMENT=y
CONFIG_ICACHE=n

I/D Cache disabled:
CONFIG_ICACHE=n
CONFIG_DCACHE=n

I/D Cache Enabled:
CONFIG_CACHE_MANAGEMENT=y

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2023-08-04 10:46:03 +02:00
Gerson Fernando Budke
45ad244212 soc: atmel: Enable platform specific init
This replace pre kernel initialization by the platform specific
initialization call. The platform specific init will configure
at very beginning the clocks, flash wait states and cache.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2023-08-04 10:46:03 +02:00
Gerson Fernando Budke
5457c2d74e soc: arm: sam: Reorder copyright by year ascending
Adjust copyright order by ascending year order.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2023-08-04 10:46:03 +02:00
Gerson Fernando Budke
0847e85088 soc: arm: atmel: Normalize Kconfig.series files
This update Kconfig.series files to normalize copyright date order from
lower to higher and reorder select entries.

Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
2023-08-04 10:46:03 +02:00