In case of stm32h5 both LL_DBGMCU_EnableTraceClock() and
LL_DBGMCU_SetTracePinAssignment() need to be called in order to properly
configure SWO output.
Select HAS_SWO, so that logging over SWO can be enabled.
Tested with ST's fork of openocd [1].
[1] https://github.com/STMicroelectronics/OpenOCD
Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
Update iMX RT boot header to support CONFIG_XIP=n, when the image is not
linked into the flash space. Also, update the boot header to correctly
calculate the flash used size within the boot data header. This field is
used by the iMX boot ROM to determine how much data to copy when running
from RAM, so using the correct size fixes an issue where the ROM would
copy more data than needed.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The CMSIS module glue code was part of arch/ directory. Move it to
modules/cmsis, and provide a single entry point for it: cmsis_core.h.
This entry header will include the right CMSIS header (M or A/R).
To make this change possible, CMSIS module Kconfig/CMake are declared as
external, allowing us to add a new Zephyr include directory.
All files including CMSIS have been updated.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This CL introduces new Flash Interface Unit (FIU) hardware in npcx4
series. The different operations of npcx9 and npcx4 FIU include:
1. 4-byte mode support for DRA mode move to SPI_DEV reg
2. To access the second flash in DRA mode, we need to configure
SPI_DEV_SEL field in BURST_CFG additionally.
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
This CL introduces new clock architectures in npcx4 series and wraps
clock configurations of different series by device tree files.
For example, the PWDWN_CTLx reg initialization relies on `pwdwn-ctl-val`
prop of pcc DT node now.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This CL adds the soc drivers for npcx4 series. Besides adding npcx4m3f
and npcx4m8f support, we also modified the register offset of
LV_GPIO_CTL and PUPD_EN for npcx4 series.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The XEC clock control driver sample code uses enum indexes to offset to
the desired GPIO CTRL register of the package. These enums are only
used in this example code and are being removed in favor of calculated
indexing into the specific GPIO register memory map.
Signed-off-by: Jeff Daly <jeffd@silicom-usa.com>
Move arm_mpu_mem_cfg header to common include directory.
The benefits are two-fold:
- Allow for out of tree SoC definitions to use them to
define mpu_regions.
- Remove odd relative include path
Signed-off-by: Moritz Fischer <moritzf@google.com>
Reduce the main clock frequency from 150MHz to 144MHz which allows meeting
the full range of CAN bitrates.
Fixes: #60811
Signed-off-by: Henrik Brix Andersen <hebad@vestas.com>
Since bb590b5b6e, which enforces a more consistent ordering of
initialisation for devices, the ECIA initialisation was happening after
GPIO initialisation. This caused interrupts to stop working on GPIO
input.
This patch fixes that by increasing the default GPIO initialisation
priority, so that it happens after ECIA.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Since bb590b5b6e, which enforces a more consistent ordering of
initialisation for devices, the SOC initialisation was happening after
GPIO initialisation. This caused interrupts to stop working on GPIO
input.
This patch fixes that by increasing the default GPIO initialisation
priority, so that it happens after SOC.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
openamp shared memory regions can be anywhere in DDR memory
withing 2G range. Current SRAM_PRIV region is 64M which
prevents access of shared memory (vrings) by RPU (cortex-r5)
if it is out of 64M range. This patch allows vrings to be in DDR within
2G address space.
Developed-by: Dan Millea
Commited by: Tanmay Shah
Signed-off-by: Dan Milea <dan.milea@windriver.com>
Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
Configure ENET_REF_CLK direction as input when
CONFIG_ETH_MCUX_RMII_EXT_CLK is set to allow Ethernet external clock
usage.
Signed-off-by: Benjamin Lemouzy <blemouzy@centralp.fr>
SiLabs' sleeptimer driver supports several hardware peripherals, of
which the counter driver so far only supports the RTCC-based variant.
This patch adds support for the SYSRTC-based sleeptimer implementation,
which is required for Gecko SoCs that do not have an RTCC module.
Signed-off-by: Markus Fuchs <markus.fuchs@ch.sauter-bc.com>
nRF53/91 require usage of nrf_regulators_system_off, so the API is not
common with nRF51/52. This was an oversight during the conversion.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Adds support for the NXP VMU RT1170 board. This Vehicle
Management Unit based on the i.MX RT1176 brings a fantastic
combination of sensors and IO all on one board for development
of various systems. It is also the featured board for
CogniPilot's Cerebri - VMU autopilot software based on Zephyr.
Co-authored-by: Peter van der Perk <peter.vanderperk@nxp.com>
Signed-off-by: Benjamin Perseghetti <bperseghetti@rudislabs.com>
Remove CONFIG_OCRAM_NOCACHE setting, as this is now possible to achieve
using devicetree linker regions, and there is no point in having a
specific Kconfig for one memory region on the RT series like this.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Enable SOC fixed MPU regions by default for the RT10xx/RT11xx SOC lines.
Additionally, add code to handle defining the SDRAM0 region as
device type (non cacheable, non shareable). This behavior can
be disabled with CONFIG_NXP_IMX_EXTERNAL_SDRAM=y. Set this Kconfig
for all boards in tree using SDRAM.
This will resolve an issue present on the RT11xx series where
the core may execute speculative prefetches to the SDRAM region when
no SDRAM is present on the board, resulting in the system faulting.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Don't default CONFIG_DEVICE_CONFIGURATION_DATA to enabled for iMX RT
SOCs, as this configuration block is only used when the board needs
peripherals like the external memory controller setup from reset by the
bootrom.
Enable this feature on all in tree boards that will require it,
and document the change to the default value in release notes.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Nordic SoCs do all power management automagically when going to idle (ie
k_cpu_idle()). The only extra state, system off, is now handled via
sys_shutdown(), so there's no need to support the PM subsystem.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
So far the init priories were:
enetc_psi0=60 < enetc_vsin=61 < emdio=70 < ethernet-phy=80
because the Ethernet PSI driver was doing global initialization for the
whole NETC complex, including enabling MDIO function (due to the way
the HAL works).
Change to use the default init priorities:
mdio=60 < phy=70 < eth=enetc_psi0=80 < enetc_vsin=81
by executing at an early stage the NETC global initialization. This also
allows to match the DT hierarchy representation of NETC with the
effective priorities assigned.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Disable SysTick when STIMER is in use and configure
SYS_CLOCK_HW_CYCLES_PER_SEC setting for it.
Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
This commit addst pinctrl support for Apollo4 SoCs.
Co-authored-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Maciej Sobkowski <msobkowski@antmicro.com>
The sam0 CMCC configure Cortex-M cache controller. However, it is not
clear how the cache management should be performed. It is nor clear if
instructions like SCB_EnableICache can be used. In this case, if cache
management should be made only by CMCC it may require a dedicated
implementation.
Besides above, the CPU_CORTEX_M4 do not define cache by default which
can signal a bad configuration in tree since the SOC_SERIES_SAME54 do
not define which caches should be available.
This force cache controller disable to avoid issues.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
The current platform initialization do not take in consideration cache
management for historic reasons. This fixes any miss configuration and
allow users to enable/disable caches at board definition. The default
value is cache disabled and the below examples are for SAMV71 which
have both I/D Cache available:
I Cache only:
CONFIG_CACHE_MANAGEMENT=y
CONFIG_DCACHE=n
D Cache only:
CONFIG_CACHE_MANAGEMENT=y
CONFIG_ICACHE=n
I/D Cache disabled:
CONFIG_ICACHE=n
CONFIG_DCACHE=n
I/D Cache Enabled:
CONFIG_CACHE_MANAGEMENT=y
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This replace pre kernel initialization by the platform specific
initialization call. The platform specific init will configure
at very beginning the clocks, flash wait states and cache.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This update Kconfig.series files to normalize copyright date order from
lower to higher and reorder select entries.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Some configurations have the system timer driver hardwired in.
Let's make them compatible with CONFIG_SYS_CLOCK_EXISTS=n.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
This device has a single instance of EMAC (a 100Mbps version of GMAC).
TCP/UDP checksum calculation is offloaded.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Reuse existing NXP LPSPI binding for this SoC since the hardware block
for this device is the same as the one supported for other NXP devices.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Do not select CONFIG_CACHE_MANAGEMENT in the Microchip SAM CAN driver
Kconfig but rather leave it up to the SoC/platform Kconfig to enable it as
needed and enable CACHE_MANAGEMENT by default for the Atmel SAM E70/V71 SoC
series.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Currently on zephyr, RAIL is used only for bluetooth. RAIL library is
needed to use efr32 radio regardless of the protocol used. We add
SOC_GECKO_USE_RAIL kconfig option to indicate if we use radio.
FPU is needed when using RAIL, we configure it if SOC_GECKO_USE_RAIL
is set.
Signed-off-by: Antoine Bout <antoine.bout@silabs.com>
Update to shim driver compatible with the hardware block
in S32K344. Configure the pins before initializing I2C
to avoid happening bus busy.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Reuse existing MCUX-based shim driver for FlexCAN.
Enable flexcan0 for Zephyr canbus to run tests.
Signed-off-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Adds driver for pwm on xmc4xxx using Capture Compare Unit 8 (CCU8)
module. There are two CCU8 nodes with each one having four slices.
Each slice has two output channels.
Unlike CCU4, this module can generate complementary high-side/low-side
signals for each output channel. A variable dead time can be added
during the off to on transitions to make sure that the
high-side/low-side signals are not on at the same time.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Adds driver for pwm on xmc4xxx using Capture Compare Unit 4 (CCU4)
module. There are four CCU4 with each one having four channels
Thus it's possible to have up to 16 pwm output signals. The output of
each channel can only be connected to a specific port/pin. The possible
connection and gpio configurations are defined using pinctrl.
The CCU4 module also has a capture mode. Capture support will be added
in the future.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Pinmuxing is now done by a pinctrl driver, not by board.c,
so the code used previously for pinmuxing can be removed.
Fixes#59186.
Signed-off-by: Wojciech Sipak <wsipak@antmicro.com>
Introduces support for SoC-specific input-edge-detect configuration to
the CC13/26xx pinctrl driver.
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
CC13/26xx's pinctrl_cc13xx_cc26xx.c driver included ioc.h and
(indirectly) pinctrl_soc.h which contained duplicate defines.
This change removes the header conflict and redundant definitions.
This prepares for subsequent changes in this change set that add
additional flags to the pinctrl driver which would otherwise trigger the
header conflict.
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
- use CONFIG_HAS_HW_NRF_* symbols consistently in nRF multi-instance
drivers when creating particular driver instances
- remove unnecessary hidden Kconfig options that indicated the type of
peripheral to be used by a given instance (e.g. SPI, SPIM, or SPIS)
and enabled proper nrfx driver instance; instead, use one option per
peripheral type and include the corresponding shim driver flavor into
compilation basing on that option (not the one that enables the nrfx
driver as it was incorrectly done so far in some cases)
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Some EFR32 build broke after 3d2194f11e with:
pm.c:152: undefined reference to `pm_state_exit_post_ops'
Add an extra empty function to make this one build again.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Added dts additions for stm32f105xb cpu which is the same as existing
stm32f105xc with less flash.
Signed-off-by: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
This CL attempts to implement npcx's flash driver instead of the
original one (npcx spi driver plus spi_nor flash driver).
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Add a new pinctrl type to control peripheral modules' specific IO
characteristics such as tri-state, the power supply type selection (3.3V
or 1.8V), and so on. In NPCX series, the corresponding registers/fields
are irregular. This CL wraps these definitions to dt nodes and put them
in pinctrl property if needed.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Remove unnecessary __weak attribute from power management functions.
These functions are now defined once, globally, and mandatory for
systems that support CONFIG_PM.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Add a new Kconfig option that has to be selected by SoCs providing PM
hooks. This option will be now required to enable CONFIG_PM. Before this
change, CONFIG_PM could always be enabled, regardless of SoC providing
any kind of low-power support.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Updated the clock init to reflect the sdk also
updated the clock frequencies to reflect the
respective soc clock values, this file originally
contained unexpected clock values, updated comments
to reflect changes and got rid of doxygen style
comments
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
- This includes the driver, test app, and sample app
- Only the boards\arm\xmc47_relax_kit board is supported for now
Signed-off-by: Bill Waters <bill.waters@infineon.com>
Removes duplicate code and inconsistencies in the naming of the
cc13xx_cc26xx devicetree and RTC driver hierarchy and alignes it with
the actual TI product series naming hierarchy.
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
On nRF5340 net core it was observed that when `wfi` instruction was
followed by `pop {r0, lr}` in the `arch_cpu_idle` function,
the value of `lr` sometimes got read as 0 from memory despite
having correct value stored in the memory.
This commit inserts additional `nop` instruction after waking up
to delay access to the memory.
Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
Reuse existing MCUX-based shim driver for LPUART that is compatible with
the hardware block in S32K344. DMA is not yet supported.
Use the board's debug connector (P6 / LPUART2) as default console.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Unify the pinctrl_soc.h header for all the NXP S32 family by using
the HAL macros that expose the features supported on specific
devices. This approach still need a different binding for each device to
expose in DT different properties and allowed values.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Introduce minimal power initialization for NXP S32 SoCs and allow to
reset the SoC through the sys_reboot() API.
Presently only S32K3 SoCs is supported but it can be extended later to
other NXP S32 SoCs, hence it's placed in a common directory.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
The S32K3 MCUs are 32-bit Arm Cortex-M7-based microcontrollers with a
focus on automotive and industrial applications. The S32K344 features
a lock-step core, internal flash, RAM and TCM with ECC.
Co-authored-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Co-authored-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
NMI_INIT() is now a no-op, so remove it from all SoC code. Also remove
the irq lock/unlock pattern as it was likely a cause of copy&paste when
NMI_INIT() was called.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
This patch sets ENET2 ref clock to be generated by External OSC
ENET2 ref clock direction as output
ENET2 ref clk frequency to 50MHz
Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
A known issue exists that does not allow a CC13/26x2R device to
establish a link to a CC13/26x2P device unless the capacitor array is
tuned to a non-default value in the P device.
See SimpleLink(TM) cc13xx_cc26xx SDK 6.20+ Release Notes, Known Issues.
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
All Cortex-M processors can support RTT by default. This change enables
RTT support for the cc13xx/cc26xx SoC series (tested in hardware on
CC1352R).
Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
Add Nuvoton numaker series clock controller support, including:
1. Do system clock initialization in z_arm_platform_init().
2. Support peripheral clock control API equivalent to BSP
CLK_EnableModuleClock()/CLK_SetModuleClock().
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
Add a new pinctrl driver for TI CC32XX SoC. The driver has not been
tested, just implemented following datasheet specs and checked that it
compiles. Consider this as a best-effort driver to remove custom pinmux
code in board files.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Disable RT boot header for CM4 core. This will ensure the boot header is
not present when building an application targeting RAM on the CM4.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The Nordic board are selecting CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT by
default and rely on some HAL code to implement a cycle accurate busy
delay loop.
This is in general fine for real hardware but when QEMU and emulation is
taken into account, a cycle accurate busy wait implementation based on
delay in executing machine code can be misleading.
Let's take for example qemu_cortex_m0 (that is based on the nRF51
chipset) and this code:
uint32_t before, after;
while (1) {
before = k_cycle_get_32();
k_busy_wait(1000 * 1000);
after = k_cycle_get_32();
printk("diff cycles: %d\n", after - before);
}
With CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1000000 this diff cycles should
be always around 1000000, in reality when executed with:
qemu-system-arm -cpu cortex-m0 -machine microbit -nographic
-kernel build/zephyr/zephyr.elf
This results in something like this:
diff cycles: 22285
diff cycles: 24339
diff cycles: 21483
diff cycles: 21063
diff cycles: 21116
diff cycles: 19633
This is possibly due to the fact that the cycle accurate delay busy loop
is too fast in emulation.
When dealing with QEMU let's use the reliable busy loop implementation
based on k_cycle_get_32() instead.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
1. Add support for the USB Full Speed controller
2. Add a Kconfig to specify if a dedicated USB
RAM is available in the SoC.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Add FLEXSPI1 and FLEXSPI2 memory sections for RT5xx SOC. These sections
can be used by the user's application as part of a custom linker script,
if the application needs to relocate a buffer to external SRAM connected
to FLEXSPI1 or FLEXSPI2
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This commits selects the `CONFIG_SOC_GECKO_SE` option for the BG27 SoC
series. This is required for BLE support, as it enables the inclusion of
the `sl_protocol_crypto` component from SiLabs HAL.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Internal bootloader will only run application image if valid product
header is present on flash. This means product header is required for
application that are not linked to code partition. Other applications
that are linked to code partition are meant to be run by MCUboot and
should not touch product header, with the exception of MCUboot itself
which is also run by internal bootloader so requires product header.
Default flash load offset for applications not linked to code partition
is set to 0x2400 as this is where internal bootloader looks for an
application image to run based on product header written by flasher.
Flash load offset for MCUboot is set from boot partition.
Valid product header is added by ezFlashCLI when using "flash_image"
command.
Co-authored-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Niek Ilmer <niek.ilmer.aj@renesas.com>
Applications that are run from MCUboot should reconfigure cache to
ensure they run from cached ared on flash. Initial cache configuration
is done by internal bootloader and is valid for MCUboot only.
Cache is configured once at boot, then new configuration is applied by
triggering SW reset.
Co-authored-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Niek Ilmer <niek.ilmer.aj@renesas.com>
Flash address is updated to 0x16000000, i.e. actual location instead of
remapped one. FLASH_BASE_ADDRESS is now set via dts.
Co-authored-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Niek Ilmer <niek.ilmer.aj@renesas.com>
sl_power_manager can only be used if HAL services infrastructure
is enabled, and that is controlled by SOC_GECKO_DEV_INIT kconfig option.
Therefore, SOC_GECKO_PM_BACKEND_PMGR may not be enabled without
SOC_GECKO_DEV_INIT.
Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
Using EM2 or deeper sleep states (where HF clocks are off) requires
special care if BLE radio is used, since BLE radio relies on that clock,
and its power/clock requirements need to be taken into account
On SiLabs, radio PM is implemented as part of RAIL blob, which relies
on sl_power_manager HAL service. I've implemented SoC PM
state changes using sl_power_manager instead of emlib, and added
call to RAIL PM initialization in Gecko HCI driver.
Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
Driver was based on can_sam. SAMC21 has only 1 interrupt for one
can "output", so can interrupt has to executes two lines of
interrupts.
CAN is configured to use OSC48M clock via GLCK7. GLCK7 is set
by divider configured from dts.
Signed-off-by: Kamil Serwus <kserwus@gmail.com>
This patch enables the PLL clock output and PLL ref clock
for second ethernet module in NXP's i.MxRT106x SoCs
Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
To reduce the interrupt latency of MIWU events, the driver prepares a
dedicated callback function item list for each MIWU group in this PR. We
needn't check the MIWU table and group of the event in ISR. And the
maximum item number of each list is also limited to 8. After applying
this PR, the interrupt latency reduces to ~10us consistently.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Glitches were observed if a GPIO pin was configured by
ROM to a non-default state and then Zephyr PINCTRL
reconfigured the pin. The fix involves using the correct
PINCTRL YAML output enable and state flags. Reading the
current spin state and reflecting into new pin configuration
if the pin is output and the drive low/high properties are
not present. We also take advantage of GPIO hardware reflecing
the alternate output value in the parallel output bit before
enabling parallel output mode. Interpret boolean flags with
both enable and disable as do not touch if neither flag is
present. We give precedence to enable over disable if both
flags mistakenly appear. Note, PINCTRL always clears the
GPIO control input pad disable bit.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
1. Enable os_timer as a wakeup-source in the board
dts file.
2. Enable PM_DEVICE when PM is enabled.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Added logging declaration to soc.c of stm32wl, which resolves build
errors when using this SOC with DEBUG logging level
Fixes: #57655
Signed-off-by: Oliver King <oliver.king@steadconnect.com>
board:
- update device tree to use flexcomm devices to the chip design
- enable clocks (soc init file)
- setup connections for loopback test in system controller (board init
file)
tests:
- update board files (overlay, conf)
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
Update MCUX ELCDIF driver to use new LCDIF bindings. This
update also adds support for configuring the root clock of
the ELCDIF module based on the pixel-clock property to the
RT11xx SOC clock init, as this SOC series has this IP block
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Update DCNANO LCDIF IP to use shared lcd interface binding. This
requires changes to the RT5xx SOC and RT595 EVK, as this SOC
uses the LCDIF IP, and configures the clock for it based off
the new pixel-clock property.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce phy-clock property, which is used by MIPI devices to determine
the target clock frequency for the MIPI PHY. This property can vary
depending on the attached display and target framerate.
Update the MIPI DSI MCUX driver to utilize this property to configure
the MIPI host, and update the RT500 clock initialization to configure
the MIPI root clock based on this property.
Remove dphy-clk-div property from the MIPI DSI 2L binding, as it
is redundant with this change.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Improve the radio off code, mainly:
- Compile the file only if necessary, ie, LORA radio not in use
- Use pin information from DT, so that we do not need to hardcode pins
and can switch to dt-spec APIs.
- Improve error handling, includes, etc.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Although existing nRF SoCs have only one I2S instance, the nrfx_i2s
driver has now multi-instance API and the related nrfx configuration
symbols need to be used appropriately.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Ensure code cache is enabled at boot for RT11xx. CMSIS SystemInit should
enable the code cache, but if CONFIG_INIT_ARCH_HW_AT_BOOT=y and
CONFIG_CACHE_MANAGEMENT=y, then the cache will be disabled after
SystemInit is called. Since calling SCB_EnableICache will not
change hardware settings if the ICACHE is already enabled, just
call it unconditionally during init.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add Silicon Labs xG24-PK6010A (BRD4187C radio plug-in board)
support to the efr32_radio board.
Signed-off-by: Markus Fuchs <markus.fuchs@ch.sauter-bc.com>
For certain combinations of configuration parameters,
z_arm_init_arch_hw_at_boot() disables the instruction cache. Make sure
to re-enable it if required.
Signed-off-by: Jan Peters <peters@kt-elektronik.de>
Clearing of shared memory by one side of the communication
is no longer required after
commit 0620cb1fe1
("ipc: ipc_service: icmsg: Increase reliability of bonding")
was merged.
Signed-off-by: Emil Obalski <Emil.Obalski@nordicsemi.no>
To be consistent with the current NXP clocking scheme,
move the LPADC clocking code to the SOC files where
all of the other peripheral clocking is done.
Also remove any other SOC-specific code to the
respective SOC file and out of this driver.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
It is enabled by default if Device Tree includes a flash controller,
and disabled otherwise. SoC defconfig should not touch it.
Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
The mps3 soc is missing PMU defines required for CMSIS. This
adds the defines __PMU_PRESENT and __PMU_NUM_EVENTCNT
enabling the api for the PMU.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Move STM32H7_DUAL_CORE to
soc/arm/st_stm32/stm32h7/Kconfig.soc
add select STM32H7_DUAL_CORE for SOC_STM32H745XX/H747XX
Cleanup old occurences where was set to y
Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
This new Kconfig option lets the developer configure if the Cortex M4
core should be force-booted during M7 init independent of the BCM4
option byte.
This allows to disable this default behaviour via Kconfig which was not
possible so far.
Signed-off-by: Jan Krautmacher <jan@krautmacher.org>
Deprecates setting GPREGRET to the reset reason as this has been
replaced with the boot mode retention subsystem for nRF51/nRF52.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This commit adds the Gecko IADC driver and support for it to the
efr32bg_sltb010a board.
Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
Secure Element's mailbox is needed for entropy gathering purposes.
Enable it in the EFR32MG24 SoC series Kconfig.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
- Add Gecko BURTC sys_clock driver to handle wake up from EM2,3 states
- Remove custom PM policy and dependency on HAL sl_power_manager service
- EM1 supported in all configurations
- EM2,3 supported only if SysTick is replaced by BURTC
Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
This commit adds the SiLabs Bluetooth HCI driver. It also enables this
BLE HCI driver on the efr32bg_sltb010a board.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
HAL API changes in ethernet and pwm
SoC RT595 power management code change
west.yml update
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
This prevents configuration errors if a board is configured when
the SoC indicates segger RTT support but the segger module is
not available.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This adds the SPI driver for the Renesas SmartBond(tm) DA1469x MCU family.
The driver only supports controller mode. All four SPI modes are supported.
Note that the lowest supported speed is 2285714Hz.
Requesting speeds higher than 16MHz, will result in a 16MHz SCLK.
Co-authored-by: Stan Geitel <stan@geitel.nl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
This commit adds a missing `__weak` symbol to the `pm_policy_next_state`
function.
This is needed for e.g. `tests/kernel/profiling/profiling_api` to build
correctly.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
The nRF9161 is technically a SiP (System-in-Package) that consists of
the nRF9120 SoC and additional components like PMIC, FEM, and XTAL,
so for nrfx/MDK the nRF9120 SoC is to be selected as the build target,
but since the nRF9161 is what a user can actually see on a board, using
only nRF9120 in the Zephyr build infrastructure might be confusing.
That's why in the top level of SoC definitions (for user-configurable
options in Kconfig, for example) the nRF9161 term is used and nRF9120
underneath.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Use one common `if SOC_SERIES_NRF52X` instead of `depends on` for
each particular SoC option.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This is a follow-up to commit 4be102f8e05a9fa12290d8209a8cb38569265478.
Inclusion of `<system_nrf*.>` from `soc.c` files is no longer needed
since `SystemInit()` is not called from those files.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This adds USB-HS support for LPC55S16, much in the same way that
LPC55S28 support was added previously.
Signed-off-by: Maxime Vincent <maxime@veemax.be>
Many areas of Zephyr divide and round up without using the DIV_ROUND_UP
macro. Make use of it, so that we make use of a tested system macro and
at the same time we make code more readable.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The init infrastructure, found in `init.h`, is currently used by:
- `SYS_INIT`: to call functions before `main`
- `DEVICE_*`: to initialize devices
They are all sorted according to an initialization level + a priority.
`SYS_INIT` calls are really orthogonal to devices, however, the required
function signature requires a `const struct device *dev` as a first
argument. The only reason for that is because the same init machinery is
used by devices, so we have something like:
```c
struct init_entry {
int (*init)(const struct device *dev);
/* only set by DEVICE_*, otherwise NULL */
const struct device *dev;
}
```
As a result, we end up with such weird/ugly pattern:
```c
static int my_init(const struct device *dev)
{
/* always NULL! add ARG_UNUSED to avoid compiler warning */
ARG_UNUSED(dev);
...
}
```
This is really a result of poor internals isolation. This patch proposes
a to make init entries more flexible so that they can accept sytem
initialization calls like this:
```c
static int my_init(void)
{
...
}
```
This is achieved using a union:
```c
union init_function {
/* for SYS_INIT, used when init_entry.dev == NULL */
int (*sys)(void);
/* for DEVICE*, used when init_entry.dev != NULL */
int (*dev)(const struct device *dev);
};
struct init_entry {
/* stores init function (either for SYS_INIT or DEVICE*)
union init_function init_fn;
/* stores device pointer for DEVICE*, NULL for SYS_INIT. Allows
* to know which union entry to call.
*/
const struct device *dev;
}
```
This solution **does not increase ROM usage**, and allows to offer clean
public APIs for both SYS_INIT and DEVICE*. Note that however, init
machinery keeps a coupling with devices.
**NOTE**: This is a breaking change! All `SYS_INIT` functions will need
to be converted to the new signature. See the script offered in the
following commit.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
init: convert SYS_INIT functions to the new signature
Conversion scripted using scripts/utils/migrate_sys_init.py.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
manifest: update projects for SYS_INIT changes
Update modules with updated SYS_INIT calls:
- hal_ti
- lvgl
- sof
- TraceRecorderSource
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
tests: devicetree: devices: adjust test
Adjust test according to the recently introduced SYS_INIT
infrastructure.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
tests: kernel: threads: adjust SYS_INIT call
Adjust to the new signature: int (*init_fn)(void);
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Remove per soc definitions that are already defined in the exact same
way in include/zephyr/arch/arm/aarch32/nmi.h.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Remove per soc definitions that are already defined in the exact same
way in include/zephyr/arch/arm/aarch32/nmi.h.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Initialization part of this anomaly is now handled internally
by the startup code provided by the MDK.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
Zephyr PM expects the SoC layer upon wake to unmask interrupts
the PM layer masked. MEC172x was re-enabling interrupt globally
in the Cortex-M4 but not clearing the mask set by Zephyr PM.
This worked in previous Zephyr releases but broke in the latest
Zephyr changes. Fixed the SoC to re-enable interrupts globally
and call irq_unlock(0) as Zephyr PM does if pm_state_exit_post_ops
is not implemented. Tested on MEC172x EVB with PLL clock out pin
enabled and verified PLL goes off in deep sleep, system wakes,
and interrupts are firing.
Signed-off-by: scott worley <scott.worley@microchip.com>
This commit introduces power management support for EFR32BG SoCs.
Tested on the efr32bg_sltb010a board.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
There are some issues with the current version of the code, mainly the
improper use of the internal OSC8M as a source for the DFLL48m without
division. The DFLL48M is designed to accept a maximum of ~33KHz
at it's input, as higher values will bring the multiplier down,
leading to instability.
Also added the following features:
* Support for external HF oscillator (XOSC)
* Support for crystal/external oscillators on XOSC32K/XOSC
* Automatic dividers/multiplier computation based on DT cpu frequency
* Support for user configurable NVM wait states
* Added option to skip clock (re)initialization (bootloader usecase).
Tests were performed on a custom SAMD20G18 board using different clock
sources and cpu frequencies.
Clocks were routed to GPIO pins and observed on a scope.
According to the datasheet, architecture is identical on D21/R21.
Due to the nature of the internal architecture and the fact that
DFLL48M is not really meant to output anything other than 48MHZ
some combinations of requested DT cpu frequency and source
frequency will not result in a perfect match.
Mostly insipred by the SAML21 implementation.
Signed-off-by: Ionut Catalin Pavel <iocapa@iocapa.com>
1. Move the GPIO mux setting to the soc layer. The GPIO MUX
value may vary based on the SoC Family
2. Enable the digital input buffer if available
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Add configuration items to select various ARM debug options
such as SWD only, SWD plus SWV, or SWD plus ETM. The default
is SWD only.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Enable at SoC boot time when enabled through Kconfig. Cache management
API is not used since it could be built without its support enabled.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
When CONFIG_NOCACHE_MEMORY=y, the .nocache section is placed in between
__rodata_region_end and _app_smem_start/__kernel_ram_start. Make sure
this region is covered by the MPU background region so that the static
region for nocache is configured correctly.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Introduce the new stm32h5 soc serie from STMIcroelectronics.
Note that stm32h503x do not have TrustZone nor SAU
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Remove the manually created linker section, because it's already
automatically generated for all sram regions in the DTS with the
"zephyr,memory-region" compatibility.
Signed-off-by: Hein Wessels <heinwessels93@gmail.com>
Change device tree VW routing to a form allowing overrides.
Add two new DT optional properties for specifying the reset
source and reset value of each virtual wire. Only virtual
wires that are enabled using the status property are modified.
NOTE: eSPI virtual wires are controlled in groups of 4 by
hardware. The optional reset signal source properties applies
to all four virtual wires in the group. If this field is
changed from the hardware default, it should be changed for
only one virtual wire in the group. If the property exists
in more than one wire in the group it must be set to the
same value.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Modify Mircrochip MEC172x eSPI driver to get eSPI virtual wire
hardware routing from device tree.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
The clock control driver requires three pieces of information:
PCR register index, bit position, and clock domain. Clock domain
was missing from DT information and MCHP macros.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Some pico-sdk drivers call a panic function, originally implemented
as part of the Pico's C runtime. This commit adds a Zephyr compatible
implementation of panic, so that those drivers could be compiled with
Zephyr.
Signed-off-by: Yonatan Schachter <yonatan.schachter@gmail.com>
Add initial version of clock control for Atmel SAM SoC series. This add
support to Power Management which allows control peripherals clock.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Product URL: https://www.ti.com/product/CC1352P7
Datasheet : https://www.ti.com/lit/ds/symlink/cc1352p7.pdf
Features:
Powerful 48-MHz Arm® Cortex®-M4F processor
* 704KB flash program memory
* 256KB of ROM for protocols and library functions
* 8KB of cache SRAM
* 144KB of ultra-low leakage SRAM with parity for
high-reliability operation
* Dual-band Sub-1 GHz and 2.4 GHz operation
Updates:
* Remove CC1352P7_LaunchXL due to compliance checks
* Add CC1352P7 updates
* Update hal_ti for CC1352P7 support
* Remove blank line at end of modules/Kconfig.simplelink
* Split struct and typedef for pinctrl_soc_pin/pinctrl_soc_pin_t
* Reference cc13x2_cc26x2/pinctrl_soc.h
* Reference cc13x2_cc26x2/soc.h
Signed-off-by: Vaishnav Achath <vaishnav@beagleboard.org>
In general, RTC and TIMER driver implements counter API but there
are exception when those peripherals are used in a custom way
(e.g. for system timer or bluetooth). In that case, system must
prevent using counter based on a reserved instance. Previously,
it was managed by Kconfig options but that cannot be maintained
when switching to devicetree configuration of the counter driver.
A new approach removes Kconfig options and instead adds static
asserts in the files which are using direct peripherals. Those
asserts check if given node is not enabled in the device tree.
Signed-off-by: Krzysztof Chruscinski <krzysztof.chruscinski@nordicsemi.no>
Removed the EEPROM and ESPI configuration from file
Kconfig.defconfig.mec172xnsz. Since it overrides the
setting present in the Device Tree file.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Use Device Tree bindings to configure clock source/frequency for enabled
UARTs only.
Get rid of UART clock ungating from `soc.c`, as that functionality has
been moved to the clock controller.
Signed-off-by: Artur Rojek <artur@conclusive.pl>
Add functionality for changing the code location
based on the flash chosen node for RT devices.
Remove obsolete Kconfigs that used to be used
to set the code location for RT devices.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Allow selecting between direct SMPS and LDO on the startup. This
enables selecting to use SMPS regulators which can save bit of power.
Signed-off-by: Miika Karanki <miika.karanki@vaisala.com>
The STM32H730 series has a variant built with SMPS. It uses
`stm32h730xxq.h` header file instead of `stm32h730xx.h`, which has the
SMPS macro defined.
This commit adds the `SOC_STM32H730XXQ` configuration option to allow
the build system include the proper header file. With this change,
boards can enable `CONFIG_POWER_SUPPLY_DIRECT_SMPS` to set up the power
supply for the CPU.
Signed-off-by: Chen Xingyu <hi@xingrz.me>
Add clock initialization for MIPI and LCIDF to NXP RT5xx SOC.
Note that clock divider properties are used by both initialization
routines, as the required clock divider will vary depending on
attached display.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
This is a follow-up to commit 7195db01f4.
Restore the check that was accidentaliy removed in the above commit,
so that the message is again logged only once per detection of the
anomaly 160 conditions.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This is a follow-up to commit fe3b97a87f.
This message should not be a warning, as it does not actually indicate
that something potentially bad happened. On the contrary, it informs
that conditions in which the anomaly 160 could occur were detected and
the anomaly was prevented from occurring. There is no need for this
message to appear in the default configuration (INFO level). In fact,
the message would undesirably flood the console in some cases (like
the kernel/mem_protect/stack_random test) and sometimes it would also
require enlarging the stack of the idle thread (the function is called
underneath k_cpu_idle()). Therefore, the logging level of this message
is changed to DEBUG.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Added initial version of Infineon CAT1 Pin controller driver.
Added initial version of binding file for Infineon CAT1 Pinctrl driver.
Added initial version of dt header for Infineon CAT1 pinctrl driver.
Signed-off-by: Nazar Palamar <nazar.palamar@infineon.com>
Since PINCTRL and pinctrl-0 is now required, there's no point in doing
extra validation at driver level. Modify the macro to just check that
sleep state is present when needed, since it was the only remaining
assertion that was not covered. Renamed the macro to make it more clear
what it does: NRF_DT_CHECK_NODE_HAS_PINCTRL_SLEEP
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Drop the non existing option PINMUX_XEC, this has been removed in
d76f4f2c8a drivers: pinmux: mchp_xec: drop driver
And is currently causing build errors.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Add the stm32U5 serie for the support of the STM32_BACKUP_SRAM
The PWR peripheral is enabled by the soc/arm/st_stm32/stm32u5/soc.c
Signed-off-by: Francois Ramu <francois.ramu@st.com>
This is a follow-up to commit fe3b97a87f.
Add a cmake warning issued when the workaround for the nRF5340 anomaly
160 cannot be applied because the application is configured with no
system clock.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Drop STM32 pinmux driver in favor of pinctrl. Some definitions located
in pinmux headers were used by the pinctrl driver, so they have been
moved there.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Cleanup core if booting from bootloader using RT5xx. This is required
because the call to SystemInit will push data to the stack, and the
bootloader may have configured stack limits or MPU settings. Either
would cause the core to fault if these settings are not first
cleaned up.
Perform this cleanup if the boot header is not present, as in this case
the application was likely kicked off via a bootloader.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Allow to include boot header for code linked into
not only FlexSPI controlled memory.
Fixes#53867
Signed-off-by: Mikhail Siomin <victorovich.01@mail.ru>
Implement a workaround for the nRF53 anomaly 160. This consist of
a set of writes to certain hardware registers that is done at boot
and a piece of code that is executed when the CPU is made idle and
that prevents the CPU from switching between active and sleep modes
more than five times within a 200 us period.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Use CMSIS SystemInit for all NXP iMX.RT SOCs, to simplify initialization
flow, and remove redundant code where possible.
Introduce Kconfigs to disable Cache at boot, since SystemInit will enable
code cache on these platforms, which may be undesirable behavior.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Convert NXP LPC SOCs to use CMSIS SystemInit, and remove redundant code
where it exists. This will enable initialization flows to be more
standardized across all platforms.
Since LPC54xxx and LPC55xxx series enables SRAM banks in SystemInit,
provide Kconfigs to bypass this setting and keep additional SRAM
banks unclocked.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add call to SystemInit for all NXP Kinetis SOCs and remove any
redundant code from initialization flow. This allows watchdog
initialization to be removed from all Kinetis SOCs as it is handled
by SystemInit.
Since Kinetis watchdog is enabled by default at boot, allow watchdog
setup to by bypassed with CONFIG_WDOG_ENABLE_AT_BOOT. This
setting requires the user to provide a watchdog configuration hook
using z_arm_watchdog_init, but will allow the watchdog to remain
enabled.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
update the endpint in dts to 6 to alignd with RM
enable usb-device for LPC55S28
all USB supported tests/samples PASS
samples:
scripts/twister -p lpcxpresso55s28 \
--device-testing --hardware-map ~/map.yml \
-T samples/subsys/usb/
...
INFO - 7 of 25 test configurations passed (100.00%),\
0 failed, 18 skipped with 0 warnings in 73.49 seconds
...
tests
scripts/twister -p lpcxpresso55s28 \
--device-testing --hardware-map ~/map.yml \
-T tests/subsys/usb/
...
INFO - 3 of 4 test configurations passed (100.00%),\
0 failed, 1 skipped with 0 warnings in 36.39 seconds
...
Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
Allow the the SoC to enter deep sleep when CONFIG_PM_DEVICE
is enabled. This will allow to selectively add low power
support for certain drivers like UART and ADC.
The previous checking of ifndef CONFIG_PM_DEVICE was
incorrect. The MEC172x requires the soc power file to perform
some operations when CONFIG_PM_DEVICE is enabled to allow
the hardware to shut down the PLL.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
PR #30403 implemented nocache regions for ethernet DMA buffers in sram3 to
fix issue #29915. Unfortunately, some STM32H7 variants do not have any
sram3 so they still suffer from #29915.
All H7 variants have sram2 though, so use that for targets without sram3.
Signed-off-by: Björn Stenberg <bjorn@haxx.se>
When running the blinky example on STM32H747, with the BOOT_CM4 bit set
to 0, the M4 core goes into panic.
Increasing the value of the hardware semaphore retry prevents this.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
This patch allows successive reflashing operation on stm32f3
boards by Enabling the Debug Module during SLEEP mode.
This will especially makes reflahing and debugging possible
with pyocd runner on west commands.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
On some STM32 MCUs SEGGER RTT is only working with realtime updates
when DMA is clocked. The STM32U5 series uses a new DMA controller
module called GPDMA.
Refs: #34324Fixes: #54316
Signed-off-by: Almin Iriskic <almin.iriskic@student.tugraz.at>
Add SOC_CC1352P and SOC_CC2652P chip types to SoC's Kconfig
(with integrated high power amplifiers).
Also requires modifications to HAL TI's family conditions.
Signed-off-by: Stancu Florin <niflostancu@gmail.com>
New KConfig option to set `CCFG_FORCE_VDDR_HH` inside CC13xx/CC26xx
customer configuration file, making it it possible to use 14dBm
TX power (instead of the default 13 dBm limitation).
Signed-off-by: Stancu Florin <niflostancu@gmail.com>
Disables allowing the python argparse library from automatically
shortening command line arguments, this prevents issues whereby
a new command is added and code that wrongly uses the shortened
command of an existing argument which is the same as the new
command being added will silently change script behaviour.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
The nRF HW models have been updated to correspond to a 52833 instead
of a 52832. Let's follow them.
The motivation for the change is to enable proper BIS encryption support
(for BT LE Audio ISO).
Changes:
* Point in manifest to latest HW models
* SOC_COMPATIBLE_NRF52832 has been removed, and SOC_COMPATIBLE_NRF52833
added in its place (with no uses at this point)
* Where SOC_COMPATIBLE_NRF52832 was used to set encryption like for a 52832
(to avoid using the MAXPACKETLENGHT), we set the condition to just
SOC_NRF52832.
Note: The MAXPACKETLENGHT register exists in the new simulated nrf52833,
thought it does nothing.
* In the BLE ctrl LLL radio HAL, all macros are renamed accordingly
(timings are NOT changed).
* Board dts definition now refers to the 52833 soc definition. New 52833
features set as not supported by now.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add three xbar nodes and four qdec nodes in the rt10xx devicetree include.
Add xbara to rt1052 in Kconfig.soc
Signed-off-by: Jeppe Odgaard <jeppe.odgaard@prevas.dk>
Introduce DT nodes for NETC complex and enable its usage for
s32z270dc2_r52 boards. Using PSI0 as default networking interface and
Switch Port0 as it's the only port available on this board.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
This commit modifies the defconfig for efr32bg22 SoC so that Gecko SPI
selection depends on the DT_HAS_*_ENABLED define.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Update usage of zephyr_code_relocate to follow new API. The old method
of relocating a file was the following directive:
zephyr_code_relocate(file location)
The new API for zephyr_code_relocate uses the following directive:
zephyr_code_relocate(FILES file LOCATION location)
update in tree usage to follow this model. Also, update the NXP HAL SHA,
as NXP's HAL uses this macro as well.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The names of these peripherals in the device tree
did not match the Reference Manual for the RT500.
Also fixed a typo in a comment referring to USDHC which should have been
about USB.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
- Adds the pin controls and ushdc settings in device tree
- Attaches clock to USDHC in soc.c
- Adds binding for mmc
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The value in this bitfield is provided in the two's complement form,
so it requires special handling. Previously, it was read as just an
unsigned value and this could result in a wrongly computed CAPVALUE.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
For NPCX SMB/I2C SMB modules in FIFO mode, the registers include:
* Common registers, offset 0x00-0x0f, accessible regardless of the value
of BNK_SEL
* Bank 0 registers, offset 0x10-0x1e, accessible if BNK_SEL is set to 0
* Bank 1 registers, offset 0x10-0x1e, accessible if BNK_SEL
is set to 1
In the current driver, it uses two structures, `smb_reg` and
`smb_fifo_reg`, to access `Common + Bank 0` and `Common + Bank 1`
registers. But It might be easy to misunderstand that they are two
different modules.
This CL tries to simplify this by the following steps:
1. Use `union` to combine `Bank 0/1` registers in the same structure.
2. Remove `smb_fifo_reg`. We needn't use two structures to present
SMB registers.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
This commit adds the support for host commands being transported
by the Serial Host Interface on the NPCX SoC.
Signed-off-by: Michał Barnaś <mb@semihalf.com>
1. Support Sleep, Deep Sleep and Deep Power down modes
2. Enable the MEMC FlexSPI driver when using device power
management so we can reconfigure the FlexSPI pins to
save power. The MEMC FlexSPI driver is enabled when we
enable the Flash subsystem, however we would like to
reconfigure the FlexSPI pins even when the Flash driver
is disabled, hence MEMC is selected when PM_DEVICE
is turned on.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Following updates previously done for other drivers, rename all
occurrences of S32 to NXP S32 to avoid ambiguity.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Add support for configuring FlexSPI1 clock speed to RT5xx soc
initialization, so that memory present on FlexSPI1 can be accessed.
Note that FlexSPI1 is referred to as FlexSPI2 in the dts files for this
SOC.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Remove the test clock out Kconfig from SoC level. Instead use
device tree PINCTRL entry with updated clock control driver.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Add support for Microchip MEC15xx to the XEC clock control driver.
MEC15xx 32KHz clock support uses the same 32KHz source for both the
PLL and peripherals. MEC152x does not include the PCR clock monitor
present in MEC172x. MEC15xx and MEC172x support internal silicon
oscillator, parallel and single ended crystal inputs, and the
32KHZ_PIN input. MEC152x supports fall back to internal silicon
OSC when VTR and 32KHZ_PIN are turned off. Therefore in MEC152x the
internal silicon oscillator can only be disabled if using an external
32KHz which is always on. For MEC152x the driver will only use the
PLL source clock device tree value.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Fix Microchip XEC clock control driver single-ended XTAL2 pin
initialization. Add support for external 32KHZ_IN pin as a
clock source including PINTRL to switch the GPIO to 32KHZ_IN
function. Add device tree option to disable internal silicon
oscillator if it is not required by the configuration. Add
device tree tuning options based on crystal and board layout.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Enabling by default (if SPI3 used) because it affects all revisions
since "Engineering B", including the most recent one as of today
(revision 3).
Size changes when enabled:
- -Og: flash +160 bytes (+0.02%), RAM +8 bytes (+0.01%)
- -Os: flash +144 bytes (+0.02%), no change to RAM usage
Signed-off-by: Reto Schneider <reto.schneider@husqvarnagroup.com>
The unaligned trap bit is set by default, contrary to the xmc
reference manual. This PR unsets the bit in the initialization.
It can still be set later via the CONFIG_TRAP_UNALIGNED_ACCESS
option.
Note that the same approach is used in xmc4500 reference software
init code (see SystemCoreSetup() in infineon hal module).
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Cleaning up the instances of CODE_LOCATION used in the soc
clock_init and replaced them with the Kconfig
FLASH_MCUX_FLEXSPI_XIP due to the correlation with
the flexspi clocks and the XIP feature of Flexspi.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
This Kconfig is moved to the soc level since it determines
the flexspi clock initialization for XIP.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Added information about pin output direction into
Z_PINCTRL_STM32_PINCFG_INIT if output_low or output_high is provided.
GPIO output flag is set in configuration struct and this will end up
being loaded into MODE register. Because of that it is no longer
required for pinctrl_configure_pins() to set MODE register value for
GPIO input/output.
Fixes#53141.
Signed-off-by: Lukasz Mazur <lukasz.mazur@hidglobal.com>
Clean up occurrences of "#if IS_ENABLED(CONFIG_FOO)" an replace
with classical "#if defined(CONFIG_FOO)".
Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
This commit adds support for Silicon Labs EFR32BG22 SoC.
Co-authored-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
The ADC module has four conversion groups, each one is set up as a zephyr
device. The start-up calibration is initiated globally for all groups
and it is run in each device init function. The ADC module supports post
calibration per group. Post calibration is run automatically after each
group acquires the samples.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
xmc_device.h sets which XMC4xxx.h file to include and also sets
other defines such as GLOCK_GATING_SUPPORTED.
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Switch all imxrt boards to use the systick timer by default, and only
enable the GPT timer when using low power modes. This is desirable
because the systick has a higher resolution, but the GPT can run
while the core clock is gated, making it useful for low power modes.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
In Infineon XMC4XXX SoCs, gpio interrupts are triggered via an
Event Request Unit (ERU) module. A subset of the gpios are
connected to the ERU. The ERU monitors edge triggers and creates
a SR.
This driver configures the ERU for a target port/pin combination
for rising/falling edge events. Note that the ERU module does
not generate SR based on the gpio level. Internally the ERU
tracks the *status* of an event. The status is set on a positive
edge and unset on a negative edge (or vice-versa depending on
the configuration). The value of the status is used to implement
a level triggered interrupt; The ISR checks the status flag and
calls the callback function if the status is set.
The ERU configurations for supported port/pin combinations are
stored in a devicetree file dts/arm/infineon/xmc4xxx_x_x-intc.dtsi.
The configurations are stored in the opaque array
uint16 port_line_mapping[].
Signed-off-by: Andriy Gelman <andriy.gelman@gmail.com>
Currently, memory from __rodata_region_end to __kernel_ram_start (or
_app_smem_start if config userspace) was uncovered by programable MPU
region. But to config static MPU region (nocache region is on ths
region), the programable MPU region need confg full patition.
Signed-off-by: Duong Vu Nam <duong.vunam@nxp.com>
Add zephyr,memory-region compatible and attribute to SOC memory regions,
so that sections will be generated and MPU attributes can be applied.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Use the messaging unit to ensure that the RT11xx dual core mode will
wait for the second core to boot successfully during early init
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
RT11xx features CM4 core, which must be booted from CM7 core. Add
support for loading an image for the CM4 to RAM, and booting the CM4 core
from this image. Each image is built independently using sysbuild, and the
M4 image build produces built collateral with load address information the
M7 image can use to load it to RAM
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Allow linking code into OCRAM region when building for RT1xxx SOCs. This
can be used on the RT11xx dual core SOCs as a shared memory region, when
the M7 core needs to load code into a region accessible to the M4 core.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Expand ifdef by adding new Kconfig option UDC_KINETIS as
preparation for USBFSOTG UDC driver.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
The cache operations must be quick, optimized and possibly inlined. The
current API is clunky, functions are not inlined and passing parameters
around that are basically always known at compile time.
In this patch we rework the cache functions to allow us to get rid of
useless parameters and make inlining easier.
In particular this changeset is doing three things:
1. `CONFIG_HAS_ARCH_CACHE` is now `CONFIG_ARCH_CACHE` and
`CONFIG_HAS_EXTERNAL_CACHE` is now `CONFIG_EXTERNAL_CACHE`
2. The cache API has been reworked.
3. Comments are added.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Add a hidden Kconfig option to select the index of the target RTU
(Real-Time Unit) subsystem. This index can be used by peripheral
drivers, for example, to know the peripheral instance index since the
HAL is index-based.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Microchip XEC GPIO pins support inverting the output of
alternate pin functions. This feature may be useful for
those peripherals that do not implement output inversion
in the peripheral. GPIO control register pad input and
parallel input register values are not affected by the
function output invert feature. GPIO interrupt detection
of an output is inverted if the invert polarity is enabled.
Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
Added a missing SDK function POWER_PowerInit
to the clock_init function of the soc in lpc55S36.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
EXTRA_IMGTOOL_ARGS is used to set additional options by the user.
Any user change will overwrite this option, which
is unintuitive.
Also option ROM_START_OFFSET will be overwritten which is also unintuitive.
Replace hardcoded config option MCUBOOT_EXTRA_IMGTOOL_ARGS
with proper config ROM_START_OFFSET.
Signed-off-by: Maciej Zagrabski <mzi@trackunit.com>
HAL for NXP S32 is updated to a newer version, hence some headers and
macro definitions must be updated accordingly.
Signed-off-by: Manuel Arguelles <manuel.arguelles@nxp.com>
Update rt5xx base address calculation to use the zephyr,chosen flash node
to determine flash base address. Note that due to the external flash
controller, the flexSPI base address must be used when the flash device
is on the flexSPI bus.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Update rt6xx base address calculation to use the zephyr,chosen flash node
to determine flash base address. Note that due to the external flash
controller, the flexSPI base address must be used when the flash device
is on the flexSPI bus.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Updated the clock_init function to the latest sdk
and added a safe initialization for the flash setup
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
