Improve the radio off code, mainly:
- Compile the file only if necessary, ie, LORA radio not in use
- Use pin information from DT, so that we do not need to hardcode pins
and can switch to dt-spec APIs.
- Improve error handling, includes, etc.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Although existing nRF SoCs have only one I2S instance, the nrfx_i2s
driver has now multi-instance API and the related nrfx configuration
symbols need to be used appropriately.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Ensure code cache is enabled at boot for RT11xx. CMSIS SystemInit should
enable the code cache, but if CONFIG_INIT_ARCH_HW_AT_BOOT=y and
CONFIG_CACHE_MANAGEMENT=y, then the cache will be disabled after
SystemInit is called. Since calling SCB_EnableICache will not
change hardware settings if the ICACHE is already enabled, just
call it unconditionally during init.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Add Silicon Labs xG24-PK6010A (BRD4187C radio plug-in board)
support to the efr32_radio board.
Signed-off-by: Markus Fuchs <markus.fuchs@ch.sauter-bc.com>
For certain combinations of configuration parameters,
z_arm_init_arch_hw_at_boot() disables the instruction cache. Make sure
to re-enable it if required.
Signed-off-by: Jan Peters <peters@kt-elektronik.de>
Clearing of shared memory by one side of the communication
is no longer required after
commit 0620cb1fe1
("ipc: ipc_service: icmsg: Increase reliability of bonding")
was merged.
Signed-off-by: Emil Obalski <Emil.Obalski@nordicsemi.no>
To be consistent with the current NXP clocking scheme,
move the LPADC clocking code to the SOC files where
all of the other peripheral clocking is done.
Also remove any other SOC-specific code to the
respective SOC file and out of this driver.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
It is enabled by default if Device Tree includes a flash controller,
and disabled otherwise. SoC defconfig should not touch it.
Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
The mps3 soc is missing PMU defines required for CMSIS. This
adds the defines __PMU_PRESENT and __PMU_NUM_EVENTCNT
enabling the api for the PMU.
Signed-off-by: Ryan McClelland <ryanmcclelland@meta.com>
Move STM32H7_DUAL_CORE to
soc/arm/st_stm32/stm32h7/Kconfig.soc
add select STM32H7_DUAL_CORE for SOC_STM32H745XX/H747XX
Cleanup old occurences where was set to y
Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
This new Kconfig option lets the developer configure if the Cortex M4
core should be force-booted during M7 init independent of the BCM4
option byte.
This allows to disable this default behaviour via Kconfig which was not
possible so far.
Signed-off-by: Jan Krautmacher <jan@krautmacher.org>
Deprecates setting GPREGRET to the reset reason as this has been
replaced with the boot mode retention subsystem for nRF51/nRF52.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This commit adds the Gecko IADC driver and support for it to the
efr32bg_sltb010a board.
Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
Secure Element's mailbox is needed for entropy gathering purposes.
Enable it in the EFR32MG24 SoC series Kconfig.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
- Add Gecko BURTC sys_clock driver to handle wake up from EM2,3 states
- Remove custom PM policy and dependency on HAL sl_power_manager service
- EM1 supported in all configurations
- EM2,3 supported only if SysTick is replaced by BURTC
Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
This commit adds the SiLabs Bluetooth HCI driver. It also enables this
BLE HCI driver on the efr32bg_sltb010a board.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
HAL API changes in ethernet and pwm
SoC RT595 power management code change
west.yml update
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
This prevents configuration errors if a board is configured when
the SoC indicates segger RTT support but the segger module is
not available.
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This adds the SPI driver for the Renesas SmartBond(tm) DA1469x MCU family.
The driver only supports controller mode. All four SPI modes are supported.
Note that the lowest supported speed is 2285714Hz.
Requesting speeds higher than 16MHz, will result in a 16MHz SCLK.
Co-authored-by: Stan Geitel <stan@geitel.nl>
Signed-off-by: Ben Lauret <ben.lauret.wm@renesas.com>
This commit adds a missing `__weak` symbol to the `pm_policy_next_state`
function.
This is needed for e.g. `tests/kernel/profiling/profiling_api` to build
correctly.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
The nRF9161 is technically a SiP (System-in-Package) that consists of
the nRF9120 SoC and additional components like PMIC, FEM, and XTAL,
so for nrfx/MDK the nRF9120 SoC is to be selected as the build target,
but since the nRF9161 is what a user can actually see on a board, using
only nRF9120 in the Zephyr build infrastructure might be confusing.
That's why in the top level of SoC definitions (for user-configurable
options in Kconfig, for example) the nRF9161 term is used and nRF9120
underneath.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
Use one common `if SOC_SERIES_NRF52X` instead of `depends on` for
each particular SoC option.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This is a follow-up to commit 4be102f8e05a9fa12290d8209a8cb38569265478.
Inclusion of `<system_nrf*.>` from `soc.c` files is no longer needed
since `SystemInit()` is not called from those files.
Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
This adds USB-HS support for LPC55S16, much in the same way that
LPC55S28 support was added previously.
Signed-off-by: Maxime Vincent <maxime@veemax.be>
Many areas of Zephyr divide and round up without using the DIV_ROUND_UP
macro. Make use of it, so that we make use of a tested system macro and
at the same time we make code more readable.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
The init infrastructure, found in `init.h`, is currently used by:
- `SYS_INIT`: to call functions before `main`
- `DEVICE_*`: to initialize devices
They are all sorted according to an initialization level + a priority.
`SYS_INIT` calls are really orthogonal to devices, however, the required
function signature requires a `const struct device *dev` as a first
argument. The only reason for that is because the same init machinery is
used by devices, so we have something like:
```c
struct init_entry {
int (*init)(const struct device *dev);
/* only set by DEVICE_*, otherwise NULL */
const struct device *dev;
}
```
As a result, we end up with such weird/ugly pattern:
```c
static int my_init(const struct device *dev)
{
/* always NULL! add ARG_UNUSED to avoid compiler warning */
ARG_UNUSED(dev);
...
}
```
This is really a result of poor internals isolation. This patch proposes
a to make init entries more flexible so that they can accept sytem
initialization calls like this:
```c
static int my_init(void)
{
...
}
```
This is achieved using a union:
```c
union init_function {
/* for SYS_INIT, used when init_entry.dev == NULL */
int (*sys)(void);
/* for DEVICE*, used when init_entry.dev != NULL */
int (*dev)(const struct device *dev);
};
struct init_entry {
/* stores init function (either for SYS_INIT or DEVICE*)
union init_function init_fn;
/* stores device pointer for DEVICE*, NULL for SYS_INIT. Allows
* to know which union entry to call.
*/
const struct device *dev;
}
```
This solution **does not increase ROM usage**, and allows to offer clean
public APIs for both SYS_INIT and DEVICE*. Note that however, init
machinery keeps a coupling with devices.
**NOTE**: This is a breaking change! All `SYS_INIT` functions will need
to be converted to the new signature. See the script offered in the
following commit.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
init: convert SYS_INIT functions to the new signature
Conversion scripted using scripts/utils/migrate_sys_init.py.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
manifest: update projects for SYS_INIT changes
Update modules with updated SYS_INIT calls:
- hal_ti
- lvgl
- sof
- TraceRecorderSource
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
tests: devicetree: devices: adjust test
Adjust test according to the recently introduced SYS_INIT
infrastructure.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
tests: kernel: threads: adjust SYS_INIT call
Adjust to the new signature: int (*init_fn)(void);
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Remove per soc definitions that are already defined in the exact same
way in include/zephyr/arch/arm/aarch32/nmi.h.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Remove per soc definitions that are already defined in the exact same
way in include/zephyr/arch/arm/aarch32/nmi.h.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Initialization part of this anomaly is now handled internally
by the startup code provided by the MDK.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
Zephyr PM expects the SoC layer upon wake to unmask interrupts
the PM layer masked. MEC172x was re-enabling interrupt globally
in the Cortex-M4 but not clearing the mask set by Zephyr PM.
This worked in previous Zephyr releases but broke in the latest
Zephyr changes. Fixed the SoC to re-enable interrupts globally
and call irq_unlock(0) as Zephyr PM does if pm_state_exit_post_ops
is not implemented. Tested on MEC172x EVB with PLL clock out pin
enabled and verified PLL goes off in deep sleep, system wakes,
and interrupts are firing.
Signed-off-by: scott worley <scott.worley@microchip.com>
This commit introduces power management support for EFR32BG SoCs.
Tested on the efr32bg_sltb010a board.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
There are some issues with the current version of the code, mainly the
improper use of the internal OSC8M as a source for the DFLL48m without
division. The DFLL48M is designed to accept a maximum of ~33KHz
at it's input, as higher values will bring the multiplier down,
leading to instability.
Also added the following features:
* Support for external HF oscillator (XOSC)
* Support for crystal/external oscillators on XOSC32K/XOSC
* Automatic dividers/multiplier computation based on DT cpu frequency
* Support for user configurable NVM wait states
* Added option to skip clock (re)initialization (bootloader usecase).
Tests were performed on a custom SAMD20G18 board using different clock
sources and cpu frequencies.
Clocks were routed to GPIO pins and observed on a scope.
According to the datasheet, architecture is identical on D21/R21.
Due to the nature of the internal architecture and the fact that
DFLL48M is not really meant to output anything other than 48MHZ
some combinations of requested DT cpu frequency and source
frequency will not result in a perfect match.
Mostly insipred by the SAML21 implementation.
Signed-off-by: Ionut Catalin Pavel <iocapa@iocapa.com>
1. Move the GPIO mux setting to the soc layer. The GPIO MUX
value may vary based on the SoC Family
2. Enable the digital input buffer if available
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Add configuration items to select various ARM debug options
such as SWD only, SWD plus SWV, or SWD plus ETM. The default
is SWD only.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Enable at SoC boot time when enabled through Kconfig. Cache management
API is not used since it could be built without its support enabled.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
