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zephyr/soc/arm/nxp_imx/rt/soc_rt10xx.c

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arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
/*
soc: arm: nxp_imx: support enet2 interface on RT106x series This patch enables the PLL clock output and PLL ref clock for second ethernet module in NXP's i.MxRT106x SoCs Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
2023-05-17 05:37:54 +05:30
* Copyright 2017-2023 NXP
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
*
* SPDX-License-Identifier: Apache-2.0
*/
soc: migrate includes to <zephyr/...> In order to bring consistency in-tree, migrate all soc code to the new prefix <zephyr/...>. Note that the conversion has been scripted, refer to zephyrproject-rtos#45388 for more details. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 11:11:04 +02:00
#include <zephyr/kernel.h>
#include <zephyr/device.h>
#include <zephyr/init.h>
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
#include <soc.h>
soc: migrate includes to <zephyr/...> In order to bring consistency in-tree, migrate all soc code to the new prefix <zephyr/...>. Note that the conversion has been scripted, refer to zephyrproject-rtos#45388 for more details. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 11:11:04 +02:00
#include <zephyr/linker/sections.h>
#include <zephyr/linker/linker-defs.h>
soc: arm: replace redundant config option for caches for nxp_imx Replace the redundant cache config options for the nxp_imx and use sys_cache* functions to enable the caches. These will automatically consider CONFIG_CACHE_MANAGEMENT. Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
2023-12-18 10:41:25 +01:00
#include <zephyr/cache.h>
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
#include <fsl_clock.h>
soc: nxp_imx: include fsl_flexspi_nor_boot when boot header is present Only include fsl_flexspi_nor_boot when a boot header is present, as this is the only case where the boot header data will be required. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-11-01 17:54:03 -05:00
#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER
soc: nxp_imx: Add support for external xip flash boot header Adds support for the boot data, image vector table, and FlexSPI NOR config structures used by the imx rt boot ROM to boot an application from an external xip flash device. It is now possible to build and flash a bootable zephyr image to the external xip flash on the mimxrt1020_evk, mimxrt1050_evk, and mimxrt1060_evk boards via the 'ninja flash' build target and jlink runner. Note, however, that the default board configurations still link code into internal ITCM, therefore you must set CONFIG_CODE_HYPERFLASH=y or CONFIG_CODE_QSPI=y explicitly to override the default. You must also set CONFIG_NXP_IMX_RT_BOOT_HEADER=y to build the boot header into the image. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-12-27 08:09:53 -06:00
#include <fsl_flexspi_nor_boot.h>
soc: nxp_imx: include fsl_flexspi_nor_boot when boot header is present Only include fsl_flexspi_nor_boot when a boot header is present, as this is the only case where the boot header data will be required. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-11-01 17:54:03 -05:00
#endif
soc: migrate includes to <zephyr/...> In order to bring consistency in-tree, migrate all soc code to the new prefix <zephyr/...>. Note that the conversion has been scripted, refer to zephyrproject-rtos#45388 for more details. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 11:11:04 +02:00
#include <zephyr/dt-bindings/clock/imx_ccm.h>
soc: nxp_imx: rt: enable ethernet ref clock output Enable soc ethernet ref clock output at the SOC level instead of board level, since it is required for all iMX.RT SOCs Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-03-23 09:41:42 -05:00
#include <fsl_iomuxc.h>
soc: nxp_imx: configure USB device EHCI controller driver for rt1050 add usbd1 definition to rt dts file, set EHCI controller config default value in rt1050 default config file, add EHCI controller driver MACROs to dts_fixup.h, initialize EHCI clock in rt soc.c add HAS_MCUX_USB_EHCI for supported soc in Kconfig.soc Signed-off-by: Mark Wang <yichang.wang@nxp.com>
2019-05-05 13:20:04 +08:00
#if CONFIG_USB_DC_NXP_EHCI
#include "usb_phy.h"
drivers: usb: mcux: Restructure driver for SDK updates 1. Move the defines from usb_dc_mcux.h to usb_device_config.h and fsl_os_abstraction.h. These headers are used by the SDK USB driver. usb_dc_mcux.h header file is not longer needed and hence deleted. 2. Delete the Zephyr implementation of the usb_device_struct driver and use the one implemented inside the SDK USB driver. This requires updating the references to usb_device_struct inside the USB driver 3. Move defines and structures used by the driver out of the header file that is included by the SDK and into the MCUX USB driver. 4. Use end point defines provided by Zephyr instead of adding them locally. 5. Add a Kconfig to set the thread stack size 6. Move code to enable interrupts back to usb_attach function. Interrupts should be enabled after the init is successful, else we see errors of the ISR getting called before the init is complete causing Faults 6. Update west.yml to update the NXP HAL to get the updated SDK USB driver. Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-08-18 19:14:27 -05:00
#include "usb.h"
soc: nxp_imx: configure USB device EHCI controller driver for rt1050 add usbd1 definition to rt dts file, set EHCI controller config default value in rt1050 default config file, add EHCI controller driver MACROs to dts_fixup.h, initialize EHCI clock in rt soc.c add HAS_MCUX_USB_EHCI for supported soc in Kconfig.soc Signed-off-by: Mark Wang <yichang.wang@nxp.com>
2019-05-05 13:20:04 +08:00
#endif
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
soc: nxp: rt1xxx: Enable NXP FlexRAM Enable NXP FlexRAM in DTS and SOC code. Do not configure flexram at runtime if the code is in the RAM. Fix RT1060 DT to be more accurate. Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2023-09-14 19:40:17 -05:00
#include "memc_nxp_flexram.h"
modules: cmsis: move glue code to modules/cmsis The CMSIS module glue code was part of arch/ directory. Move it to modules/cmsis, and provide a single entry point for it: cmsis_core.h. This entry header will include the right CMSIS header (M or A/R). To make this change possible, CMSIS module Kconfig/CMake are declared as external, allowing us to add a new Zephyr include directory. All files including CMSIS have been updated. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-06-29 18:22:37 +02:00
#include <cmsis_core.h>
ARM: nxp_imx: rt10xx: add XTAL and RTC_XTAL DT clocks There are two external clocks driving i.MX RT 10xx SoCs: XTAL and RTC_XTAL. Add "fixed-clock" DT nodes for each. Update also "nxp,imx-ccm" binding, so that CCM (Clock Control Module) peripheral consumes those clocks by "xtal" and "rtc-xtal" names. Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
2022-08-31 22:43:34 +02:00
#define CCM_NODE DT_INST(0, nxp_imx_ccm)
ARM: nxp_imx: rt10xx: migrate ARM, AHB and IPG dividers to DT Those dividers were configured in Kconfig so far. Add 'arm-podf', 'ahb-podf' and 'ipg-podf' "fixed-factor-clock" compatible DT child nodes under 'ccm' (Clock Control Module) and use configured 'clock-div' values instead of Kconfig equivalents. Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
2022-09-07 10:02:16 +02:00
#define BUILD_ASSERT_PODF_IN_RANGE(podf, a, b) \
BUILD_ASSERT(DT_PROP(DT_CHILD(CCM_NODE, podf), clock_div) >= (a) && \
DT_PROP(DT_CHILD(CCM_NODE, podf), clock_div) <= (b), \
#podf " is out of supported range (" #a ", " #b ")")
boards: mimxrt1050_evk: add condition to initialize different PLL - add conditions to initialize different PLL Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2018-05-14 07:45:32 +08:00
#ifdef CONFIG_INIT_ARM_PLL
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
/* ARM PLL configuration for RUN mode */
const clock_arm_pll_config_t armPllConfig = {
.loopDivider = 100U
};
boards: mimxrt1050_evk: add condition to initialize different PLL - add conditions to initialize different PLL Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2018-05-14 07:45:32 +08:00
#endif
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
soc: nxp_imx: configure USB device EHCI controller driver for rt1050 add usbd1 definition to rt dts file, set EHCI controller config default value in rt1050 default config file, add EHCI controller driver MACROs to dts_fixup.h, initialize EHCI clock in rt soc.c add HAS_MCUX_USB_EHCI for supported soc in Kconfig.soc Signed-off-by: Mark Wang <yichang.wang@nxp.com>
2019-05-05 13:20:04 +08:00
#if CONFIG_USB_DC_NXP_EHCI
/* USB PHY condfiguration */
#define BOARD_USB_PHY_D_CAL (0x0CU)
#define BOARD_USB_PHY_TXCAL45DP (0x06U)
#define BOARD_USB_PHY_TXCAL45DM (0x06U)
#endif
soc: nxp_imx: rt: fix enet pll initialization config macro name - Update config macro name for enet pll - Update impacted defconfig of RT1052 Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2019-01-09 14:01:41 +08:00
#ifdef CONFIG_INIT_ENET_PLL
/* ENET PLL configuration for RUN mode */
mimxrt1050_evk: enabling networking hardware Enables Networking hardware on i.MX-RT 1050-EVKB board. Pinout enabled board specific etherenet connection, also pin initialization was moved later to PRE_KERNEL_2 in order to have sysclock initialized before. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2018-11-15 18:28:47 +02:00
const clock_enet_pll_config_t ethPllConfig = {
soc: arm: nxp_imx: rt: mimxrt1024: add device support - Add soc information for RT1024 Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
2020-10-23 10:37:17 +08:00
#if defined(CONFIG_SOC_MIMXRT1011) || \
defined(CONFIG_SOC_MIMXRT1015) || \
defined(CONFIG_SOC_MIMXRT1021) || \
defined(CONFIG_SOC_MIMXRT1024)
arch: arm: nxp: imxrt1021: add device support - Add Soc information for RT1020 Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2019-01-08 08:27:52 +08:00
.enableClkOutput500M = true,
soc: nxp_imx: Fix enabling ENET PLL outputs The ENET PLL should be enabled if the SoC is the MIMXRT1021 (it used by the ARM core) or if the ENET device is enabled. The 500MHz clock should be enabled if the SoC is the MIMXRT1021. The ENET clock should be enabled if the ENET device is enabled. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2019-01-20 21:14:08 +01:00
#endif
soc: rt10xx: enable phy clock with new driver when using either old or new driver for nxp enet, enable the phy clock Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2023-08-24 11:10:41 -05:00
#if defined(CONFIG_ETH_NXP_ENET) || defined(CONFIG_ETH_MCUX)
soc: arm: nxp_imx: support enet2 interface on RT106x series This patch enables the PLL clock output and PLL ref clock for second ethernet module in NXP's i.MxRT106x SoCs Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
2023-05-17 05:37:54 +05:30
#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay)
soc: nxp_imx: Fix ethernet build error Fixes an ethernet build error introduced with MCUXpresso SDK 2.5.0, caused by a slight change in the ethernet pll configuration structure. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-04 09:15:37 -06:00
.enableClkOutput = true,
arch: arm: nxp: imxrt1021: add device support - Add Soc information for RT1020 Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2019-01-08 08:27:52 +08:00
#endif
soc: arm: nxp_imx: support enet2 interface on RT106x series This patch enables the PLL clock output and PLL ref clock for second ethernet module in NXP's i.MxRT106x SoCs Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
2023-05-17 05:37:54 +05:30
#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet2), okay)
.enableClkOutput1 = true,
#endif
#endif
nxp: rt series eth timer clock enable enable ethernet timer clock when enabling ptp Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2021-05-17 14:36:21 +08:00
#if defined(CONFIG_PTP_CLOCK_MCUX)
.enableClkOutput25M = true,
#else
soc: nxp_imx: Fix ethernet build error Fixes an ethernet build error introduced with MCUXpresso SDK 2.5.0, caused by a slight change in the ethernet pll configuration structure. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-04 09:15:37 -06:00
.enableClkOutput25M = false,
nxp: rt series eth timer clock enable enable ethernet timer clock when enabling ptp Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2021-05-17 14:36:21 +08:00
#endif
soc: rt10xx: fix the sequence of Enet2 ref clk enablement This patch sets ENET2 ref clock to be generated by External OSC ENET2 ref clock direction as output ENET2 ref clk frequency to 50MHz Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
2023-06-04 23:56:09 +05:30
#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay)
soc: nxp_imx: Fix ethernet build error Fixes an ethernet build error introduced with MCUXpresso SDK 2.5.0, caused by a slight change in the ethernet pll configuration structure. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-04 09:15:37 -06:00
.loopDivider = 1,
soc: rt10xx: fix the sequence of Enet2 ref clk enablement This patch sets ENET2 ref clock to be generated by External OSC ENET2 ref clock direction as output ENET2 ref clk frequency to 50MHz Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
2023-06-04 23:56:09 +05:30
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet2), okay)
.loopDivider1 = 1,
#endif
mimxrt1050_evk: enabling networking hardware Enables Networking hardware on i.MX-RT 1050-EVKB board. Pinout enabled board specific etherenet connection, also pin initialization was moved later to PRE_KERNEL_2 in order to have sysclock initialized before. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2018-11-15 18:28:47 +02:00
};
#endif
soc: nxp_imx: configure USB device EHCI controller driver for rt1050 add usbd1 definition to rt dts file, set EHCI controller config default value in rt1050 default config file, add EHCI controller driver MACROs to dts_fixup.h, initialize EHCI clock in rt soc.c add HAS_MCUX_USB_EHCI for supported soc in Kconfig.soc Signed-off-by: Mark Wang <yichang.wang@nxp.com>
2019-05-05 13:20:04 +08:00
#if CONFIG_USB_DC_NXP_EHCI
usb_phy_config_struct_t usbPhyConfig = {
BOARD_USB_PHY_D_CAL, BOARD_USB_PHY_TXCAL45DP, BOARD_USB_PHY_TXCAL45DM,
};
#endif
soc: nxp_imx: Enable mcux elcdif driver and clocks Enables the mcux elcdif shim driver and clocks on imx rt socs when the display driver interface is enabled. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-02 13:11:28 -06:00
#ifdef CONFIG_INIT_VIDEO_PLL
const clock_video_pll_config_t videoPllConfig = {
.loopDivider = 31,
.postDivider = 8,
.numerator = 0,
.denominator = 0,
};
#endif
soc: nxp_imx: Add support for external xip flash boot header Adds support for the boot data, image vector table, and FlexSPI NOR config structures used by the imx rt boot ROM to boot an application from an external xip flash device. It is now possible to build and flash a bootable zephyr image to the external xip flash on the mimxrt1020_evk, mimxrt1050_evk, and mimxrt1060_evk boards via the 'ninja flash' build target and jlink runner. Note, however, that the default board configurations still link code into internal ITCM, therefore you must set CONFIG_CODE_HYPERFLASH=y or CONFIG_CODE_QSPI=y explicitly to override the default. You must also set CONFIG_NXP_IMX_RT_BOOT_HEADER=y to build the boot header into the image. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-12-27 08:09:53 -06:00
#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER
const __imx_boot_data_section BOOT_DATA_T boot_data = {
soc: arm: nxp_imx: update iMX RT boot header to handle CONFIG_XIP=n Update iMX RT boot header to support CONFIG_XIP=n, when the image is not linked into the flash space. Also, update the boot header to correctly calculate the flash used size within the boot data header. This field is used by the iMX boot ROM to determine how much data to copy when running from RAM, so using the correct size fixes an issue where the ROM would copy more data than needed. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-08-21 15:39:01 -05:00
#ifdef CONFIG_XIP
soc: nxp_imx: Add support for external xip flash boot header Adds support for the boot data, image vector table, and FlexSPI NOR config structures used by the imx rt boot ROM to boot an application from an external xip flash device. It is now possible to build and flash a bootable zephyr image to the external xip flash on the mimxrt1020_evk, mimxrt1050_evk, and mimxrt1060_evk boards via the 'ninja flash' build target and jlink runner. Note, however, that the default board configurations still link code into internal ITCM, therefore you must set CONFIG_CODE_HYPERFLASH=y or CONFIG_CODE_QSPI=y explicitly to override the default. You must also set CONFIG_NXP_IMX_RT_BOOT_HEADER=y to build the boot header into the image. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-12-27 08:09:53 -06:00
.start = CONFIG_FLASH_BASE_ADDRESS,
soc: arm: nxp_imx: update iMX RT boot header to handle CONFIG_XIP=n Update iMX RT boot header to support CONFIG_XIP=n, when the image is not linked into the flash space. Also, update the boot header to correctly calculate the flash used size within the boot data header. This field is used by the iMX boot ROM to determine how much data to copy when running from RAM, so using the correct size fixes an issue where the ROM would copy more data than needed. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-08-21 15:39:01 -05:00
.size = (uint32_t)&_flash_used,
#else
.start = CONFIG_SRAM_BASE_ADDRESS,
.size = (uint32_t)&_image_ram_size,
#endif
soc: nxp_imx: Add support for external xip flash boot header Adds support for the boot data, image vector table, and FlexSPI NOR config structures used by the imx rt boot ROM to boot an application from an external xip flash device. It is now possible to build and flash a bootable zephyr image to the external xip flash on the mimxrt1020_evk, mimxrt1050_evk, and mimxrt1060_evk boards via the 'ninja flash' build target and jlink runner. Note, however, that the default board configurations still link code into internal ITCM, therefore you must set CONFIG_CODE_HYPERFLASH=y or CONFIG_CODE_QSPI=y explicitly to override the default. You must also set CONFIG_NXP_IMX_RT_BOOT_HEADER=y to build the boot header into the image. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-12-27 08:09:53 -06:00
.plugin = PLUGIN_FLAG,
.placeholder = 0xFFFFFFFF,
};
const __imx_boot_ivt_section ivt image_vector_table = {
.hdr = IVT_HEADER,
soc: nxp_imx: Set entry to _vector_start in boot header Commit e80e655b01317458c5a85c38413f2cc4dbce1dc6 introduced linker script enforcement of Cortex-M vector table alignment. Update the i.MX RT boot header to account for the possibility that the vector table may not be placed at the address CONFIG_FLASH_BASE_ADDRESS + CONFIG_ROM_START_OFFSET anymore. For example, the RT1060 vector table has 176 entries and therefore must be aligned to 0x400 bytes. If CONFIG_FLASH_BASE_ADDRESS=0x60000000 and CONFIG_ROM_START_OFFSET=0x2200, the linker script will place the vector table at 0x60002400 instead of 0x60002200. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2020-08-17 16:29:05 -05:00
.entry = (uint32_t) _vector_start,
soc: nxp_imx: Add support for external xip flash boot header Adds support for the boot data, image vector table, and FlexSPI NOR config structures used by the imx rt boot ROM to boot an application from an external xip flash device. It is now possible to build and flash a bootable zephyr image to the external xip flash on the mimxrt1020_evk, mimxrt1050_evk, and mimxrt1060_evk boards via the 'ninja flash' build target and jlink runner. Note, however, that the default board configurations still link code into internal ITCM, therefore you must set CONFIG_CODE_HYPERFLASH=y or CONFIG_CODE_QSPI=y explicitly to override the default. You must also set CONFIG_NXP_IMX_RT_BOOT_HEADER=y to build the boot header into the image. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-12-27 08:09:53 -06:00
.reserved1 = IVT_RSVD,
soc: nxp_imx: Add support for device configuration data (DCD) Adds support for the device configuration data (DCD), which provides a sequence of commands to the imx rt boot ROM to initialize components such as an SDRAM. It is now possible to use the external SDRAM instead of the internal DTCM on the mimxrt1020_evk, mimxrt1050_evk, and mimxrt1060_evk. Note, however, that the default board configurations still link data into internal DTCM, therefore you must use a device tree overlay to override "zephyr,sram = &sdram0" Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-12-28 08:43:48 -06:00
#ifdef CONFIG_DEVICE_CONFIGURATION_DATA
.dcd = (uint32_t) dcd_data,
#else
soc: nxp_imx: Add support for external xip flash boot header Adds support for the boot data, image vector table, and FlexSPI NOR config structures used by the imx rt boot ROM to boot an application from an external xip flash device. It is now possible to build and flash a bootable zephyr image to the external xip flash on the mimxrt1020_evk, mimxrt1050_evk, and mimxrt1060_evk boards via the 'ninja flash' build target and jlink runner. Note, however, that the default board configurations still link code into internal ITCM, therefore you must set CONFIG_CODE_HYPERFLASH=y or CONFIG_CODE_QSPI=y explicitly to override the default. You must also set CONFIG_NXP_IMX_RT_BOOT_HEADER=y to build the boot header into the image. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-12-27 08:09:53 -06:00
.dcd = (uint32_t) NULL,
soc: nxp_imx: Add support for device configuration data (DCD) Adds support for the device configuration data (DCD), which provides a sequence of commands to the imx rt boot ROM to initialize components such as an SDRAM. It is now possible to use the external SDRAM instead of the internal DTCM on the mimxrt1020_evk, mimxrt1050_evk, and mimxrt1060_evk. Note, however, that the default board configurations still link data into internal DTCM, therefore you must use a device tree overlay to override "zephyr,sram = &sdram0" Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-12-28 08:43:48 -06:00
#endif
soc: nxp_imx: Add support for external xip flash boot header Adds support for the boot data, image vector table, and FlexSPI NOR config structures used by the imx rt boot ROM to boot an application from an external xip flash device. It is now possible to build and flash a bootable zephyr image to the external xip flash on the mimxrt1020_evk, mimxrt1050_evk, and mimxrt1060_evk boards via the 'ninja flash' build target and jlink runner. Note, however, that the default board configurations still link code into internal ITCM, therefore you must set CONFIG_CODE_HYPERFLASH=y or CONFIG_CODE_QSPI=y explicitly to override the default. You must also set CONFIG_NXP_IMX_RT_BOOT_HEADER=y to build the boot header into the image. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-12-27 08:09:53 -06:00
.boot_data = (uint32_t) &boot_data,
.self = (uint32_t) &image_vector_table,
.csf = (uint32_t)CSF_ADDRESS,
.reserved2 = IVT_RSVD,
};
#endif
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
/**
* @brief Initialize the system clock
*/
arm: arch code naming cleanup This patch re-namespaces global variables and functions that are used only within the arch/arm/ code to be prefixed with z_arm_. Some instances of CamelCase have been corrected. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-09-30 12:31:07 -07:00
static ALWAYS_INLINE void clock_init(void)
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
{
/* Boot ROM did initialize the XTAL, here we only sets external XTAL
* OSC freq
*/
ARM: nxp_imx: rt10xx: add XTAL and RTC_XTAL DT clocks There are two external clocks driving i.MX RT 10xx SoCs: XTAL and RTC_XTAL. Add "fixed-clock" DT nodes for each. Update also "nxp,imx-ccm" binding, so that CCM (Clock Control Module) peripheral consumes those clocks by "xtal" and "rtc-xtal" names. Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
2022-08-31 22:43:34 +02:00
CLOCK_SetXtalFreq(DT_PROP(DT_CLOCKS_CTLR_BY_NAME(CCM_NODE, xtal),
clock_frequency));
CLOCK_SetRtcXtalFreq(DT_PROP(DT_CLOCKS_CTLR_BY_NAME(CCM_NODE, rtc_xtal),
clock_frequency));
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
/* Set PERIPH_CLK2 MUX to OSC */
CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0x1);
/* Set PERIPH_CLK MUX to PERIPH_CLK2 */
CLOCK_SetMux(kCLOCK_PeriphMux, 0x1);
soc: mxrt10xx: Update the clock init code 1. Setup VDD_SOC with the appropriate setting depending on the SoC 2. Do not configure PLL_SYS and PLL_USB. These are already configured by the ROM code using the DCD 3. Fix setting for USDHC clock Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-01-17 22:16:10 -06:00
/* Setting the VDD_SOC value.
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
*/
soc: mxrt10xx: Update the clock init code 1. Setup VDD_SOC with the appropriate setting depending on the SoC 2. Do not configure PLL_SYS and PLL_USB. These are already configured by the ROM code using the DCD 3. Fix setting for USDHC clock Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-01-17 22:16:10 -06:00
DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(CONFIG_DCDC_VALUE);
mimxrt1050: fix dcdc value change process - to check status bit to make sure DCDC output is stable Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2018-05-14 07:45:59 +08:00
/* Waiting for DCDC_STS_DC_OK bit is asserted */
while (DCDC_REG0_STS_DC_OK_MASK !=
(DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0)) {
;
}
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
boards: mimxrt1050_evk: add condition to initialize different PLL - add conditions to initialize different PLL Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2018-05-14 07:45:32 +08:00
#ifdef CONFIG_INIT_ARM_PLL
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
CLOCK_InitArmPll(&armPllConfig); /* Configure ARM PLL to 1200M */
boards: mimxrt1050_evk: add condition to initialize different PLL - add conditions to initialize different PLL Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2018-05-14 07:45:32 +08:00
#endif
soc: nxp_imx: rt: fix enet pll initialization config macro name - Update config macro name for enet pll - Update impacted defconfig of RT1052 Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2019-01-09 14:01:41 +08:00
#ifdef CONFIG_INIT_ENET_PLL
mimxrt1050_evk: enabling networking hardware Enables Networking hardware on i.MX-RT 1050-EVKB board. Pinout enabled board specific etherenet connection, also pin initialization was moved later to PRE_KERNEL_2 in order to have sysclock initialized before. Signed-off-by: Andrei Gansari <andrei.gansari@nxp.com>
2018-11-15 18:28:47 +02:00
CLOCK_InitEnetPll(&ethPllConfig);
#endif
soc: nxp_imx: Enable mcux elcdif driver and clocks Enables the mcux elcdif shim driver and clocks on imx rt socs when the display driver interface is enabled. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-02 13:11:28 -06:00
#ifdef CONFIG_INIT_VIDEO_PLL
CLOCK_InitVideoPll(&videoPllConfig);
#endif
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
ARM: nxp_imx: rt10xx: migrate ARM, AHB and IPG dividers to DT Those dividers were configured in Kconfig so far. Add 'arm-podf', 'ahb-podf' and 'ipg-podf' "fixed-factor-clock" compatible DT child nodes under 'ccm' (Clock Control Module) and use configured 'clock-div' values instead of Kconfig equivalents. Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
2022-09-07 10:02:16 +02:00
#if DT_NODE_EXISTS(DT_CHILD(CCM_NODE, arm_podf))
/* Set ARM PODF */
BUILD_ASSERT_PODF_IN_RANGE(arm_podf, 1, 8);
CLOCK_SetDiv(kCLOCK_ArmDiv, DT_PROP(DT_CHILD(CCM_NODE, arm_podf), clock_div) - 1);
soc: arm: nxp_imx: rt: add device support i.MX RT1010 - Add device support for i.MXRT1010 Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2019-09-24 08:52:39 +08:00
#endif
ARM: nxp_imx: rt10xx: migrate ARM, AHB and IPG dividers to DT Those dividers were configured in Kconfig so far. Add 'arm-podf', 'ahb-podf' and 'ipg-podf' "fixed-factor-clock" compatible DT child nodes under 'ccm' (Clock Control Module) and use configured 'clock-div' values instead of Kconfig equivalents. Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
2022-09-07 10:02:16 +02:00
/* Set AHB PODF */
BUILD_ASSERT_PODF_IN_RANGE(ahb_podf, 1, 8);
CLOCK_SetDiv(kCLOCK_AhbDiv, DT_PROP(DT_CHILD(CCM_NODE, ahb_podf), clock_div) - 1);
/* Set IPG PODF */
BUILD_ASSERT_PODF_IN_RANGE(ipg_podf, 1, 4);
CLOCK_SetDiv(kCLOCK_IpgDiv, DT_PROP(DT_CHILD(CCM_NODE, ipg_podf), clock_div) - 1);
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
/* Set PRE_PERIPH_CLK to PLL1, 1200M */
CLOCK_SetMux(kCLOCK_PrePeriphMux, 0x3);
/* Set PERIPH_CLK MUX to PRE_PERIPH_CLK */
CLOCK_SetMux(kCLOCK_PeriphMux, 0x0);
#ifdef CONFIG_UART_MCUX_LPUART
/* Configure UART divider to default */
CLOCK_SetMux(kCLOCK_UartMux, 0); /* Set UART source to PLL3 80M */
CLOCK_SetDiv(kCLOCK_UartDiv, 0); /* Set UART divider to 1 */
#endif
mimxrt1050: remove app specific code from soc file - Remove clock gating code to be compatible with A1 silicon - Remove PLL deinitialization code out of soc file Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2018-05-15 03:06:14 -08:00
soc: nxp_imx: Enable mcux lpi2c driver and clocks Enables the mcux lpi2c shim driver and clocks on all imx rt socs when the i2c driver interface is enabled. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-16 15:22:22 -06:00
#ifdef CONFIG_I2C_MCUX_LPI2C
CLOCK_SetMux(kCLOCK_Lpi2cMux, 0); /* Set I2C source as USB1 PLL 480M */
CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 5); /* Set I2C divider to 6 */
#endif
soc: arm: Enable the lpspi driver and clock for the imxrt soc Enables the mcux lpspi shim driver and subsystem clock for the imxrt soc. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-09-14 16:18:41 -05:00
#ifdef CONFIG_SPI_MCUX_LPSPI
CLOCK_SetMux(kCLOCK_LpspiMux, 1); /* Set SPI source to USB1 PFD0 720M */
CLOCK_SetDiv(kCLOCK_LpspiDiv, 7); /* Set SPI divider to 8 */
#endif
soc: nxp_imx: Enable mcux elcdif driver and clocks Enables the mcux elcdif shim driver and clocks on imx rt socs when the display driver interface is enabled. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-02 13:11:28 -06:00
#ifdef CONFIG_DISPLAY_MCUX_ELCDIF
drivers: display: update MCUX ELCDIF driver to use new lcdif binding Update MCUX ELCDIF driver to use new LCDIF bindings. This update also adds support for configuring the root clock of the ELCDIF module based on the pixel-clock property to the RT11xx SOC clock init, as this SOC series has this IP block Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-01-18 10:40:15 -06:00
/* MUX selects video PLL, which is initialized to 93MHz */
soc: nxp_imx: Enable mcux elcdif driver and clocks Enables the mcux elcdif shim driver and clocks on imx rt socs when the display driver interface is enabled. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-02 13:11:28 -06:00
CLOCK_SetMux(kCLOCK_LcdifPreMux, 2);
drivers: display: update MCUX ELCDIF driver to use new lcdif binding Update MCUX ELCDIF driver to use new LCDIF bindings. This update also adds support for configuring the root clock of the ELCDIF module based on the pixel-clock property to the RT11xx SOC clock init, as this SOC series has this IP block Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-01-18 10:40:15 -06:00
/* Divide output by 2 */
soc: nxp_imx: Enable mcux elcdif driver and clocks Enables the mcux elcdif shim driver and clocks on imx rt socs when the display driver interface is enabled. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-02 13:11:28 -06:00
CLOCK_SetDiv(kCLOCK_LcdifDiv, 1);
drivers: display: update MCUX ELCDIF driver to use new lcdif binding Update MCUX ELCDIF driver to use new LCDIF bindings. This update also adds support for configuring the root clock of the ELCDIF module based on the pixel-clock property to the RT11xx SOC clock init, as this SOC series has this IP block Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-01-18 10:40:15 -06:00
/* Set final div based on LCDIF clock-frequency */
CLOCK_SetDiv(kCLOCK_LcdifPreDiv,
((CLOCK_GetPllFreq(kCLOCK_PllVideo) / 2) /
DT_PROP(DT_CHILD(DT_NODELABEL(lcdif), display_timings),
clock_frequency)) - 1);
soc: nxp_imx: Enable mcux elcdif driver and clocks Enables the mcux elcdif shim driver and clocks on imx rt socs when the display driver interface is enabled. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2019-01-02 13:11:28 -06:00
#endif
soc: nxp_imx: rt: enable ethernet ref clock output Enable soc ethernet ref clock output at the SOC level instead of board level, since it is required for all iMX.RT SOCs Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-03-23 09:41:42 -05:00
#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet), okay) && CONFIG_NET_L2_ETHERNET
soc: arm: imx_rt10xx: support enet1 external clock Configure ENET_REF_CLK direction as input when CONFIG_ETH_MCUX_RMII_EXT_CLK is set to allow Ethernet external clock usage. Signed-off-by: Benjamin Lemouzy <blemouzy@centralp.fr>
2023-06-29 11:11:24 +02:00
#if CONFIG_ETH_MCUX_RMII_EXT_CLK
/* Enable clock input for ENET1 */
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, false);
#else
soc: nxp_imx: rt: enable ethernet ref clock output Enable soc ethernet ref clock output at the SOC level instead of board level, since it is required for all iMX.RT SOCs Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-03-23 09:41:42 -05:00
/* Enable clock output for ENET1 */
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1TxClkOutputDir, true);
#endif
soc: arm: imx_rt10xx: support enet1 external clock Configure ENET_REF_CLK direction as input when CONFIG_ETH_MCUX_RMII_EXT_CLK is set to allow Ethernet external clock usage. Signed-off-by: Benjamin Lemouzy <blemouzy@centralp.fr>
2023-06-29 11:11:24 +02:00
#endif
soc: nxp_imx: rt: enable ethernet ref clock output Enable soc ethernet ref clock output at the SOC level instead of board level, since it is required for all iMX.RT SOCs Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-03-23 09:41:42 -05:00
soc: rt10xx: fix the sequence of Enet2 ref clk enablement This patch sets ENET2 ref clock to be generated by External OSC ENET2 ref clock direction as output ENET2 ref clk frequency to 50MHz Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
2023-06-04 23:56:09 +05:30
#if DT_NODE_HAS_STATUS(DT_NODELABEL(enet2), okay) && CONFIG_NET_L2_ETHERNET
/* Set ENET2 ref clock to be generated by External OSC,*/
/* direction as output and frequency to 50MHz */
IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET2TxClkOutputDir |
kIOMUXC_GPR_ENET2RefClkMode, true);
#endif
soc: rt10xx: Enable USB2 controller clock Enable USB2 controller clock on RT10xx SOC init, if nodelabel has status="okay" Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-02-24 12:40:02 -06:00
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb1), okay) && CONFIG_USB_DC_NXP_EHCI
soc: nxp_imx: configure USB device EHCI controller driver for rt1050 add usbd1 definition to rt dts file, set EHCI controller config default value in rt1050 default config file, add EHCI controller driver MACROs to dts_fixup.h, initialize EHCI clock in rt soc.c add HAS_MCUX_USB_EHCI for supported soc in Kconfig.soc Signed-off-by: Mark Wang <yichang.wang@nxp.com>
2019-05-05 13:20:04 +08:00
CLOCK_EnableUsbhs0PhyPllClock(kCLOCK_Usb480M,
soc: rt10xx: Enable USB2 controller clock Enable USB2 controller clock on RT10xx SOC init, if nodelabel has status="okay" Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-02-24 12:40:02 -06:00
DT_PROP_BY_PHANDLE(DT_NODELABEL(usb1), clocks, clock_frequency));
soc: nxp_imx: configure USB device EHCI controller driver for rt1050 add usbd1 definition to rt dts file, set EHCI controller config default value in rt1050 default config file, add EHCI controller driver MACROs to dts_fixup.h, initialize EHCI clock in rt soc.c add HAS_MCUX_USB_EHCI for supported soc in Kconfig.soc Signed-off-by: Mark Wang <yichang.wang@nxp.com>
2019-05-05 13:20:04 +08:00
CLOCK_EnableUsbhs0Clock(kCLOCK_Usb480M,
soc: rt10xx: Enable USB2 controller clock Enable USB2 controller clock on RT10xx SOC init, if nodelabel has status="okay" Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-02-24 12:40:02 -06:00
DT_PROP_BY_PHANDLE(DT_NODELABEL(usb1), clocks, clock_frequency));
soc: nxp_imx: configure USB device EHCI controller driver for rt1050 add usbd1 definition to rt dts file, set EHCI controller config default value in rt1050 default config file, add EHCI controller driver MACROs to dts_fixup.h, initialize EHCI clock in rt soc.c add HAS_MCUX_USB_EHCI for supported soc in Kconfig.soc Signed-off-by: Mark Wang <yichang.wang@nxp.com>
2019-05-05 13:20:04 +08:00
USB_EhciPhyInit(kUSB_ControllerEhci0, CPU_XTAL_CLK_HZ, &usbPhyConfig);
#endif
clock/usdhc: Enable clock of USDHC of i.MXRT Enable clock of USDHC of i.MXRT. Add clock interface for USDHC in ccm. Signed-off-by: Jun Yang <jun.yang@nxp.com>
2019-07-03 21:28:35 -07:00
soc: rt10xx: Enable USB2 controller clock Enable USB2 controller clock on RT10xx SOC init, if nodelabel has status="okay" Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-02-24 12:40:02 -06:00
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usb2), okay) && CONFIG_USB_DC_NXP_EHCI
CLOCK_EnableUsbhs1PhyPllClock(kCLOCK_Usb480M,
DT_PROP_BY_PHANDLE(DT_NODELABEL(usb2), clocks, clock_frequency));
CLOCK_EnableUsbhs1Clock(kCLOCK_Usb480M,
DT_PROP_BY_PHANDLE(DT_NODELABEL(usb2), clocks, clock_frequency));
USB_EhciPhyInit(kUSB_ControllerEhci1, CPU_XTAL_CLK_HZ, &usbPhyConfig);
#endif
boards: mimxrt1064: Enabled new SDHC driver Enabled new SDHC driver for mimxrt1064 evk Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-02-16 14:53:43 -06:00
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc1), okay) && CONFIG_IMX_USDHC
clock/usdhc: Enable clock of USDHC of i.MXRT Enable clock of USDHC of i.MXRT. Add clock interface for USDHC in ccm. Signed-off-by: Jun Yang <jun.yang@nxp.com>
2019-07-03 21:28:35 -07:00
/* Configure USDHC clock source and divider */
soc: rt10xx: Set divisor for sys pll (PLL2) PFD0 Divisor must be set to calculate SD host controller clock frequency in clock driver. Fixes #42380 Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-02-01 19:33:18 -06:00
CLOCK_InitSysPfd(kCLOCK_Pfd0, 24U);
soc: mxrt10xx: Update the clock init code 1. Setup VDD_SOC with the appropriate setting depending on the SoC 2. Do not configure PLL_SYS and PLL_USB. These are already configured by the ROM code using the DCD 3. Fix setting for USDHC clock Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-01-17 22:16:10 -06:00
CLOCK_SetDiv(kCLOCK_Usdhc1Div, 1U);
clock/usdhc: Enable clock of USDHC of i.MXRT Enable clock of USDHC of i.MXRT. Add clock interface for USDHC in ccm. Signed-off-by: Jun Yang <jun.yang@nxp.com>
2019-07-03 21:28:35 -07:00
CLOCK_SetMux(kCLOCK_Usdhc1Mux, 1U);
CLOCK_EnableClock(kCLOCK_Usdhc1);
#endif
boards: mimxrt1064: Enabled new SDHC driver Enabled new SDHC driver for mimxrt1064 evk Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-02-16 14:53:43 -06:00
#if DT_NODE_HAS_STATUS(DT_NODELABEL(usdhc2), okay) && CONFIG_IMX_USDHC
drivers: usdhc: fixup i.MX RT related code after driver relocation Fixup i.MX RT related code after driver relocation. Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
2021-02-24 11:07:56 +01:00
/* Configure USDHC clock source and divider */
soc: rt10xx: Set divisor for sys pll (PLL2) PFD0 Divisor must be set to calculate SD host controller clock frequency in clock driver. Fixes #42380 Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-02-01 19:33:18 -06:00
CLOCK_InitSysPfd(kCLOCK_Pfd0, 24U);
soc: mxrt10xx: Update the clock init code 1. Setup VDD_SOC with the appropriate setting depending on the SoC 2. Do not configure PLL_SYS and PLL_USB. These are already configured by the ROM code using the DCD 3. Fix setting for USDHC clock Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-01-17 22:16:10 -06:00
CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1U);
clock/usdhc: Enable clock of USDHC of i.MXRT Enable clock of USDHC of i.MXRT. Add clock interface for USDHC in ccm. Signed-off-by: Jun Yang <jun.yang@nxp.com>
2019-07-03 21:28:35 -07:00
CLOCK_SetMux(kCLOCK_Usdhc2Mux, 1U);
CLOCK_EnableClock(kCLOCK_Usdhc2);
#endif
drivers: usdhc: fixup i.MX RT related code after driver relocation Fixup i.MX RT related code after driver relocation. Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
2021-02-24 11:07:56 +01:00
soc: nxp: rt: Add CSI video support Add CSI node to generic nxp rt dtsi. Add corresponding dts binding. Add CSI capability for rt MCUs. Signed-off-by: Loic Poulain <loic.poulain@linaro.org>
2019-07-01 14:47:14 +02:00
#ifdef CONFIG_VIDEO_MCUX_CSI
CLOCK_EnableClock(kCLOCK_Csi); /* Disable CSI clock gate */
CLOCK_SetDiv(kCLOCK_CsiDiv, 0); /* Set CSI divider to 1 */
CLOCK_SetMux(kCLOCK_CsiMux, 0); /* Set CSI source to OSC 24M */
#endif
drivers: mcux: imx rt flexcan support Adds imx rt support. Allows n-number of can interfaces based on device-tree. Adds a "common" irq name. Added CAN bus pins and dts for 1060 and 1064 EVK. Signed-off-by: Rick Talbott <rtalbott@fastmail.com>
2020-09-03 11:13:09 -04:00
#ifdef CONFIG_CAN_MCUX_FLEXCAN
CLOCK_SetDiv(kCLOCK_CanDiv, 1); /* Set CAN_CLK_PODF. */
CLOCK_SetMux(kCLOCK_CanMux, 2); /* Set Can clock source. */
#endif
soc: nxp_imx: configure USB device EHCI controller driver for rt1050 add usbd1 definition to rt dts file, set EHCI controller config default value in rt1050 default config file, add EHCI controller driver MACROs to dts_fixup.h, initialize EHCI clock in rt soc.c add HAS_MCUX_USB_EHCI for supported soc in Kconfig.soc Signed-off-by: Mark Wang <yichang.wang@nxp.com>
2019-05-05 13:20:04 +08:00
soc: nxp_imx: rt: enable SWO output for iMX RT 10xx series enable swo output for iMX RT 10xx series. SWO pinmux settings are currently only present for the RT1060 and RT1064 Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-05-25 11:30:36 -05:00
#ifdef CONFIG_LOG_BACKEND_SWO
/* Enable ARM trace clock to enable SWO output */
CLOCK_EnableClock(kCLOCK_Trace);
/* Divide root clock output by 3 */
CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
/* Source clock from 528MHz system PLL */
CLOCK_SetMux(kCLOCK_TraceMux, 0);
#endif
imxrt1050: Disable low-power modes The imxrt1050 is configured to use SYSTICK for the kernel timer, but SYSTICK cannot wake up the soc from low-power modes. Disable low-power modes on this soc until we have support for an alternative timer. This fixes k_sleep on the EVKB version of the mimxrt1050_evk board. An earlier version of the board (EVK, not EVKB), had A0 silicon which by default did not enter low-power mode on a wfi. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2018-06-22 08:14:32 -05:00
/* Keep the system clock running so SYSTICK can wake up the system from
* wfi.
*/
CLOCK_SetMode(kCLOCK_ModeRun);
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
}
soc: add auido clock init per soc RT11xx and RT10xx have different audio clock settings so add them in soc.c Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2022-01-21 11:53:06 +08:00
#if CONFIG_I2S_MCUX_SAI
void imxrt_audio_codec_pll_init(uint32_t clock_name, uint32_t clk_src,
uint32_t clk_pre_div, uint32_t clk_src_div)
{
switch (clock_name) {
case IMX_CCM_SAI1_CLK:
CLOCK_SetMux(kCLOCK_Sai1Mux, clk_src);
CLOCK_SetDiv(kCLOCK_Sai1PreDiv, clk_pre_div);
CLOCK_SetDiv(kCLOCK_Sai1Div, clk_src_div);
break;
case IMX_CCM_SAI2_CLK:
CLOCK_SetMux(kCLOCK_Sai2Mux, clk_src);
CLOCK_SetDiv(kCLOCK_Sai2PreDiv, clk_pre_div);
CLOCK_SetDiv(kCLOCK_Sai2Div, clk_src_div);
break;
case IMX_CCM_SAI3_CLK:
CLOCK_SetMux(kCLOCK_Sai2Mux, clk_src);
CLOCK_SetDiv(kCLOCK_Sai2PreDiv, clk_pre_div);
CLOCK_SetDiv(kCLOCK_Sai2Div, clk_src_div);
break;
default:
return;
}
}
#endif
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
/**
*
* @brief Perform basic hardware initialization
*
* Initialize the interrupt controller device drivers.
* Also initialize the timer device driver, if required.
*
* @return 0
*/
init: remove the need for a dummy device pointer in SYS_INIT functions The init infrastructure, found in `init.h`, is currently used by: - `SYS_INIT`: to call functions before `main` - `DEVICE_*`: to initialize devices They are all sorted according to an initialization level + a priority. `SYS_INIT` calls are really orthogonal to devices, however, the required function signature requires a `const struct device *dev` as a first argument. The only reason for that is because the same init machinery is used by devices, so we have something like: ```c struct init_entry { int (*init)(const struct device *dev); /* only set by DEVICE_*, otherwise NULL */ const struct device *dev; } ``` As a result, we end up with such weird/ugly pattern: ```c static int my_init(const struct device *dev) { /* always NULL! add ARG_UNUSED to avoid compiler warning */ ARG_UNUSED(dev); ... } ``` This is really a result of poor internals isolation. This patch proposes a to make init entries more flexible so that they can accept sytem initialization calls like this: ```c static int my_init(void) { ... } ``` This is achieved using a union: ```c union init_function { /* for SYS_INIT, used when init_entry.dev == NULL */ int (*sys)(void); /* for DEVICE*, used when init_entry.dev != NULL */ int (*dev)(const struct device *dev); }; struct init_entry { /* stores init function (either for SYS_INIT or DEVICE*) union init_function init_fn; /* stores device pointer for DEVICE*, NULL for SYS_INIT. Allows * to know which union entry to call. */ const struct device *dev; } ``` This solution **does not increase ROM usage**, and allows to offer clean public APIs for both SYS_INIT and DEVICE*. Note that however, init machinery keeps a coupling with devices. **NOTE**: This is a breaking change! All `SYS_INIT` functions will need to be converted to the new signature. See the script offered in the following commit. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no> init: convert SYS_INIT functions to the new signature Conversion scripted using scripts/utils/migrate_sys_init.py. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no> manifest: update projects for SYS_INIT changes Update modules with updated SYS_INIT calls: - hal_ti - lvgl - sof - TraceRecorderSource Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no> tests: devicetree: devices: adjust test Adjust test according to the recently introduced SYS_INIT infrastructure. Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no> tests: kernel: threads: adjust SYS_INIT call Adjust to the new signature: int (*init_fn)(void); Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-10-19 09:33:44 +02:00
static int imxrt_init(void)
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
{
soc: arm: replace redundant config option for caches for nxp_imx Replace the redundant cache config options for the nxp_imx and use sys_cache* functions to enable the caches. These will automatically consider CONFIG_CACHE_MANAGEMENT. Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
2023-12-18 10:41:25 +01:00
sys_cache_instr_enable();
sys_cache_data_enable();
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
mimxrt1050: remove app specific code from soc file - Remove clock gating code to be compatible with A1 silicon - Remove PLL deinitialization code out of soc file Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2018-05-15 03:06:14 -08:00
/* Initialize system clock */
arm: arch code naming cleanup This patch re-namespaces global variables and functions that are used only within the arch/arm/ code to be prefixed with z_arm_. Some instances of CamelCase have been corrected. Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
2019-09-30 12:31:07 -07:00
clock_init();
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
return 0;
}
soc: enable noncacheable OCRAM region for nxp iMX.RT OCRAM can be used for DMA, and in this case it should be marked as noncacheable. Add KConfig symbol and appropriate linker scripts to enable OCRAM region to be defined as noncacheable, and initialized with data from flash at boot. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-03-16 12:14:00 -05:00
#ifdef CONFIG_PLATFORM_SPECIFIC_INIT
void z_arm_platform_init(void)
{
soc: arm: imx_rt10xx: call CMSIS SystemInit at early boot Call CMSIS SystemInit at early platform boot, to ensure that registers are configured correctly on RT10xx series. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-11-07 17:26:44 -06:00
/* Call CMSIS SystemInit */
SystemInit();
soc: nxp: rt1xxx: Enable NXP FlexRAM Enable NXP FlexRAM in DTS and SOC code. Do not configure flexram at runtime if the code is in the RAM. Fix RT1060 DT to be more accurate. Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2023-09-14 19:40:17 -05:00
#if defined(FLEXRAM_RUNTIME_BANKS_USED)
/* Configure flexram if not running from RAM */
memc_flexram_dt_partition();
#endif
soc: enable noncacheable OCRAM region for nxp iMX.RT OCRAM can be used for DMA, and in this case it should be marked as noncacheable. Add KConfig symbol and appropriate linker scripts to enable OCRAM region to be defined as noncacheable, and initialized with data from flash at boot. Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-03-16 12:14:00 -05:00
}
#endif
arm: Introduce NXP i.MX family, RT series, and mimxrt1052 SoC Adds the mimxrt1052 SoC, which belongs to a new family (nxp_imx) and series (rt) of SoCs. The mimxrt1052 integrates an Arm Cortex-M7 core, 512 KB TCM, and many peripherals including 2D graphics, an LCD display controller, camera interface, SPDIF and I2S. Unlike other SoCs in Zephyr, the mimxrt1052 has no internal flash. This initial port to mimxrt1052 configures the system clock to operate at 528 MHz, and enables the serial/uart and gpio interfaces to support the hello_world and blinky samples. Support for additional Zephyr driver interfaces will come later. Signed-off-by: Maureen Helm <maureen.helm@nxp.com>
2017-08-11 14:42:40 -05:00
SYS_INIT(imxrt_init, PRE_KERNEL_1, 0);
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