Commit graph

35 commits

Author SHA1 Message Date
Benedikt Schmidt
d992683db5 soc: arm: replace redundant config option for caches for nxp_imx
Replace the redundant cache config options for the nxp_imx and
use sys_cache* functions to enable the caches. These will automatically
consider CONFIG_CACHE_MANAGEMENT.

Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
2024-01-10 09:59:58 +01:00
Declan Snyder
0e935ea180 soc: rt10xx: enable phy clock with new driver
when using either old or new driver for nxp enet,
enable the phy clock

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2023-11-28 14:34:02 -06:00
Declan Snyder
2d1fdb5586 soc: nxp: rt1xxx: Enable NXP FlexRAM
Enable NXP FlexRAM in DTS and SOC code.

Do not configure flexram at runtime if the code is in the RAM.

Fix RT1060 DT to be more accurate.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2023-11-13 09:42:28 +01:00
Daniel DeGrasse
905512438e soc: arm: nxp_imx: update iMX RT boot header to handle CONFIG_XIP=n
Update iMX RT boot header to support CONFIG_XIP=n, when the image is not
linked into the flash space. Also, update the boot header to correctly
calculate the flash used size within the boot data header. This field is
used by the iMX boot ROM to determine how much data to copy when running
from RAM, so using the correct size fixes an issue where the ROM would
copy more data than needed.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-08-24 22:09:01 +01:00
Gerard Marull-Paretas
9c961571a2 modules: cmsis: move glue code to modules/cmsis
The CMSIS module glue code was part of arch/ directory. Move it to
modules/cmsis, and provide a single entry point for it: cmsis_core.h.
This entry header will include the right CMSIS header (M or A/R).

To make this change possible, CMSIS module Kconfig/CMake are declared as
external, allowing us to add a new Zephyr include directory.

All files including CMSIS have been updated.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-08-24 13:20:21 +02:00
Benjamin Lemouzy
35849319e0 soc: arm: imx_rt10xx: support enet1 external clock
Configure ENET_REF_CLK direction as input when
CONFIG_ETH_MCUX_RMII_EXT_CLK is set to allow Ethernet external clock
usage.

Signed-off-by: Benjamin Lemouzy <blemouzy@centralp.fr>
2023-08-14 08:21:26 -05:00
Daniel DeGrasse
c3dfc2220a soc: arm: nxp_imx: rt: Remove CONFIG_OCRAM_NOCACHE setting
Remove CONFIG_OCRAM_NOCACHE setting, as this is now possible to achieve
using devicetree linker regions, and there is no point in having a
specific Kconfig for one memory region on the RT series like this.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-08-04 16:11:37 -05:00
Gerard Marull-Paretas
fcaa259e22 soc: arm: remove all unnecessary NMI_INIT() calls
NMI_INIT() is now a no-op, so remove it from all SoC code. Also remove
the irq lock/unlock pattern as it was likely a cause of copy&paste when
NMI_INIT() was called.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-07-05 09:15:36 +02:00
Sumit Batra
0ae7010946 soc: rt10xx: fix the sequence of Enet2 ref clk enablement
This patch sets ENET2 ref clock to be generated by External OSC

ENET2 ref clock direction as output

ENET2 ref clk frequency to 50MHz

Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
2023-07-03 15:24:00 -05:00
Sumit Batra
7dce14632d soc: arm: nxp_imx: support enet2 interface on RT106x series
This patch enables the PLL clock output and PLL ref clock
for second ethernet module in NXP's i.MxRT106x SoCs

Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
2023-05-18 14:08:06 -05:00
Daniel DeGrasse
746758d1f6 drivers: display: update MCUX ELCDIF driver to use new lcdif binding
Update MCUX ELCDIF driver to use new LCDIF bindings. This
update also adds support for configuring the root clock of
the ELCDIF module based on the pixel-clock property to the
RT11xx SOC clock init, as this SOC series has this IP block

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-05-11 10:04:24 +02:00
Jan Peters
b9235faf22 soc: arm: imx_rt10xx: enable code cache during boot
For certain combinations of configuration parameters,
z_arm_init_arch_hw_at_boot() disables the instruction cache. Make sure
to re-enable it if required.

Signed-off-by: Jan Peters <peters@kt-elektronik.de>
2023-05-04 10:47:23 +02:00
Gerard Marull-Paretas
a5fd0d184a init: remove the need for a dummy device pointer in SYS_INIT functions
The init infrastructure, found in `init.h`, is currently used by:

- `SYS_INIT`: to call functions before `main`
- `DEVICE_*`: to initialize devices

They are all sorted according to an initialization level + a priority.
`SYS_INIT` calls are really orthogonal to devices, however, the required
function signature requires a `const struct device *dev` as a first
argument. The only reason for that is because the same init machinery is
used by devices, so we have something like:

```c
struct init_entry {
	int (*init)(const struct device *dev);
	/* only set by DEVICE_*, otherwise NULL */
	const struct device *dev;
}
```

As a result, we end up with such weird/ugly pattern:

```c
static int my_init(const struct device *dev)
{
	/* always NULL! add ARG_UNUSED to avoid compiler warning */
	ARG_UNUSED(dev);
	...
}
```

This is really a result of poor internals isolation. This patch proposes
a to make init entries more flexible so that they can accept sytem
initialization calls like this:

```c
static int my_init(void)
{
	...
}
```

This is achieved using a union:

```c
union init_function {
	/* for SYS_INIT, used when init_entry.dev == NULL */
	int (*sys)(void);
	/* for DEVICE*, used when init_entry.dev != NULL */
	int (*dev)(const struct device *dev);
};

struct init_entry {
	/* stores init function (either for SYS_INIT or DEVICE*)
	union init_function init_fn;
	/* stores device pointer for DEVICE*, NULL for SYS_INIT. Allows
	 * to know which union entry to call.
	 */
	const struct device *dev;
}
```

This solution **does not increase ROM usage**, and allows to offer clean
public APIs for both SYS_INIT and DEVICE*. Note that however, init
machinery keeps a coupling with devices.

**NOTE**: This is a breaking change! All `SYS_INIT` functions will need
to be converted to the new signature. See the script offered in the
following commit.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

init: convert SYS_INIT functions to the new signature

Conversion scripted using scripts/utils/migrate_sys_init.py.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

manifest: update projects for SYS_INIT changes

Update modules with updated SYS_INIT calls:

- hal_ti
- lvgl
- sof
- TraceRecorderSource

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

tests: devicetree: devices: adjust test

Adjust test according to the recently introduced SYS_INIT
infrastructure.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>

tests: kernel: threads: adjust SYS_INIT call

Adjust to the new signature: int (*init_fn)(void);

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-04-12 14:28:07 +00:00
Daniel DeGrasse
24b66b30eb soc: arm: nxp_imx: use CMSIS SystemInit for all NXP iMX.RT SOCs
Use CMSIS SystemInit for all NXP iMX.RT SOCs, to simplify initialization
flow, and remove redundant code where possible.

Introduce Kconfigs to disable Cache at boot, since SystemInit will enable
code cache on these platforms, which may be undesirable behavior.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-02-20 09:47:28 +01:00
Daniel DeGrasse
1ed776a218 soc: arm: imx_rt10xx: call CMSIS SystemInit at early boot
Call CMSIS SystemInit at early platform boot, to ensure that registers
are configured correctly on RT10xx series.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-11-17 11:53:42 -06:00
Daniel DeGrasse
b53eaf1f24 soc: nxp_imx: include fsl_flexspi_nor_boot when boot header is present
Only include fsl_flexspi_nor_boot when a boot header is present,
as this is the only case where the boot header data will be required.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-11-10 09:11:08 -06:00
Marcin Niestroj
adfc705b51 ARM: nxp_imx: rt10xx: migrate ARM, AHB and IPG dividers to DT
Those dividers were configured in Kconfig so far. Add 'arm-podf',
'ahb-podf' and 'ipg-podf' "fixed-factor-clock" compatible DT child nodes
under 'ccm' (Clock Control Module) and use configured 'clock-div' values
instead of Kconfig equivalents.

Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
2022-11-02 17:17:27 -05:00
Mahesh Mahadevan
9966181510 drivers: usb: mcux: Restructure driver for SDK updates
1. Move the defines from usb_dc_mcux.h to usb_device_config.h
   and fsl_os_abstraction.h. These headers are used by
   the SDK USB driver. usb_dc_mcux.h header file is not longer
   needed and hence deleted.
2. Delete the Zephyr implementation of the usb_device_struct
   driver and use the one implemented inside the SDK USB
   driver. This requires updating the references to
   usb_device_struct inside the USB driver
3. Move defines and structures used by the driver
   out of the header file that is included by the SDK and
   into the MCUX USB driver.
4. Use end point defines provided by Zephyr instead of adding
   them locally.
5. Add a Kconfig to set the thread stack size
6. Move code to enable interrupts back to usb_attach function.
   Interrupts should be enabled after the init is successful,
   else we see errors of the ISR getting called before the
   init is complete causing Faults
6. Update west.yml to update the NXP HAL to get the updated
   SDK USB driver.

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-09-09 09:44:46 -05:00
Marcin Niestroj
356960bcb5 ARM: nxp_imx: rt10xx: add XTAL and RTC_XTAL DT clocks
There are two external clocks driving i.MX RT 10xx SoCs: XTAL and
RTC_XTAL. Add "fixed-clock" DT nodes for each. Update also "nxp,imx-ccm"
binding, so that CCM (Clock Control Module) peripheral consumes those
clocks by "xtal" and "rtc-xtal" names.

Signed-off-by: Marcin Niestroj <m.niestroj@emb.dev>
2022-09-01 08:11:50 -05:00
Daniel DeGrasse
69d153cd3d soc: nxp_imx: rt: enable SWO output for iMX RT 10xx series
enable swo output for iMX RT 10xx series. SWO pinmux settings are
currently only present for the RT1060 and RT1064

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-06-28 16:02:09 -05:00
Gerard Marull-Paretas
0e69129fb3 soc: migrate includes to <zephyr/...>
In order to bring consistency in-tree, migrate all soc code to the
new prefix <zephyr/...>. Note that the conversion has been scripted,
refer to zephyrproject-rtos#45388 for more details.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2022-05-06 19:57:59 +02:00
Daniel DeGrasse
32cd207f95 boards: mimxrt1064: Enabled new SDHC driver
Enabled new SDHC driver for mimxrt1064 evk

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-04-29 14:21:36 -05:00
Daniel DeGrasse
8c115a26e0 soc: nxp_imx: rt: remove unnecessary pinmux callbacks
All iMX RT 1xxx boards are now expected to use pin control, so the USDHC
pinmuxing callbacks can be removed.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-03-25 15:47:54 -05:00
Daniel DeGrasse
8fd1b54a82 soc: nxp_imx: rt: enable ethernet ref clock output
Enable soc ethernet ref clock output at the SOC level instead of board
level, since it is required for all iMX.RT SOCs

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-03-25 15:47:54 -05:00
Daniel DeGrasse
da40ffb4a8 soc: enable noncacheable OCRAM region for nxp iMX.RT
OCRAM can be used for DMA, and in this case it should be marked as
noncacheable. Add KConfig symbol and appropriate linker scripts to
enable OCRAM region to be defined as noncacheable, and initialized with
data from flash at boot.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-03-25 10:40:59 +01:00
Daniel DeGrasse
8b7f23da28 soc: rt10xx: Enable USB2 controller clock
Enable USB2 controller clock on RT10xx SOC init, if nodelabel has
status="okay"

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-03-11 14:50:11 -08:00
Daniel DeGrasse
5dfd3c3786 soc: rt10xx: Set divisor for sys pll (PLL2) PFD0
Divisor must be set to calculate SD host controller clock frequency in
clock driver.

Fixes #42380

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2022-02-02 16:59:30 +01:00
Hake Huang
496dd79fdb soc: rt1xxx: fix build errors
remove LOG_ERR in soc init

fixing: #42179

Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2022-01-28 10:06:53 +01:00
Hake Huang
de3518157c soc: nxp_rt: sai clock header include
add sai clock source name define header
update the clock marco for sai

fixing: #42179

Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2022-01-28 10:06:53 +01:00
Hake Huang
a59e994322 soc: add auido clock init per soc
RT11xx and RT10xx have different audio clock settings
so add them in soc.c

Signed-off-by: Hake Huang <hake.huang@oss.nxp.com>
2022-01-21 11:26:45 -06:00
Mahesh Mahadevan
6f23f55e4b soc: mxrt10xx: Update the clock init code
1. Setup VDD_SOC with the appropriate setting
   depending on the SoC
2. Do not configure PLL_SYS and PLL_USB. These
   are already configured by the ROM code using
   the DCD
3. Fix setting for USDHC clock

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2022-01-21 08:36:09 -06:00
Daniel Leung
aa20e081d2 arm: remove @return doc for void functions
For functions returning nothing, there is no need to document
with @return, as Doxgen complains about "documented empty
return type of ...".

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2022-01-12 16:02:16 -05:00
Daniel DeGrasse
57f35bbf5a drivers: USDHC: Enable detection using DAT3 pulldown
Enable USDHC host to detect inserted SD card via DAT3 line pulldown.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2021-12-06 15:27:25 -05:00
Mahesh Mahadevan
f18d51073b soc: rt: Update USB config and device tree node names
The USB config name has changed to USB_MCUX and the
device tree node name has changed from nxp_kinetis_usbd
to nxp_mcux_usbd

Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
2021-08-19 17:19:11 -04:00
Ryan QIAN
431345ae79 soc: arm: nxp_imx: add rt117x support
1. Added RT10xx and RT11xx configs
2. Added a new soc file for rt117x. There are clock differences
   between the RT10xx and RT11xx series, hence the soc files
   have been separated.

Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
2021-06-29 11:30:00 -04:00
Renamed from soc/arm/nxp_imx/rt/soc.c (Browse further)