arch: arm: nxp: imxrt1021: add device support

- Add Soc information for RT1020

Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>

soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1021

@@ -0,0 +1,47 @@
+# Kconfig - i.MX RT1021
+#
+# Copyright (c) 2018, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_MIMXRT1021
+
+config SOC
+	string
+	default "mimxrt1021"
+
+if CLOCK_CONTROL
+
+config CLOCK_CONTROL_MCUX_CCM
+	default y
+
+endif # CLOCK_CONTROL
+
+config ARM_DIV
+	default 0
+
+config AHB_DIV
+	default 0
+
+config IPG_DIV
+	default 3
+
+config GPIO
+	default y
+
+if GPIO
+
+config GPIO_MCUX_IGPIO
+	default y
+
+endif # GPIO
+
+if SERIAL
+
+config UART_MCUX_LPUART
+	default y
+
+endif # SERIAL
+
+endif # SOC_MIMXRT1021

soc/arm/nxp_imx/rt/Kconfig.soc

@@ -9,6 +9,19 @@ choice
 prompt "i.MX RT Selection"
 depends on SOC_SERIES_IMX_RT
 
+config SOC_MIMXRT1021
+	bool "SOC_MIMXRT1021"
+	select HAS_MCUX
+	select HAS_MCUX_CCM
+	select HAS_MCUX_IGPIO
+	select HAS_MCUX_LPSPI
+	select HAS_MCUX_LPUART
+	select CPU_HAS_FPU
+	select CPU_HAS_ARM_MPU
+	select INIT_SYS_PLL
+	select INIT_USB1_PLL
+	select INIT_ENET_PLL
+
 config SOC_MIMXRT1051
 	bool "SOC_MIMXRT1051"
 	select HAS_MCUX
@@ -63,6 +76,18 @@ endchoice
 
 if SOC_SERIES_IMX_RT
 
+config SOC_PART_NUMBER_MIMXRT1021CAG4A
+	bool
+
+config SOC_PART_NUMBER_MIMXRT1021CAF4A
+	bool
+
+config SOC_PART_NUMBER_MIMXRT1021DAG5A
+	bool
+
+config SOC_PART_NUMBER_MIMXRT1021DAF5A
+	bool
+
 config SOC_PART_NUMBER_MIMXRT1051CVL5A
 	bool
 
@@ -89,6 +114,10 @@ config SOC_PART_NUMBER_MIMXRT1062DVL6A
 
 config SOC_PART_NUMBER_IMX_RT
 	string
+	default "MIMXRT1021CAG4A" if SOC_PART_NUMBER_MIMXRT1021CAG4A
+	default "MIMXRT1021CAF4A" if SOC_PART_NUMBER_MIMXRT1021CAF4A
+	default "MIMXRT1021DAG5A" if SOC_PART_NUMBER_MIMXRT1021DAG5A
+	default "MIMXRT1021DAF5A" if SOC_PART_NUMBER_MIMXRT1021DAF5A
 	default "MIMXRT1051CVL5A" if SOC_PART_NUMBER_MIMXRT1051CVL5A
 	default "MIMXRT1051DVL6A" if SOC_PART_NUMBER_MIMXRT1051DVL6A
 	default "MIMXRT1052CVL5A" if SOC_PART_NUMBER_MIMXRT1052CVL5A

soc/arm/nxp_imx/rt/soc.c

@@ -37,7 +37,11 @@ const clock_usb_pll_config_t usb1PllConfig = {
 #ifdef CONFIG_INIT_ENET_PLL
 /* ENET PLL configuration for RUN mode */
 const clock_enet_pll_config_t ethPllConfig = {
+#ifdef CONFIG_SOC_MIMXRT1021
+	.enableClkOutput500M = true,
+#else
 	.enableClkOutput = true,
+#endif
 	.enableClkOutput25M = false,
 	.loopDivider = 1,
 };