michaelh/zephyr
1
0
Fork 0
Code Releases Activity

boards: mimxrt1050_evk: add condition to initialize different PLL

Browse source 
- add conditions to initialize different PLL

Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
This commit is contained in:
Ryan QIAN 2018-05-14 07:45:32 +08:00 • committed by Maureen Helm
commit 3fd25c64c7
3 changed files with 48 additions and 3 deletions
Download patch file Download diff file Expand all files Collapse all files

12
arch/arm/soc/nxp_imx/rt/Kconfig.defconfig.mimxrt1052
View file

@ -10,6 +10,9 @@ if SOC_MIMXRT1052
config SOC
string
default "mimxrt1052"
select INIT_ARM_PLL
select INIT_SYS_PLL
select INIT_USB1_PLL
if CLOCK_CONTROL
@ -18,6 +21,15 @@ config CLOCK_CONTROL_MCUX_CCM
endif # CLOCK_CONTROL
config ARM_DIV
default 1
config AHB_DIV
default 0
config IPG_DIV
default 3
config GPIO
def_bool y

21
arch/arm/soc/nxp_imx/rt/Kconfig.soc
View file

@ -62,4 +62,25 @@ config SOC_PART_NUMBER_IMX_RT
that you should not set directly. The part number selection choice defines
the default value for this string.
config INIT_ARM_PLL
bool "Initialize ARM PLL"
config INIT_SYS_PLL
bool "Initialize SYS PLL"
config INIT_USB1_PLL
bool "Initialize USB1 PLL"
config ARM_DIV
int "ARM clock divider"
range 0 7
config AHB_DIV
int "AHB clock divider"
range 0 7
config IPG_DIV
int "IPG clock divider"
range 0 3
endif # SOC_SERIES_IMX_RT

18
arch/arm/soc/nxp_imx/rt/soc.c
View file

@ -13,20 +13,26 @@
#include <arch/cpu.h>
#include <cortex_m/exc.h>
#ifdef CONFIG_INIT_ARM_PLL
/* ARM PLL configuration for RUN mode */
const clock_arm_pll_config_t armPllConfig = {
.loopDivider = 100U
};
#endif
#ifdef CONFIG_INIT_SYS_PLL
/* SYS PLL configuration for RUN mode */
const clock_sys_pll_config_t sysPllConfig = {
.loopDivider = 1U
};
#endif
#ifdef CONFIG_INIT_USB1_PLL
/* USB1 PLL configuration for RUN mode */
const clock_usb_pll_config_t usb1PllConfig = {
.loopDivider = 0U
};
#endif
/**
*
@ -53,13 +59,19 @@ static ALWAYS_INLINE void clkInit(void)
*/
DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
#ifdef CONFIG_INIT_ARM_PLL
CLOCK_InitArmPll(&armPllConfig); /* Configure ARM PLL to 1200M */
#endif
#ifdef CONFIG_INIT_SYS_PLL
CLOCK_InitSysPll(&sysPllConfig); /* Configure SYS PLL to 528M */
#endif
#ifdef CONFIG_INIT_USB1_PLL
CLOCK_InitUsb1Pll(&usb1PllConfig); /* Configure USB1 PLL to 480M */
#endif
CLOCK_SetDiv(kCLOCK_ArmDiv, 0x1); /* Set ARM PODF to 0, divide by 2 */
CLOCK_SetDiv(kCLOCK_AhbDiv, 0x0); /* Set AHB PODF to 0, divide by 1 */
CLOCK_SetDiv(kCLOCK_IpgDiv, 0x3); /* Set IPG PODF to 3, divide by 4 */
CLOCK_SetDiv(kCLOCK_ArmDiv, CONFIG_ARM_DIV); /* Set ARM PODF */
CLOCK_SetDiv(kCLOCK_AhbDiv, CONFIG_AHB_DIV); /* Set AHB PODF */
CLOCK_SetDiv(kCLOCK_IpgDiv, CONFIG_IPG_DIV); /* Set IPG PODF */
/* Set PRE_PERIPH_CLK to PLL1, 1200M */
CLOCK_SetMux(kCLOCK_PrePeriphMux, 0x3);