boards: mimxrt1050_evk: add condition to initialize different PLL
- add conditions to initialize different PLL Signed-off-by: Ryan QIAN <jianghao.qian@nxp.com>
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b2522d44cb
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3 changed files with 48 additions and 3 deletions
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@ -10,6 +10,9 @@ if SOC_MIMXRT1052
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config SOC
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string
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default "mimxrt1052"
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select INIT_ARM_PLL
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select INIT_SYS_PLL
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select INIT_USB1_PLL
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if CLOCK_CONTROL
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@ -18,6 +21,15 @@ config CLOCK_CONTROL_MCUX_CCM
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endif # CLOCK_CONTROL
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config ARM_DIV
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default 1
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config AHB_DIV
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default 0
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config IPG_DIV
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default 3
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config GPIO
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def_bool y
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@ -62,4 +62,25 @@ config SOC_PART_NUMBER_IMX_RT
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that you should not set directly. The part number selection choice defines
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the default value for this string.
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config INIT_ARM_PLL
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bool "Initialize ARM PLL"
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config INIT_SYS_PLL
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bool "Initialize SYS PLL"
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config INIT_USB1_PLL
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bool "Initialize USB1 PLL"
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config ARM_DIV
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int "ARM clock divider"
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range 0 7
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config AHB_DIV
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int "AHB clock divider"
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range 0 7
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config IPG_DIV
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int "IPG clock divider"
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range 0 3
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endif # SOC_SERIES_IMX_RT
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@ -13,20 +13,26 @@
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#include <arch/cpu.h>
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#include <cortex_m/exc.h>
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#ifdef CONFIG_INIT_ARM_PLL
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/* ARM PLL configuration for RUN mode */
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const clock_arm_pll_config_t armPllConfig = {
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.loopDivider = 100U
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};
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#endif
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#ifdef CONFIG_INIT_SYS_PLL
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/* SYS PLL configuration for RUN mode */
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const clock_sys_pll_config_t sysPllConfig = {
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.loopDivider = 1U
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};
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#endif
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#ifdef CONFIG_INIT_USB1_PLL
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/* USB1 PLL configuration for RUN mode */
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const clock_usb_pll_config_t usb1PllConfig = {
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.loopDivider = 0U
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};
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#endif
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/**
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*
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@ -53,13 +59,19 @@ static ALWAYS_INLINE void clkInit(void)
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*/
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DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
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#ifdef CONFIG_INIT_ARM_PLL
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CLOCK_InitArmPll(&armPllConfig); /* Configure ARM PLL to 1200M */
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#endif
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#ifdef CONFIG_INIT_SYS_PLL
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CLOCK_InitSysPll(&sysPllConfig); /* Configure SYS PLL to 528M */
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#endif
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#ifdef CONFIG_INIT_USB1_PLL
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CLOCK_InitUsb1Pll(&usb1PllConfig); /* Configure USB1 PLL to 480M */
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#endif
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CLOCK_SetDiv(kCLOCK_ArmDiv, 0x1); /* Set ARM PODF to 0, divide by 2 */
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CLOCK_SetDiv(kCLOCK_AhbDiv, 0x0); /* Set AHB PODF to 0, divide by 1 */
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CLOCK_SetDiv(kCLOCK_IpgDiv, 0x3); /* Set IPG PODF to 3, divide by 4 */
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CLOCK_SetDiv(kCLOCK_ArmDiv, CONFIG_ARM_DIV); /* Set ARM PODF */
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CLOCK_SetDiv(kCLOCK_AhbDiv, CONFIG_AHB_DIV); /* Set AHB PODF */
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CLOCK_SetDiv(kCLOCK_IpgDiv, CONFIG_IPG_DIV); /* Set IPG PODF */
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/* Set PRE_PERIPH_CLK to PLL1, 1200M */
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CLOCK_SetMux(kCLOCK_PrePeriphMux, 0x3);
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