soc: nxp_imx: Add support for external xip flash boot header

Adds support for the boot data, image vector table, and FlexSPI NOR
config structures used by the imx rt boot ROM to boot an application
from an external xip flash device.

It is now possible to build and flash a bootable zephyr image to the
external xip flash on the mimxrt1020_evk, mimxrt1050_evk, and
mimxrt1060_evk boards via the 'ninja flash' build target and jlink
runner. Note, however, that the default board configurations still link
code into internal ITCM, therefore you must set CONFIG_CODE_HYPERFLASH=y
or CONFIG_CODE_QSPI=y explicitly to override the default. You must also
set CONFIG_NXP_IMX_RT_BOOT_HEADER=y to build the boot header into the
image.

Signed-off-by: Maureen Helm <maureen.helm@nxp.com>

ext/hal/nxp/mcux/CMakeLists.txt

@@ -28,6 +28,7 @@ zephyr_compile_definitions(${MCUX_CPU})
 zephyr_sources(devices/${MCUX_DEVICE}/fsl_clock.c)
 
 # Build mcux drivers that can be used for multiple SoC's.
+add_subdirectory(boards)
 add_subdirectory(components)
 add_subdirectory(drivers)
 

ext/hal/nxp/mcux/boards/CMakeLists.txt

@@ -0,0 +1,9 @@
+#
+# Copyright (c) 2018, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+add_subdirectory_ifdef(CONFIG_BOARD_MIMXRT1020_EVK evkmimxrt1020)
+add_subdirectory_ifdef(CONFIG_BOARD_MIMXRT1050_EVK evkbimxrt1050)
+add_subdirectory_ifdef(CONFIG_BOARD_MIMXRT1060_EVK evkmimxrt1060)

ext/hal/nxp/mcux/boards/evkbimxrt1050/CMakeLists.txt

@@ -0,0 +1,9 @@
+#
+# Copyright (c) 2018, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_compile_definitions_ifdef(CONFIG_NXP_IMX_RT_BOOT_HEADER XIP_BOOT_HEADER_ENABLE=1)
+
+zephyr_sources_ifdef(CONFIG_BOOT_FLEXSPI_NOR evkbimxrt1050_flexspi_nor_config.c)

ext/hal/nxp/mcux/boards/evkmimxrt1020/CMakeLists.txt

@@ -0,0 +1,9 @@
+#
+# Copyright (c) 2018, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_compile_definitions_ifdef(CONFIG_NXP_IMX_RT_BOOT_HEADER XIP_BOOT_HEADER_ENABLE=1)
+
+zephyr_sources_ifdef(CONFIG_BOOT_FLEXSPI_NOR evkmimxrt1020_flexspi_nor_config.c)

ext/hal/nxp/mcux/boards/evkmimxrt1060/CMakeLists.txt

@@ -0,0 +1,9 @@
+#
+# Copyright (c) 2018, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_compile_definitions_ifdef(CONFIG_NXP_IMX_RT_BOOT_HEADER XIP_BOOT_HEADER_ENABLE=1)
+
+zephyr_sources_ifdef(CONFIG_BOOT_FLEXSPI_NOR evkmimxrt1060_flexspi_nor_config.c)

ext/hal/nxp/mcux/drivers/imx/fsl_flexspi_nor_boot.h

@@ -9,7 +9,6 @@
 #define __FLEXSPI_NOR_BOOT_H__
 
 #include <stdint.h>
-#include "board.h"
 
 /*! @name Driver version */
 /*@{*/

include/arch/arm/cortex_m/scripts/linker.ld

@@ -135,6 +135,14 @@ SECTIONS
 	KEEP(*(.dbghdr))
 	KEEP(*(".dbghdr.*"))
 #endif
+
+#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER
+	KEEP(*(.boot_hdr.conf))
+	. = CONFIG_IMAGE_VECTOR_TABLE_OFFSET;
+	KEEP(*(.boot_hdr.ivt))
+	KEEP(*(.boot_hdr.data))
+#endif
+
 	. = CONFIG_TEXT_SECTION_OFFSET;
 
 #if defined(CONFIG_SW_VECTOR_RELAY)

include/linker/section_tags.h

@@ -23,6 +23,9 @@
 #define __ccm_data_section _GENERIC_SECTION(_CCM_DATA_SECTION_NAME)
 #define __ccm_bss_section _GENERIC_SECTION(_CCM_BSS_SECTION_NAME)
 #define __ccm_noinit_section _GENERIC_SECTION(_CCM_NOINIT_SECTION_NAME)
+#define __imx_boot_conf_section	_GENERIC_SECTION(IMX_BOOT_CONF)
+#define __imx_boot_data_section	_GENERIC_SECTION(IMX_BOOT_DATA)
+#define __imx_boot_ivt_section	_GENERIC_SECTION(IMX_BOOT_IVT)
 #endif /* CONFIG_ARM */
 
 #if defined(CONFIG_NOCACHE_MEMORY)

include/linker/sections.h

@@ -58,6 +58,10 @@
 #define _CCM_NOINIT_SECTION_NAME	.ccm_noinit
 #endif
 
+#define IMX_BOOT_CONF	.boot_hdr.conf
+#define IMX_BOOT_DATA	.boot_hdr.data
+#define IMX_BOOT_IVT	.boot_hdr.ivt
+
 #ifdef CONFIG_NOCACHE_MEMORY
 #define _NOCACHE_SECTION_NAME nocache
 #endif

soc/arm/nxp_imx/rt/Kconfig.soc

@@ -152,4 +152,41 @@ config IPG_DIV
 	int "IPG clock divider"
 	range 0 3
 
+menuconfig NXP_IMX_RT_BOOT_HEADER
+	bool "Enable the boot header"
+	help
+	  Enable data structures required by the boot ROM to boot the
+	  application from an external flash device.
+
+if NXP_IMX_RT_BOOT_HEADER
+
+choice BOOT_DEVICE
+	prompt "Boot device selection"
+	default BOOT_FLEXSPI_NOR
+
+config BOOT_FLEXSPI_NOR
+	bool "FlexSPI serial NOR"
+
+config BOOT_FLEXSPI_NAND
+	bool "FlexSPI serial NAND"
+
+config BOOT_SEMC_NOR
+	bool "SEMC parallel NOR"
+
+config BOOT_SEMC_NAND
+	bool "SEMC parallel NAND"
+
+endchoice
+
+config IMAGE_VECTOR_TABLE_OFFSET
+	hex "Image vector table offset"
+	default 0x1000 if BOOT_FLEXSPI_NOR || BOOT_SEMC_NOR
+	default 0x400 if BOOT_FLEXSPI_NAND || BOOT_SEMC_NAND
+	help
+	  The Image Vector Table (IVT) provides the boot ROM with pointers to
+	  the application entry point and device configuration data. The boot
+	  ROM reqiures a fixed IVT offset for each type of boot device.
+
+endif # NXP_IMX_RT_BOOT_HEADER
+
 endif # SOC_SERIES_IMX_RT

soc/arm/nxp_imx/rt/soc.c

@@ -12,6 +12,7 @@
 #include <fsl_clock.h>
 #include <arch/cpu.h>
 #include <cortex_m/exc.h>
+#include <fsl_flexspi_nor_boot.h>
 
 #ifdef CONFIG_INIT_ARM_PLL
 /* ARM PLL configuration for RUN mode */
@@ -47,6 +48,26 @@ const clock_enet_pll_config_t ethPllConfig = {
 };
 #endif
 
+#ifdef CONFIG_NXP_IMX_RT_BOOT_HEADER
+const __imx_boot_data_section BOOT_DATA_T boot_data = {
+	.start = CONFIG_FLASH_BASE_ADDRESS,
+	.size = CONFIG_FLASH_SIZE,
+	.plugin = PLUGIN_FLAG,
+	.placeholder = 0xFFFFFFFF,
+};
+
+const __imx_boot_ivt_section ivt image_vector_table = {
+	.hdr = IVT_HEADER,
+	.entry = CONFIG_FLASH_BASE_ADDRESS + CONFIG_TEXT_SECTION_OFFSET,
+	.reserved1 = IVT_RSVD,
+	.dcd = (uint32_t) NULL,
+	.boot_data = (uint32_t) &boot_data,
+	.self = (uint32_t) &image_vector_table,
+	.csf = (uint32_t)CSF_ADDRESS,
+	.reserved2 = IVT_RSVD,
+};
+#endif
+
 /**
  *
  * @brief Initialize the system clock