Fix for compiling i2s drivers on the NXP mimxrt1010_evk board.
For mimxrt1011, the defines kCLOCK_Sai2... are not defined as the sai2
peripheral does not exist. Trying to compile gives error. Fixed by adding
check for device tree node around code that uses the defines. Also added
same for sai1 and sai3. Thanks @lucien-nxp, @ZhaoxiangJin from NXP.
Signed-off-by: Imran Sajjad <imran.sajjad@iconfitness.com>
Don't force select INIT_SYS_PLL at SOC level. Instead use default y so
that board can unset it. Keep previous case where we would default y
which was only on RT1040. Also, this config is not used in RT1170 soc,
so move it to RT10xx series kconfig instead of family level. And it
appears to be on all the RT10xx, so ifdef is not needed.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Don't force select the INIT_VIDEO_PLL config so that board level can
unset it. Also clean up the code a bit in soc.c files.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The LDO config should not be forcefully selected at SOC level. Instead,
use soft default y so that board definition can unset it if desired.
Also, in the soc.c, the LDO code should be on both the rt1160 and
rt1170, so the definitions should exist, and ifdef is not needed. So can
switch to IS_ENABLED to decrease configuration complexity of the source
code.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The DCDC should be on all the platforms and the functions and structs
should therefore be defined on all the platforms. So the ifdef is not
needed, we can remove it to increase code compilation coverage unity
across configurations slightly. Compiler should optimize out the block
when IS_ENABLED is false statically.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Don't forcefully select this config in SOC level. Make it softer default
y so board can unselect it.
The config should not be possible if there is no arm pll, namely on
RT101x and RT102x. So add dependency clause about this.
And of course, code for this was a mess, clean up a bit.
Also remove the ifdeffry for selecting a default value for the two SOCs,
because they already put the same default value in the SOC Devicetree
DTSI, so that code had no purpose as long as a board didn't completely
redefine the SOC DT.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Initial motivation for this commit was to not force select
the INIT_ENET_PLL config from SOC level to allow for board level
configuration which might want it to be off.
While doing that, I discovered that RT11xx actually does not have
anything called by "ENET PLL" in the reference manual. So I have
removed the config for RT11xx. The default clock source for this soc.c
code for RT11xx is PLL1 DIV2, which I changed to just be configured if
ethernet is enabled, which was the reason to configure this pll as it
stands now, even though it is not specific to ethernet (although the
DIV2 output is mostly for ethernet). Another config is therefore not
needed.
For RT10xx, the situation is a lot more complicated. There is a lot of
discrepancy again between what is considered the "ENET PLL" both
conceptually and literally between the RM, SDK, and Zephyr config. And
also the code to define the config struct was a complete mess. So I have
simplified the code and changed it so that the config is only a soft
default to y instead of selected forcefully. Also, for the case of the
RT1010 and RT1020 series, the SDK is appearing to configure PLL6 (again
there is no clear ENET PLL meaning on these platforms) 500M output
through this "enet pll" configuration function. So similarly instead of
always enabling this output for those platforms, I added a new config
which can be set or unset by board level.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The original logic relied on the tick passed in. This method
is inaccurate as the tick value passed in was the exit latency.
Update the code to calculate the remaining time left and set
a counter using this value.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Several reason cause loopback test failed:
a) FlexIO input frequency is not correct, on RT11xx, input freq is 24M,
while max baud rate can reach 1/4 of input freq, so it can only support
6Mbps.
b) Flexio shift register depend on correct timer output to triggger TX
and RX, if timer comparison value is not accurate, RX error happens on
high baud rate. This is the reason why test fails on RT1060.
also fix a error on FlexIO clock ID calculation.
Signed-off-by: Raymond Lei <raymond.lei@nxp.com>
Use default value 0 if board DT doesn't define it.e
It's totally fine if the board device tree doen't define
load_capacitance_picofarads for the crystal oscillator. In that case,
just fallback to 0.
Signed-off-by: jens rudberg <jens@teenage.engineering>
The siwx91x need a specific firmware image format. These image end with
.rps extension. The current name of the image is zephyr.bin.rps. However,
the .bin suffix is not relevant. It makes even more sense if we consider
the output of west sign: zephyr.signed.bin.rps. We can simplify these name
by remove the .bin suffix.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Once the keys has been provisioned on the Silabs siwx91x, the chip expects
the firmware to be properly signed.
This PR automate the signing process. Hence, "west flash" will work as
expected.
Co-developed-by: Aasim Shaik <aasim.shaik@silabs.com>
Signed-off-by: Aasim Shaik <aasim.shaik@silabs.com>
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Silabs siwx91x support signed and encrypted firmwares. This PR includes
support for these features in "west sign"
Co-developed-by: Aasim Shaik <aasim.shaik@silabs.com>
Signed-off-by: Aasim Shaik <aasim.shaik@silabs.com>
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Disable generation of .hex output, since the Commander runner
prefers it over the .bin output but SiWx91x needs a .bin.rps file.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Co-developed-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Use runners_yaml_props_target to set the name of the file to
flash, rather than hard-coding it for each board.
Co-developed-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Floating-Point System ID register (FPSID) = 0x41033094
AArch32 Media and VFP Feature Register 0 (MVFR0) = 0x10110222
AArch32 Media and VFP Feature Register 0 (MVFR1) = 0x1111111
MVFR1 SIMDFMAC, bits [31:28] = 0; FMAC is not supported
Signed-off-by: Simon Maurer <mail@maurer.systems>
Enlarge NUM_IRQS by 32 which is the number of interrupts for
SGI (Software Generated Interrupts) and PPI (Private Peripheral
Interrupts).
Signed-off-by: Tony Han <tony.han@microchip.com>
Obtain the divisor value for generate the corresponding MCKx from the
register instead of from the variable to avoid wrong result caused by
un-synced division ratios.
Signed-off-by: Tony Han <tony.han@microchip.com>
Obtain generic clock division ratio from the register instead of
from the variable to avoid wrong result caused by un-synced
division ratios.
Signed-off-by: Tony Han <tony.han@microchip.com>
Adding supporting soc files for the k32lx platforms and updating
soc.yaml.
Signed-off-by: Ishraq Ibne Ashraf <ishraq.i.ashraf@gmail.com>
soc: nxp: kinetis: k32lx: Use device tree provided value
This clock frequency value will be defined in the board device tree.
Signed-off-by: Ishraq Ibne Ashraf <ishraq.i.ashraf@gmail.com>
CS hold time parameter is not correct which may cause bus fault
randomly.
System hang during status register reading after flash progromming which
is caused by parameter accessing in XIP mode.
Add dummy delay for READ command according the flash datasheet which is
required for SDR mode.
Use FlexSPI internal divider for clock updating instead of register in
CCM to avoid potential risk caused by flash access during clock updating
procedure.
Signed-off-by: Raymond Lei <raymond.lei@nxp.com>
Increase the number of HCI command transmit buffers on ESP32 to prevent
sporadic command timeouts. This is a temporary workaround.
Upcoming changes to the BLE proprietary blobs will address the root cause.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
List NEORV32 v1.11.6 as the currently supported version. No changes to the
in-tree drivers needed for the changes between v1.11.3 and v1.11.6.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Previously the clock was not attached to all Flexcomm ports. Some ports
were configured with FRO_12M, others with FRO_HF, some not at all.
Now every Flexcomm port in I2C, SPI or USART mode uses the FRO_HF clock,
if it is enabled in the device tree, to cover all use cases.
Signed-off-by: Fabian Otto <fabian.otto@rohde-schwarz.com>
This patch allows to link the request of the linklayer for a
temperature calibration to the temperature driver.
The linklayer will then adapt and trigger its calibration related to
the current temperature.
Signed-off-by: Romain Jayles <romain.jayles@st.com>
Add LINKLAYER_PLAT_EnableBackupDomainAccess() and
LINKLAYER_PLAT_DisableBackupDomainAccess() to use Zephyr resources
that use a reference counter for access requests, for enabling
and disabling access the BackupDomain resources.
Bump hal_stm32 module to the revision integrating related stm32wba
BLE updates.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Use recently added SoCs functions to request access to SoC backup
domain resources These function use a reference counter to track these
request and ensure the resources are accessible as long as at least a
consumer requires access.
Fixes issue 90942.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Add SoC functions to enable/disable STM32 backup Domain access
and use a reference counter to track requests. These helper functions
may be called from a interrupt context. On domain access enable, the
function loops until written bit is set however this is expected to be
effective after very few clock cycles and seems not even required
(not mentioned in any SoC documentation). The loop is preserved as
used in previous implementation.
Among all supported STM32 SoCs, only STM32C0 and STM32WB0 series do not
implement this mechanism hence add option CONFIG_STM32_BACKUP_PROTECTION
that is enabled for all SoC series but these 2.
Fixes issue 90942.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Fixes: commit 5f4b51f9b1 ("soc: intel_adsp: add a debug window slot
descriptor") - restore the maximum debug slot number. The added slot
resides in page 0, not at the end of the array. The bug didn't have
any run-time implications - no access to those high index value slots
is performed, all platforms so far have 3 slots at most, so this is a
pure correctness fix.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
