Fixed the include directive for mchp_pinctrl_pinmux_sam.h
by replacing quotes with angle brackets.
Signed-off-by: Arunprasath P <arunprasath.p@microchip.com>
- Update the path of pinctrl.h in sama7g54_ek.dts
- Select CONFIG_MICROCHIP_SAM for sama7g5 family devices
- Add SAM group Kconfig symbol for proper family grouping
- Rename PIC32C Kconfig symbol to MICROCHIP_PIC32C
and update references
- Update west.yml for hal-microchip re-organization
Signed-off-by: Arunprasath P <arunprasath.p@microchip.com>
The config PM_S2RAM_CUSTOM_MARKING is not an optional config for a
user to select, it is required by some soc implementations of S2RAM,
in which case it must be selected by the soc.
Refactor the configuration to be HAS_PM_S2RAM_CUSTOM_MARKING, and
make the currently only soc which needs it select it. Then update
samples which previously had to select this option for this soc.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Select ARM_ARCH_TIMER when RZ_OS_TIMER is not selected
Signed-off-by: Hoang Nguyen <hoang.nguyen.jx@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
This commit should deal with updating the re-configuration of the
I-cache controller when buidling for mcuboot. Previously, the whole
controller was updated, given that a slot entry adheres to controller's
peculiarities (that is an image should be aligned to specific image sizes
i.e. 256kB, 512kB, etc). However, that approach should adversely affect
flash memoy layout. The proposed scheme now imposes that images be aligned
to minimum cache-able area, that is 64KB.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
- Add SOC interrupt properties and interrupt-names ("reset_prep", "pcidev",
"pmu2ioapic") to intel_ish5 DTS files so PM IRQs are discoverable via DT.
- Move SEDI PM initialization and IRQ setup into ISH SOC PM init:
- Remove the direct call to sedi_pm_init() from soc_early_init_hook in
soc.c.
Previously SEDI code has those IRQ numbers hard coded and calls Zephyr APIs
to connect IRQs, which should be avoided.
Signed-off-by: Dong Wang <dong.d.wang@intel.com>
- cleanup header files included.
- Rename LOG_MODULE_REGISTER from pm_service to ish_pm and use
CONFIG_PM_LOG_LEVEL.
- Guard verbose debug traces so they only print for suspend-to-RAM/long
idle states, reducing runtime noise.
- Promote an unsupported power state message from LOG_DBG to LOG_ERR.
No functional change to power handling; changes are limited to logging
and verbosity control.
Signed-off-by: Dong Wang <dong.d.wang@intel.com>
Select ARM DWT feature to suppress build warning related to null pointer
detection mechanism.
Signed-off-by: Ioannis Karachalios <ioannis.karachalios.px@renesas.com>
Add UICR.SECURESTORAGE configuration based on device tree partitions.
Validates partition layout and populates size fields in 1KB units.
Handles missing partitions gracefully.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Switch to using the new NXP_ENABLE_WAKEUP_SIGNAL and
NXP_DISABLE_WAKEUP_SIGNAL macros to avoid adding
platform specific calls in the Zephyr drivers.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
The SDK code to handle managing Wakeup IRQ's for low power mode
varies between SoC's.
Add a MACRO that can be called by the Zephyr drivers so we
can manage these variations without adding SoC specific code
to the drivers.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Using WDT_DISABLE_AT_BOOT instead of WDOG_ENABLE_AT_BOOT prevents the
definition of z_arm_watchdog_init, which is important because the COP
watchdog configuration register can only be configured once.
Signed-off-by: Alexandre Rey <alx.rey@icloud.com>
Ensuring flash region has been erased before writing to avoid
inconsistences and force expected erased value (0xFF) into
flash when erasing a region when Hardware Flash Encryption is
enabled
This is handled on this implementation because MCUboot's state
machine relies on erased valued data (0xFF) readed from a
previously erased region that was not written yet, however when
hardware flash encryption is enabled, the flash read always
decrypts whats being read from flash, thus a region that was
erased would not be read as what MCUboot expected (0xFF).
Signed-off-by: Almir Okato <almir.okato@espressif.com>
The lfrccal takes the two properties tempMeasIntervalSeconds and
tempDeltaCalibrationTriggerCelsius which are in steps of 0.25.
The bicrgen.py script incorrectly treated these values as steps
of 1, so the actual values written to (and read from) bicr where
scaled incorrectly.
This commit fixes the scaling for those two props.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
This brings CMSIS HAL glue code, which is required if we want to enable
any HAL module without everything blowing up. cmsis_core_m_defaults.h
cannot be used once we enable HAL. CMSIS is that nice.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
SF32LB52x is a SoC from SiFli Technologies(Nanjing) Co., Ltd, based on
Arm Star-MC1 core (Cortex-M33 compatible).
For more details, see:
https://wiki.sifli.com/en/hardware/SF32LB520-3-5-7-HW-Application.htmlhttps://wiki.sifli.com/en/hardware/SF32LB52B-E-G-J-HW-Application.html
0-3-5-7 are powered using a Lithium battery and support USB charging.
B-E-G-J are powered at 3.3V and do not support charging.
Other termination codes indicate what type of memory and size is
embedded in the package (QSPI NOR or PSRAM).
Other families exist within the SF32LB family, like SF32LB56x,
SF32LB58x, etc.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Currently, the DMA on several Renesas boards is failing due to
the security attribution of DMA.
As a solution: Enable secure security attribution
for DMA module for:
- RA6: ra6e1, ra6e2, ra6m4, ra6m5
- RA4: ra4c1, ra4e1, ra4e2, ra4l1, ra4m2, ra4m3
Signed-off-by: Khanh Nguyen <khanh.nguyen.wz@bp.renesas.com>
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Enable CONFIG_PM_DEVICE_RUNTIME_DEFAULT_ENABLE by default for all
nordic SoCs if CONFIG_PM_DEVICE_RUNTIME is used. This will ensure
consistent behavior across all nordic SoCs and remove the need
for pasting the devicetree propert zephyr,pm-device-runtime-auto
everywhere.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Add support for BGM220P modules. Enable oscillators in SoC DTS
since the necessary crystals are present in the modules.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Add missing EUART0 peripheral to devicetree for xg22.
Fix NUM_IRQS, there are 64 external interrupts on xg22.
Remove `select` of UART_INTERRUPT_DRIVEN at SoC level, this doesn't
belong here, since it prevents disabling the UART. This should be a
board or application level decision.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Because generation and programming of UICR + PERIPHCONF artifacts
depend on the 'uicr' image which in turn must be included by Sysbuild,
many if not most nrf54h20 applications will need to be built using
Sysbuild to function as intended.
To make this known to the user, print a CMake warning whenever
CONFIG_NRF_PERIPHCONF_SECTION=y but Sysbuild is not being used.
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
Add build system support for populating the PERIPHCONF
(global domain peripheral configuration), based on nodes and properties
found in the devicetree. This should make it so all samples and tests
that were broken by the move to IronSide SE now function correctly
without workarounds or manual steps.
When enabled, a new python script called gen_periphconf_entries.py is
run when building. The script iterates over nodes and properties in the
devicetree and generates a C file called periphconf_entries_generated.c
in the build directory, which is added as a source file. The C file
uses the macros from uicr.h to configure the global domain according
to the devicetree.
The PERIPHCONF entry generation is enabled by default when building
for nrf54h20dk/nrf54h20/cpuapp and nrf54h20dk/nrf54h20/cpurad.
It will also be used on nrf9280 soon, therefore it is placed
in the common uicr directory.
This new feature does the same job as nrf-regtool did when building
for nrf54h20 before, and is compatible by the bindings that were used
by nrf-regtool.
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
In !XIP case, provide RAM_RO and RAM_RW regions with their
respective MPU configurations.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Co-authored-by: Sudan Landge <sudan.landge@arm.com>
MCU_GAP_FILLING is advised on ARMv8 based platforms to prevent from
against attacks that attempt to execute malicious code from SRAM.
It is enabled by default when USERSPACE is disabled, enable it
also when enabled.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
The SIUL2 pin control driver is a native implementation usable across
all NXP SoCs with SIUL2 IP. Remove the "S32" prefix to allow clean
reuse by other families.
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
Originally the driver is selected if `HAS_MCUX_SRC_V2` is
selected in SOC level kConfig.
Change to use dts to mark the driver is avaiable for some SOC.
Signed-off-by: Jason Yu <zejiang.yu@nxp.com>
Added support for sys_poweroff on ADL and ATOM socs based on
acpi_poweroff.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
