The IRQSTEER driver defines the z_soc_irq_* SoC multi-level
interrupt hooks directly, claiming the SoC's contract from a driver:
z_soc_irq_enable(), z_soc_irq_disable(), z_soc_irq_is_enabled() and
z_soc_irq_priority_set(), plus an internal helper that also sat in
the global z_soc namespace. Interrupt controller drivers should only
expose their own namespaced API; providing the SoC hooks is platform
glue and does not belong in a driver.
Rename the control functions to nxp_irqstr_irq_* following the
driver's existing internal prefix, declare them in a driver header,
make the internal enable/disable helper static, and provide the
z_soc_irq_* mapping from one shared platform file wired at the i.MX
family level, covering every SoC with an IRQSTEER devicetree node
(i.MX8/8M/8X ADSP on Xtensa, i.MX93/94/95 M cores on ARM).
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The deep-sleep counter (1kHz RTC) used on platform RW61x stops at
zero and does not track PM3 exit recovery time. This causes two
issues:
1. After PM3 exit, the kernel sees unaccounted time remaining
and enters a parasitic PM2 to fill the gap. Fix by adding
the exit-latency back to the compensated sleep time in the
OS timer driver (mcux_os_timer.c).
2. On counter overflow re-entry into PM3, the PM policy
exit-latency subtraction is not applied since re-entry
bypasses the PM framework. Fix by adjusting the RTC wakeup
count in the SoC power re-arm loop (soc/nxp/rw/power.c).
Signed-off-by: Jacob Wienecke <jacob.wienecke@nxp.com>
Every MAX32 SoC carried a hardcoded CONFIG_NUM_IRQS sized to the full
hardware IRQ line count: 18 values spread over 14 Kconfig files in three
different syntactic styles. Each one had to be maintained by hand, was
easy to get wrong when a peripheral was added, and forced applications
to carry an ISR table sized for peripherals they never enable.
Replace them with a single family-level default derived from the
devicetree via dt_highest_controller_irq_number(). The helper only
considers nodes with status = "okay", so the table is now sized to what
the application actually uses. Both cores are covered: Cortex-M4 and
Cortex-M33 through the NVIC node, RV32 through the MAX32 RISC-V core
interrupt controller. Only one of those controllers is ever present in a
given build's devicetree, so the default for the other core is inert.
The default is declared with configdefault and placed after the per-SoC
rsource statements, so a SoC or a board can still pin an explicit value.
Measured with samples/hello_world, the derived values are at or below
the previous constants on all 32 buildable MAX32 board targets, for
example max78002/m4 105 -> 57, max32657 54 -> 26 and max32655/rv32
64 -> 28.
This mirrors the equivalent change made for STM32.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Maureen Helm <maureen.helm@analog.com>
nrfx 4.5.0 restructured NRF_WICR_Type. The Wi-Fi core boot address
previously sat inside an anonymous reserved block, so wifi_setup()
read it as NRF_WICR->RESERVED[0], which resolved to WICR + 0x000.
The new layout names that region as the FIRMWARE group:
__IOM NRF_WICR_FIRMWARE_Type FIRMWARE; /* 0x000 */
__IM uint32_t RESERVED[28];
__IOM NRF_WICR_IPCCONFIG_Type IPCCONFIG; /* 0x080 */
FIRMWARE occupies 0x000..0x00F, so RESERVED[0] silently moved from
0x000 to 0x010. The code still compiles, but now reads an
unprogrammed word instead of the LMAC boot address. The LMAC VPR is
started at a bogus PC, so the Wi-Fi core never boots and the IPC
endpoint never binds:
<err> wifi_nrf: IPC endpoint not bound after 30000 ms
<err> wifi_nrf: nrf_wifi_fmac_dev_add_zep: dev_init failed
Read the named FIRMWARE.LMACINITPC field instead. This matches the
offset the WICR generation tooling programs for firmware-lmacinitpc
(soc/nordic/nrf71/wicr/gen_wicr/gen_wicr.py), so the boot address is
picked up from the same location it is written to.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
Assisted-by: Claude:claude-opus-5
The ART (Adaptive Real-Time) flash cache accelerator base address is
configured using only DT_REG_ADDR(DT_CHOSEN(zephyr_flash)) without
accounting for CONFIG_FLASH_LOAD_OFFSET. When the M4 flash layout uses
zephyr,flash = &flash0 with a non-zero CONFIG_FLASH_LOAD_OFFSET,
the ART caches the wrong flash region.
For example, with CONFIG_FLASH_LOAD_OFFSET=0x100000 the ART points at
0x08000000 (Bank 1) while M4 code executes from 0x08100000 (Bank 2).
This results in a 0% cache hit rate and every instruction fetch paying
the full flash wait-state latency penalty. Since the M4 core has no
I-Cache or D-Cache, the ART accelerator is its only flash caching
mechanism.
Add CONFIG_FLASH_LOAD_OFFSET to the ART base address calculation so it
points to the actual code execution region. This is a no-op when
CONFIG_FLASH_LOAD_OFFSET=0.
Signed-off-by: Farrell Aultman <Farrell.Aultman@sandc.com>
Signed-off-by: Murali Karicheri <murali.karicheri@sandc.com>
1. update hal nxp to the SDK 26.09.00 pvw1
2. MCXA SystemInit initializes SRAM ECC by clearing
the first 8 KiB of SRAM. Zephyr calls SystemInit after
moving MSP to the main stack in that range, so the
clear corrupts the active return stack and locks up
during boot.
Move the ECC initialization to the no-stack early
reset hook and prevent SystemInit from repeating it.
This preserves cold-boot ECC initialization
without clearing an active Zephyr stack.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Remove the CONFIG_BT_CONN_TX_MAX Kconfig option and its only in-tree
user, the SiWx91x SoC configdefault. No C code has read the symbol since
it was deprecated, so it had no effect on any build; the number of
pending TX buffers with a callback follows CONFIG_BT_BUF_ACL_TX_COUNT,
which was already both the default and the range floor of the removed
option. The SiWx91x default of 15 matched that SoC's
BT_BUF_ACL_TX_COUNT default, so behaviour is unchanged there too.
Deprecated in Zephyr 4.2.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:opus-5
For the rpi5, you will need to use both the BCM2712 the RP1 pinctrl driver.
The process for selecting which to use is done in
`soc/brcm/bcm2712/pinctrl_soc.c`.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
This commit adds missing DISCARDs for the `.note.GNU-stack` section, which
carries information about whether the ELF requires an executable stack.
Since Zephyr largely operates without an ELF loader, this section can be
safely discarded, and already is for the vast majority of platforms:
% grep -R ".note.GNU-stack" * | wc -l
51
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
CONFIG_BT_AUTO_PHY_UPDATE was deprecated in Zephyr 4.3 in favour of the
role-specific BT_AUTO_PHY_CENTRAL and BT_AUTO_PHY_PERIPHERAL Kconfig
choices, which also allow picking which PHY is preferred. Remove it as
part of the 4.5 deprecation removal cycle.
All C code and all in-tree samples and tests were already migrated to
the role-specific options when the deprecation was introduced, so only
the remaining Kconfig references need dropping. Since the deprecated
symbol lost its "default y if !BT_USER_PHY_UPDATE" in 4.3, it has been
unset in every in-tree configuration ever since, which makes each of
these references dead code today:
- The BT_AUTO_PHY_PERIPHERAL choice loses its "default
BT_AUTO_PHY_PERIPHERAL_2M if BT_AUTO_PHY_UPDATE" entry and keeps
falling through to _NONE, as it already did.
- BT_CTLR_LLCP_LOCAL_PROC_CTX_BUF_NUM loses the always-false
"BT_AUTO_PHY_UPDATE=y" disjunct of its "default 6" condition, which
now reads exactly as it already evaluated: BT_AUTO_DATA_LEN_UPDATE=y
&& BT_CTLR_LLCP_CONN < 4.
- The STM32WB0 SoC defconfig set BT_AUTO_PHY_UPDATE=n, which had no
effect on either role, and is simply dropped.
This keeps the change behaviour-neutral. Two pre-existing quirks are
deliberately left alone rather than fixed here, since they are policy
changes for their respective maintainers and not part of removing a
deprecated symbol: the local procedure context count no longer reaches
6 via automatic PHY update, and the STM32WB0 series follows the
BT_AUTO_PHY_CENTRAL default of _2M for central-role connections.
The BT_BUF_CMD_TX_COUNT help text is updated to name the replacement
choices.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:opus-5
Manually trigger GPIO_IRQn after waking up from backup mode. Do not
disable retention ldo after waking up from backup mode as it causes
resets in standby mode.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
This commit moves pinctrl registers definition file to RTS5817
soc directory, because gpio driver will also include this file
Signed-off-by: Darcy Lu <darcy_lu@realsil.com.cn>
The generic RISC-V timing backend reads the kernel cycle counter,
which on these SoCs is the systimer at 16MHz. A tick of 62.5ns is
coarse next to a kernel latency of a few hundred nanoseconds, so
a whole distribution can collapse onto one or two counter values.
Add a SoC backend reading the mcycle CSR, which counts at the CPU
clock: 240MHz on the ESP32-C5 and 400MHz on the ESP32-P4. Only
those two select it. The older cores in the family count cycles
in a custom CSR and do not implement mcycle, so the capability is
selected per SoC rather than family wide.
Assisted-by: Claude:opus-4-8
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The ACE40 MMU mapping table doesn’t have entries for the rom_ext
code and data IMR regions. This prevents FW access to rom_ext
authentication API callbacks. Hence adding those missing entries.
Signed-off-by: Wojciech Jablonski <wojciech.jablonski@intel.com>
Flash constants live in a DROM window separate from executable text.
PMP already covers the text region, but without a matching read entry
for DROM, user mode faults as soon as it touches const data. Add a
read-only PMP region over the full image rodata range on C5, C6, and P4.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
This changes include:
- Streamline data structures by embedding espi_taf_pckt directly into
driver data, eliminating manual field copies and indirection.
- Optimize completion handler to write directly to FLASHTXBUF register.
- Implement defensive RX/TX bounds validation to guard against buffer
overflows.
- Add safety fallback for unsupported eSPI cycle type.
Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
Add macros that treat the QMSPI Mode register's three clock bits (idle
state, transmit phase, sample phase) as a single SPI-mode field to
simplify driver code.
The Control and Descriptor registers' TX and RX DMA-enable fields use
the same value encoding, so share one direction-agnostic set of value
macros (DMA_DIS; LDMA_CH0..2 for local-DMA channels; DMAC_U1B/U2B/U4B
for central-DMA access size) while keeping separate TX/RX get/set
macros. This also corrects the 4-byte TX value, which was 4 (out of
range for the 2-bit field) and is now 3, matching RX.
Update the existing spi_xec_qmspi_ldma.c consumer to the new LDMA_CH0
names; identical field values, so no functional change.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Replace use of dt_nodelabel_has_prop() with use of
dt_nodelabel_bool_prop() on boolean properties since the former always
return true when a property is defined which is the case for
"nordic,nrf-radio" and "silabs,series2-radio" DT compatible nodes which
both include ble-radio.yaml and radui.yaml bindings that defines these
boolean properties.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Add the SDIF node and attach its source clock: the main clock, divided to
stay within the controller's maximum source frequency. The divider follows
the cpu node's clock-frequency, as the rest of this file does.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Marvin Gnad <marvin.gnad@gmail.com>
Remove CONFIG_PLATFORM_SPECIFIC_INIT and its z_arm_platform_init() hook,
deprecated in favour of CONFIG_SOC_RESET_HOOK / soc_reset_hook() well
before Zephyr 4.2 and therefore due for removal in 4.5.
The option had no reader left: neither cortex_m/reset.S nor
cortex_a_r/reset.S tests it, both only branch to soc_reset_hook(). Its
single in-tree selector, soc/renode/cortex_r8_virtual, is migrated to
select SOC_RESET_HOOK and its hook renamed to soc_reset_hook(); the body
is unchanged. Note that this re-activates the SCTLR.V clear on that SoC,
which had silently been dead code since the reset paths stopped calling
z_arm_platform_init() - the SoC now again selects the low exception
vector base as originally intended. It runs slightly later in the reset
sequence, after the per-mode stack pointers are set up. This should be
smoke-tested under Renode.
The stale z_arm_platform_init mention in the IAR linker script helper
comment is updated to soc_reset_hook.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Assisted-by: Claude:opus-5
Add the USB0 full-speed and USB1 high-speed IP3511 device-controller
nodes and the dedicated 8K USB SRAM region, bring up the USB PHYs and
device clocks in clock_init(), and link the USB stack's buffers into the
dedicated RAM (usb.ld) as the IP3511HS controller requires.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Marvin Gnad <marvin.gnad@gmail.com>
soc/arm/beetle carried its own soc.yml, which made it a SoC tree of its
own even though it sits inside soc/arm and is already reached from there:
soc/arm/Kconfig.soc and soc/arm/Kconfig rsource */Kconfig.soc and
*/Kconfig, and soc/arm/CMakeLists.txt adds the series subdirectory.
The two trees therefore had to be loaded together for beetle to work,
as soc/arm/beetle/Kconfig.soc selects SOC_FAMILY_ARM from
soc/arm/Kconfig.soc, and beetle's Kconfig.soc ended up being sourced
twice, once through the generated Kconfig.soc and once through the
rsource glob.
Describe beetle as a series of the arm family in soc/arm/soc.yml and drop
the extra soc.yml. beetle_r0 now resolves to the soc/arm directory, which
is where its files are reached from anyway.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The MCUX HAL places code and data into custom "CodeQuickAccess" and
"DataQuickAccess" input sections (for example in fsl_romapi.c) via the
AT_QUICKACCESS_SECTION_* macros. On the RT11xx SoC these were never
collected by a linker script, so they became orphan output sections.
For an orphan code section GCC also emits an orphan
".ARM.exidxCodeQuickAccess" unwind-index table. This table is kept
whenever CONFIG_ARCH_STACKWALK is enabled (for example sample.perf,
which sets CONFIG_FRAME_POINTER=y). The orphan code and its exidx
entry can be placed more than 1 GB apart, overflowing the 31-bit
R_ARM_PREL31 relocation and breaking the link with:
relocation truncated to fit: R_ARM_PREL31 against `CodeQuickAccess'
Add SoC linker snippets that pull CodeQuickAccess into the ROM text
region and DataQuickAccess into the initialized data region, so the
sections are no longer orphans and each code section stays adjacent
to its unwind data. This fixes sample.perf on mimxrt1170_evk/cm7.
Fixes#115625
Assisted-by: GitHubCopilot:claude-opus-4.8
Signed-off-by: Hake Huang <hake.huang@nxp.com>
GCC now emits DWARF 5 since -gdwarf-4 was dropped, which adds
.debug_rnglists, .debug_loclists and .debug_line_str. The RT6xx/RT7xx
HiFi linker scripts only listed the DWARF 1-3 sections, so those became
orphan sections, and --orphan-handling=warn with --fatal-warnings turned
them into a link error.
Add the DWARF 5 sections these three scripts were missing, matching what
the other Xtensa SoC scripts and include/zephyr/linker/debug-sections.ld
already do.
Assisted-by: Claude Code:claude-opus-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
dt_nodelabel_has_prop only checks for the existence of a property. bool
properties always exist if they are defined in the binding and have a value
of either true or false.
This caused these configs to always default to true - even if the
properties weren't enabled in the device tree.
Signed-off-by: Michael Zimmermann <michael.zimmermann@sevenlab.de>
The default drive strength for edge gpios was being assigned to the
incorrect value of one-eighth. It is now being set to half strength.
Signed-off-by: Brett Peterson <brett.peterson@infineon.com>
The Type D IOCON register is not laid out the same way on the two SoCs
that share this directory: the LPC546xx FUNC field is one bit wider, so
MODE sits at [5:4] instead of [4:3] and DIGIMODE and FILTEROFF move up
with it. Compare UM10914 Table 206 with UM10912 Table 252.
soc.h hardcoded the LPC5411x positions, so the values it provides are
not correct on the LPC546xx.
Derive them from the device header's field macros, as pinctrl_soc.h
already does, so they follow whichever layout the SoC has.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Marvin Gnad <marvin.gnad@gmail.com>
Setting symbol default value without 'configdefault', or without
explicit 'if' checks of dependencies, results in dependency weakening.
In this case, NOCACHE_MEMORY is redefined and set to the given default
value even if dependency ARCH_HAS_NOCACHE_MEMORY_SUPPORT is
not selected.
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
Setting symbol default value without 'configdefault', or without
explicit 'if' checks of dependencies, results in dependency weakening.
In this case, CACHE_MANAGEMENT is redefined and set to the given
default value even if dependencies D/ICACHE are not enabled.
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
Setting symbol default value without 'configdefault', or without
explicit 'if' checks of dependencies, results in dependency weakening.
In this case, CACHE_MANAGEMENT is redefined and set to the given
default value even if dependencies D/ICACHE are not enabled.
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
Setting symbol default value without 'configdefault', or without
explicit 'if' checks of dependencies, results in dependency weakening.
In this case, CACHE_MANAGEMENT is redefined and set to the given
default value even if dependencies D/ICACHE are not enabled.
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
Setting symbol default value without 'configdefault', or without
explicit 'if' checks of dependencies, results in dependency weakening.
In this case, CACHE_MANAGEMENT is redefined and set to the given
default value even if dependencies D/ICACHE are not enabled.
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
Setting symbol default value without 'configdefault', or without
explicit 'if' checks of dependencies, results in dependency weakening.
In this case, CACHE_MANAGEMENT is redefined and set to the given
default value even if dependencies D/ICACHE are not enabled.
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
Setting symbol default value without 'configdefault', or without
explicit 'if' checks of dependencies, results in dependency weakening.
In this case, CACHE_MANAGEMENT is redefined and set to the given
default value even if dependencies D/ICACHE are not enabled.
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
Setting symbol default value without 'configdefault', or without
explicit 'if' checks of dependencies, results in dependency weakening.
In this case, CACHE_MANAGEMENT is redefined and set to the given
default value even if dependencies D/ICACHE are not enabled.
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
Setting symbol default value without 'configdefault', or without
explicit 'if' checks of dependencies, results in dependency weakening.
In this case, CACHE_MANAGEMENT is redefined and set to the given
default value even if dependencies D/ICACHE are not enabled.
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
Setting symbol default value without 'configdefault', or without
explicit 'if' checks of dependencies, results in dependency weakening.
In this case, CACHE_MANAGEMENT is redefined and set to the given
default value even if dependencies D/ICACHE are not enabled.
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
Setting symbol default value without 'configdefault', or without
explicit 'if' checks of dependencies, results in dependency weakening.
In this case, CACHE_MANAGEMENT is redefined and set to the given
default value even if dependencies D/ICACHE are not enabled.
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
