Commit graph

5973 commits

Author SHA1 Message Date
Tien Nguyen
673d408b40 soc: renesas: Add initial support for Renesas RZ/G2LC
Add initial support for Renesas RZ/G2LC (r9a07g044c22gbg), a 361-pin
package variant of RZ/G2L

Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Phuc Pham <phuc.pham.xr@bp.renesas.com>
2025-04-16 08:10:38 +02:00
Ayush Singh
e443fbd6db soc: ti: k3: Add support for AM6232
- AM6232 is a dual core variant of AM6234 with everything being smae.
- Used in the first batch of PocketBeagle 2

Signed-off-by: Ayush Singh <ayush@beagleboard.org>
2025-04-16 01:15:41 +02:00
Charles Dias
389c9e7b67 soc: st: stm32: add support for stm32u5g9xx
Add Kconfig and YML SoC configurations for STM32U5G9xx.

Signed-off-by: Charles Dias <charlesdias.cd@outlook.com>
2025-04-16 01:10:06 +02:00
Francois Ramu
82d0c7aa5c soc: stm32: Adds the STM32WBA65x device.
This commit adds support for the STM32WBA65x MCU.

Signed-off-by: Francois Ramu <francois.ramu@st.com>
2025-04-15 15:33:15 +02:00
Jhan BoChao
482d17f235 driver: sensor: add tachometer driver for rts5912
Add tachometer driver for Realtek rts5912.

Signed-off-by: Jhan BoChao <jhan_bo_chao@realtek.com>
2025-04-15 09:28:01 +02:00
Nitin Pandey
50e36095dd driver: wifi: siwx91x: Add roaming configuration
- Defined Kconfig macros for Roam config
- Added set roam configuration API call
  after BGSCAN

Signed-off-by: Nitin Pandey <nitin.pandey@silabs.com>
2025-04-14 23:06:20 +02:00
Neil Chen
720f726072 soc: mcxa153: add SOC support for MCXA153
Add MCXA153 support

Signed-off-by: Neil Chen <cheng.chen_1@nxp.com>
2025-04-12 00:02:28 +02:00
Scott Worley
4d1139de91 soc: microchip: mec: Unify kernel timer tick rate configuration
Microchip MEC was configuring the kernel timer tick rate at the
board level instead of the SoC level. We unify all this by moving
the Kconfig logic out of the board level into each mec chip.
We also derive SYS_CLOCK_HW_TICKS_PER_SEC from the device tree
node enabled for the kernel timer: Microchip's 32 KHz RTOT timer
or Cortex-M4 SYSTICK. The soc kconfig rules are loading all mec
subdirectories for every build causing warnings when building
new socs with this change. We made the changes for all the mec chips.

Signed-off-by: Scott Worley <scott.worley@microchip.com>
2025-04-11 17:31:37 +02:00
Lucas Tamborrino
232e2c5a3c drivers: uart: espressif: Add LP UART driver
Add LP UART driver for LP Core

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2025-04-11 13:34:17 +02:00
Lucas Tamborrino
0b79b47811 soc: espressif: Filter LP Core from esptool command
Filter LP Core from esptool post build commands

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2025-04-11 13:34:17 +02:00
Eric Ackermann
39babba9a9 soc: add OpenHW Group CVA6 SoC
Adds support for the CVA6 family of RISC-V CPUs.
CVA6 is commonly found as a soft core CPU on FPGA designs.
Different configurations and instruction set extensions can be
configured, and different SoCs targeting various FPGA boards are
available.
This commit adds support for the 32-bit and 64-bit configurations
of CVA6, as well as three slightly different SoCs (a minimal 32-bit
configuration, a 64-bit configuration without FPU, a 64-bit
configuration with FPU).

Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
2025-04-11 13:33:50 +02:00
Tim Lin
f3ddb06028 soc: ite: ilm: it51xxx: Support RAM code size up to 4K
Previously, the RAM code size was limited to 1K, causing issues when the
code exceeded this limit. This update modifies the implementation to
support RAM code sizes up to 4K

test: zephyrproject/zephyr/tests/drivers/flash/common --> pass

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2025-04-11 06:34:15 +02:00
Tomáš Juřena
d700943d29 soc: st: stm32: Add poweroff to F4 family
Allows F4 MCUs to enter standby mode which behave similar to the poweroff
mode.

Signed-off-by: Tomáš Juřena <jurenatomas@gmail.com>
2025-04-11 06:33:56 +02:00
Derek Snell
070bd0e295 soc: nxp: rw61x: enable USB clock for UDC
When using USB Next stack and UDC driver, enable USB clock

Signed-off-by: Derek Snell <derek.snell@nxp.com>
2025-04-10 15:51:45 +02:00
Krzysztof Chruściński
a36b154fd1 soc: nordic: nrf54h: power: Enable cache as early as possible
Add nrf_cache_power_up and nrf_cache_power_down functions. In case of
s2ram power up cache as early as possible, before restoring ARM core
registers. It improves restore time from 180 us to 33 us.

As a minor optimization nrf_memconf_ramblock_control_mask_enable_set is
used which allows to control ram blocks for icache and dcache in a
single register write.

Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
2025-04-09 15:24:02 +02:00
Tomáš Juřena
315ea56fef soc: st: common: Rename STM32_PWR_WKUP_PIN_SRC_x
This renames the STM32_PWR_WKUP_PIN_SRC_x symbols to better match
their meaning. It also adds a new symbol (STM32_PWR_WKUP_PIN_NOT_MUXED)
for SoCs without wake-up mux support.

Signed-off-by: Tomáš Juřena <jurenatomas@gmail.com>
2025-04-09 15:22:59 +02:00
Tien Nguyen
1d736d36ab driver: pinctrl: Add support for Renesas RZ/G2L
Add pinctrl support for Renesas RZ/G2L

Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
2025-04-09 12:35:54 +02:00
Tien Nguyen
de49dac738 soc: renesas: Add initial support for Renesas RZ/G2L
Add initial support for Renesas RZ/G2L

Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
2025-04-09 12:35:54 +02:00
Andrzej Głąbek
4dded19ad7 soc: nordic: Disable cache for soft peripheral RAM region in nRF54H/nRF92
Add an entry for the RAM region assigned to soft peripherals that will
disable caching for that region. Without this, communication with the
FLPR coprocessor cannot be performed correctly.

Signed-off-by: Andrzej Głąbek <andrzej.glabek@nordicsemi.no>
2025-04-08 16:11:31 +02:00
Tomáš Juřena
f1e3784b9d soc: st: stm32: poweroff uses stm32_wkup_pins
Update the poweroff code to use stm32_pwr_wkup_pin_cfg_pupd if enabled.

Signed-off-by: Tomáš Juřena <jurenatomas@gmail.com>
2025-04-08 11:45:24 +02:00
Tim Lin
a531e71376 drivers/timer: Add timer driver of it51xxx
Add timer driver for ITE it51xxx series.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2025-04-08 10:48:26 +02:00
Tim Lin
df56c85e94 drivers/clock: Add clock drivers of it51xxx
Add clock drivers for ITE it51xxx series.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2025-04-08 10:48:26 +02:00
Tim Lin
8c2f5684bb drivers/flash: Enable flash controller for it51xxx series
Enable flash controller for ITE it51xxx series.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2025-04-08 10:48:26 +02:00
Tim Lin
d9571f6412 soc: ITE: ilm: Enable instruction memory for it51xxx series
Enable instruction memory for ITE it51xxx series.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2025-04-08 10:48:26 +02:00
Tim Lin
f0d21fb497 drivers/pinctrl: Enable pinctrl driver for it51xxx series
Enable pinctrl driver for ITE it51xxx series.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2025-04-08 10:48:26 +02:00
Tim Lin
7a06df9cc3 soc: ITE: Add ITE it51xxx SoC
Add support for ITE it51xxx SoC.
NOTE: it51526aw is not support RISCV_ISA_EXT_C.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2025-04-08 10:48:26 +02:00
Tim Lin
0e5218cbcc drivers: ITE: Use generic name instead of specific chip name
Use generic name for structure in driver instead of specific chip name
for better compatibility.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2025-04-08 10:48:26 +02:00
Tim Lin
09f25854b3 soc: Separate it8xxx2 related files from the common folder
Some files should be separated from the common folder to
each soc folder for future expansion of the chip.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2025-04-08 10:48:26 +02:00
Tim Lin
c7e6cfb8cb soc/ite/ec: common: Modify the format to comply with check_compliance.py
Modify the format to comply with check_compliance.py.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2025-04-08 10:48:26 +02:00
Titan Chen
5a94a1ca66 drivers: counter: rts5912: add support slow timer counter driver
Port rts5912 slow timer counter driver on Zephyr

Signed-off-by: Titan Chen <titan.chen@realtek.com>
2025-04-07 21:13:10 +02:00
Samuel Chee
7e95006abf drivers: pinctrl: add pinctrl drivers for arm v2m_beetle
Adds pinctrl driver for the v2m_beetle board target.

Signed-off-by: Samuel Chee <samche01@arm.com>
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
2025-04-07 15:18:10 +02:00
Samuel Chee
a2f0e5d372 drivers: pinctrl: add pinctrl drivers for arm mps3
Adds pinctrl driver for all Arm mps3 targets

Signed-off-by: Samuel Chee <samche01@arm.com>
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
2025-04-07 15:18:10 +02:00
Samuel Chee
99ae4bf132 drivers: pinctrl: add pinctrl driver for Arm mps2
Adds pinctrl driver for all Arm mps2 targets.

Signed-off-by: Samuel Chee <samche01@arm.com>
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
2025-04-07 15:18:10 +02:00
Iuliana Prodan
ab5c0b5195 soc: nxp: imx: add resource_table section in linker script
Add resource_table section in linker script
for i.MX8ULP, for inter-process communication.

Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
2025-04-07 15:17:34 +02:00
Aksel Skauge Mellbye
64a4c593e1 drivers: pinctrl: silabs: Add support for fixed routes
Add support for fixed GPIO routes that don't have a configurable
route register, but still require mode configuration and enabling.

Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
2025-04-07 08:54:38 +02:00
Alvis Sun
dd578065bc soc: nuvoton: npcx: refactor npcx soc hierarchy for future chip support
This commit refactors the NPCX SoC hierarchy to improve maintainability and
enable future support for upcoming chips.

Key changes include:
1. Introduced a new `npcxn` subdirectory under `common/` to consolidate
shared components across the npcxn series.
2. Renamed and reorganized register access files for improved consistency.
3. Updated relevant Kconfig files, header files, and CMakeLists
for the new structure.

Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
2025-04-07 07:27:38 +02:00
Marek Matej
f10e7b8395 soc: espressif: esp32: Allow DRAM1 to use for .noinit
Add config to relocate the .noinit section to DRAM1 region.
Remove unused config.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2025-04-07 07:27:23 +02:00
Nhut Nguyen
6ca84e3c9a soc: renesas: rz: Fix loader program
Due to a change in linker script cortex_a_r/scripts/linker.ld
, the _image_ram_start has been changed so the Zephyr image
cannot be copied from flash to ram as expected
and cannot run properly.
It is replaced by CONFIG_SRAM_BASE_ADDRESS, the _image_ram_size is also
replaced by _flash_used as a preventive measure.

Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
2025-04-06 12:18:07 +02:00
Sylvio Alves
ac0705d59b soc: espressif: update restart procedure
Use esp_restart call to guarantee and registered
shutdown handlers will be triggered before rebooting.
This guarantees that subsystems like Wi-Fi and BLE
will deinit correctly.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-04-05 11:02:13 +02:00
Christopher Cichiwskyj
7dcec3384e soc: add support for STM32F479
This chip shares its design with STM32F469, but with
an added cryptography accelerator.

Signed-off-by: Christopher Cichiwskyj <cichiwskyj@gmail.com>
2025-04-04 12:06:29 +02:00
Adrian Bonislawski
e64cce9053 soc: intel_adsp: ace30: set MMU permissions for rom_ext sections
This patch will set MMU permissions for rom_ext sections
It is possible to call the rom_ext code located in IMR

Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
2025-04-04 09:35:29 +02:00
Adrian Bonislawski
368f6cfee4 soc: intel_adsp: ace30: extend hwreg1 MMU mapping
This patch will extend MMU mapping range for hwreg1 entry
because it is required to access lower register addresses

Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
2025-04-04 09:35:29 +02:00
Julien Racki
c099e27c06 soc: st: stm32: Provide basic support for STM32MP13 series
Enable basic support to STM32MP13, in single core configuration (A7)
with I and D cache enabled.

Signed-off-by: Julien Racki <julien.racki@st.com>
2025-04-04 09:35:03 +02:00
Emilio Benavente
9a893c6bd9 boards: nxp: Added I2S Support for RW612
Added I2S support for RW612.

Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
2025-04-03 21:06:14 +02:00
Krzysztof Chruściński
4b1691531b soc: nordic: nrf54h: Change PM_DEVICE_RUNTIME default
nrf54h20 device requires device runtime PM to be enabled when
device PM is in use.

Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
2025-04-03 11:07:55 +02:00
Jiafei Pan
e94a545599 soc: imx9: fix pinctrl drive strength setting
Current code configures the higher bits ahead of drive strength
to be "1", this patch fix this issue.

Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Signed-off-by: Lei Xu <lei.xu@nxp.com>
2025-04-03 11:07:01 +02:00
Peter Wang
9580bc5627 soc: mcxa166,mcxa276: add SOC support for MCXA166 and MCXA276
add soc MCXA166 and MCXA276 for board frdm_mcxa166 and frdm_mcxa276

Signed-off-by: Peter Wang <chaoyi.wang@nxp.com>
2025-04-03 08:43:16 +02:00
Khanh Nguyen
fb572d59a2 soc: renesas: Add power management support for Renesas RA8
Updated `CMakeLists.txt` and `Kconfig` to integrate power management
for RA8D1, RA8M1, and RA8T1.

Modified `Kconfig.defconfig` to configure ULPT timer as the system timer
when power management is enabled:
- Adjusted `SYS_CLOCK_HW_CYCLES_PER_SEC` and `SYS_CLOCK_TICKS_PER_SEC`
for ULPT timer.
- Disabled `CORTEX_M_SYSTICK` when ULPT timer is used as the system timer.

Implemented power management logic in the new `power.c` file for:
- RA8D1 (`soc/renesas/ra/ra8d1/power.c`)
- RA8M1 (`soc/renesas/ra/ra8m1/power.c`)
- RA8T1 (`soc/renesas/ra/ra8t1/power.c`)

Signed-off-by: Khanh Nguyen <khanh.nguyen.wz@bp.renesas.com>
2025-04-03 08:41:08 +02:00
S Mohamed Fiaz
701be0c331 driver: sleeptimer: siwx917: Add siwx91x Sleeptimer driver
This commit enables the Sleeptimer driver support for the siwx917 device.

Signed-off-by: S Mohamed Fiaz <fiaz.mohamed@silabs.com>
2025-04-03 06:24:54 +02:00
Sylvio Alves
9857f114f8 linker: esp32: move regi2c_ctrl to iram
This prevents boot lock up due to critical sections
calls during bootloader stage.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2025-04-03 00:03:56 +02:00