Manifest parsing has been moved to common/ so there is no need
to include this header anymore in sram.c.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Both CONFIG_INTEL_ADSP_(UN-)CACHED_REGION should be dependent
on whether CONFIG_INTEL_ADSP_MEMORY_IS_MIRRORED is enabled.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Correct the existing CONFIG_XTENSA_CPU_HAS_HIFI* version for
the ACE SoC to reflect the actual version of HiFi being used.
This is purely cosmetic as the current architecture code does
not distinguish between versions.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Since it unconditionally targets labels in the gpio[a-z] range,
If gpio-expander uses a label that matches this rule,
it will behave incorrectly.
For example, follows
```
gpioz: gpio {
compatible = "awinic,aw9523b-gpio";
```
We using instead of DT_NODE_HAS_STATUS_OKAY, limit it to nodes with
`st,stm32-gpio` or `st,stm32mp2-gpio` compatibility using
DT_NODE_HAS_COMPAT_STATUS.
Co-authored-by: Mathieu CHOPLAIN <mathieu.choplain-ext@st.com>
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
The Xtensa arch code can generate the linker snippet for vectors
to be included in the main linker script. So use that instead of
manually doing it in linker script. This follows the allocated
space defined in SoC automatically.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Adds public API header for the PSC3 HPPASS, with the following:
- Interrupt mask constants.
- Event callback types.
- API functions: Autonomous Controller management, HPPASS management and
status, trigger helpers, and callback registration.
Assisted-by: Github Copilot:claude-opus-4.7
Signed-off-by: John Batch <john.batch@infineon.com>
kernel.h implies kernel_structs.h via kernel_includes.h, making
explicit inclusion of kernel_structs.h unnecessary whenever kernel.h
is already included in the same translation unit.
Remove the redundant includes across arch, boards, drivers, kernel,
lib, samples, subsys, and tests trees.
in include/zephyr/kernel_structs.h:
* 2. kernel.h shall imply kernel_structs.h, such that it shall not be
* necessary to include kernel_structs.h explicitly when kernel.h is
* included.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Updates the SoC initialization to configure PSRAM IO GLB register such that
PSRAM GPIO registers (32-37) are reused for pins whose registers are
allocated for SF2 internal flash (23-28), and modifies the GPIO driver to
use those offset registers when configuring.
Signed-off-by: Dan Mangum <georgedanielmangum@gmail.com>
Co-authored-by: Camille BAUD <mail@massdriver.space>
The BICR structure has a field at the end for a CRC of the preceeding
structure. Add computation and population of the CRC field to the
bicrgen.py script, and add a check for the validity of the CRC field,
if present, when parsing a BICR structure.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Add soc_secure_flash_range_is_secure() and soc_secure_flash_read().
The helpers classify a flash range against the "nordic,tz-secure"
devicetree descriptor and route reads that overlap a tagged secure
partition through soc_secure_mem_read(). Other reads stay a plain
memcpy().
The ranges are expanded from DT at build time, so contiguous
(nRF54L, nRF7120) and interleaved (nRF5340, nRF91 multi-slot
MCUboot) layouts work with the same helper. Without an okay
tz-secure node, or in secure builds, both helpers reduce to a plain
memcpy() and can be called unconditionally.
A matching stub is added to the nrf_bsim soc_secure.h.
Signed-off-by: Dag Erik Gjørvad <dag.erik.gjorvad@nordicsemi.no>
Clean up soc from unneeded HF CLK initialization which is done
using DT configuration for clocks.
Signed-off-by: Laura Carlesso <laura.carlesso@infineon.com>
Add support for full SMIF hardware initialization for the serial
memory flash driver when booting from internal RRAM.
On PSE84, the ROM extended boot only configures the SMIF subsystem
when the device boots from external flash. When the first application
(MCUboot or CM33 secure) runs from RRAM, the SMIF pins, clocks,
peripheral groups, and peripheral itself are left uninitialized.
Introduce CONFIG_FLASH_INFINEON_SMIF_HW_INIT to conditionally
perform these steps before mtb_serial_memory_setup() is called.
Extract the info as much as possible from DT. Some are still hardcoded
in the driver and will require additional polishing in a follow-up PR.
Assisted-by: Claude:claude-opus-4.7
Signed-off-by: Laura Carlesso <laura.carlesso@infineon.com>
Encode the SF32LB52x slew-rate pinctrl property into HPSYS_PINMUX.
The devicetree value 0 selects slow slew rate and 1 selects fast
slew rate, while the hardware bit uses 1 for slow and 0 for fast.
PA39-PA42 reuse the same bit as MODE instead of SR. Mask SR out for
those pads and drive MODE separately from the selected pinctrl
function, setting it only for I2C routing and clearing it otherwise.
Signed-off-by: Haoran Jiang <halfsweet@halfsweet.cn>
Add basic SoC support for the Allwinner sun50i_h618 SoC. This includes
Kconfig definitions, SoC configuration files, and early memory map setup.
Tested by building the hello_world sample:
west build -b opi_zero2w samples/hello_world
Signed-off-by: Khai Do <dovankhai97@gmail.com>
Stop defining custom FLASH_SIZE and FLASH_BASE_ADDRESS Kconfig symbols
in the Espressif SoC tree and consume the chosen zephyr,flash node
directly from devicetree.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
There are some (many?) applications and drivers which use the GPIO API
without making sure to enable it first. Unfortunately, it is common for
boards to enable CONFIG_GPIO=y in their defconfig, which allows these
applications/drivers to work fine even though they don't explicitly
enable the GPIO drivers they depend on... except when the target does
not enable CONFIG_GPIO=y as expected, which is now the case on STM32
platforms.
Unfortunately, due to a combination of several factors, such misuses
will currently result in runtime failures on STM32 platforms that are
not immediately obvious to diagnose:
- the GPIO API is implemented entirely in headers and not gated behind
any symbol - as a result, consumers of the API will build fine and
there will be no link error due to missing subsystem code when the
GPIO subsystem is disabled
- the GPIOport manager instantiates devices regardless of CONFIG_GPIO;
as such, the `undefined reference to __device_dts_ord_NNN` link error
that would be expected to occur doesn't and images build just fine
- when CONFIG_GPIO=n, the GPIOport devices have NULL as `api` pointer
The GPIO API functions expect `dev->api` to be valid - as do functions
in every other Zephyr API - so they don't check that `dev->api != NULL`
and blindly dereference `api` which is NULL in this case. If the MPU is
enabled, this should fault immediately and could be easy to diagnose;
however, if the MPU is not enabled, the NULL dereference will (usually)
not fault and the resulting behavior is unpredictable.
Provide a dummy implementation of the GPIO API when CONFIG_GPIO=n such
that calls to the API will fail gracefully and log a clear error message
instead of causing unpredictable behavior, which should help users to
diagnose the issue and fix their configuration.
A broader rework of the GPIOport manager organization could solve this
issue by bringing back the link-time errors, but this is a much larger
effort and I'm not sure the result will be satisfactory, so let's start
with this first even though it is a bit hacky.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Inform sysbuild about the outputs of `gen_uicr` to allow creating proper
dependencies. This is supported by setting BYPRODUCT_* cache variables.
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
The nrf-mspi peripheral is intended to use DMA for almost all use-cases.
Therefore, we can enable it by default.
Signed-off-by: David Jewsbury <david.jewsbury@nordicsemi.no>
Update SoC-specific interrupt handling code to use "flags" instead
of "sense" when accessing interrupt properties from device tree.
This aligns with the updated interrupt controller bindings that now
consistently use "flags" as the cell name for the IRQ type field.
Signed-off-by: Amneesh Singh <amneesh@ti.com>
Replace CONFIG_FLASH_BASE_ADDRESS + CONFIG_FLASH_LOAD_OFFSET with
DT_MAPPED_PARTITION_ADDR(DT_CHOSEN(zephyr_code_partition)), which
is unavailable when zephyr,mapped-partition is used.
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
siwx91x has a platform specific bootloader. Therefore, mcuboot is not
supporter and the user has to use a specific API to upgrade the firmware.
This API is already available on Zephyr through
CONFIG_SIWX91X_FIRMWARE_UPGRADE. However, no example code was provided.
This patch introduces "silabs fota <URL>" shell command that can be used as
an example for firmware update implementation.
The TLS capability is not mandatory for this example. For the record, I
have tested https capability on siwx917_rb4338a with samples/net/wifi/shell
and these parameters:
CONFIG_SIWX91X_FIRMWARE_UPGRADE=y
CONFIG_NET_SOCKETS_SOCKOPT_TLS=y
CONFIG_MBEDTLS_CIPHERSUITE_TLS_ECDHE_ECDSA_WITH_CHACHA20_POLY1305_SHA256=y
CONFIG_NET_SOCKETS_TLS_CONNECT_TIMEOUT=30000
CONFIG_PSA_WANT_ALG_SHA_384=y
CONFIG_NET_BUF_RX_COUNT=80
CONFIG_MBEDTLS_SSL_IN_CONTENT_LEN=4096
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Add TDM DAI driver and ACP 7.0 register
definitions for AMD Audio Co-Processor. This includes:
- TDM DAI driver (tdm_dai.c) with support for I2S format
- ACP 7.0 chip register definitions and offset mappings
- Device tree bindings and nodes for TDM DAI instances
- Kconfig and CMake build integration
Signed-off-by: Siva Subramanian Ravi Saravanan <sravisar@amd.com>
Co-authored-by: DineshKumar Kalva <DineshKumar.Kalva@amd.com>
Fix devicetree coding style regarding whitespaces through the tree.
This affects code snippets inside documentation, comments, error messages
as to encourage a style that passes CI. Follow-up of #101619
Signed-off-by: Josuah Demangeon <me@josuah.net>
Fix systimer object linking (currently wrong name) for ESP32-C2,
ESP32-C3 and ESP32-H2, to correctly place it in IRAM.
Follows #109434.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Unlike the GIC distributor/redistributor, the GICv3 ITS is accessed
through a base mapped by its own driver via device_map() when the node
is enabled, so it never needs a static MMU entry. The agilex5 ITS node
is disabled and never accessed, making this mapping dead. Remove it.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The GIC register banks are accessed by the interrupt controller driver
through flat physical addresses before any driver can map them via the
device MMIO API, so they must be present in the page tables as soon as
the MMU is enabled. Until now every arm64 SoC had to repeat the same GIC
entries in its own mmu_regions.c to achieve this.
Map all the GIC reg banks in the arch core, generated from devicetree
and guarded by the presence of an arm,gic node, and provide a weak empty
mmu_config so a SoC that only needs the GIC no longer requires an
mmu_regions.c. Drop the now-redundant GIC entries from every arm64 SoC.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
Problem:
- When CONFIG_LTO is enabled, the boot ROM fails to recognize the
image because .image_id field in img_header is corrupted.
- LTO optimization causes the const struct img_header contents to
be modified incorrectly, breaking the image header that must be
placed at the beginning of the flash.
Fix:
- Add __attribute__((used)) to img_header to prevent LTO from
optimizing away or modifying the structure contents.
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
Added support for autanalog PRB for PSE84.
This implementation uses the shared autonomous controller (AC) MFD
with the other autanalog drivers.
The PRB is a programmable reference block inside the autonomous
(aut) analog subsystem. It is controlled using the autonomous
controller (AC), which is a programmable state machine. The AC is
shared across all autonomous analog peripherals including the
SAR, PRB, PTComp, CTB, and CTDAC.
The PRB contains two variable voltage references derived from
either VDDA(1.8V) or VGBR(0.9V). These need to be configured
together and accessed using the AC. A PRB MFD is used to bring
together the two voltage reference configurations. AC MFD then
references the combined PRB MFD configuration, and brings together
all other autanalog peripherals into a single AC setup for the
application.
Assisted-by: Claude:claude-opus-4.6
Signed-off-by: Richard Mc Sweeney <Richard.McSweeney@infineon.com>
Add Power Down mode wakeup handling in soc_early_init_hook.
Check km4_aon_boot_done flag to distinguish between normal boot
and wakeup from Power Down mode, and call appropriate PM exit
sequences.
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
ESP32 cache has no per-address invalidate primitive, so
cache_hal_invalidate_addr() aborts. Skip the flash IROM/DROM
invalidate step on ESP32 only.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Disambiguate the boot-log segment label on socs where the irom and
drom hardware address ranges overlap (esp32c5, esp32c6, esp32h2,
esp32p4). Match against the linker-provided map vaddrs first so the
correct "IROM" or "DROM" string is printed, falling back to the
range-based macros for any other mapped segment.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
These pin are currently managed by the HAL. However, for the consistency,
this patch enforces their declaration in the Device Tree.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
The Zephyr implementation (and more importantly, the version of WiseConnect
SDK used in the HAL) strictly depends on a specific version of the NWP
firmware.
However, the current check prevents the user from running a newer release
of the NWP firmware. Let's relax this test to only check if the patch
number is older than what we expect.
In addition, since we bundle a copy of the NWP firmware with Zephyr (via
west blob), there are fewer risks of mismatch than when we introduced this
restriction.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
WIFI_SILABS_SIWX91X_FEAT_HIDE_PSK_CREDENTIALS impacted the way the NWp
print the log message. However, these logs are not available on production
firmware. So, it does not make sense to expose this parameter.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Defining a Kconfig symbol several times is dangerous. It is better to use
configdefault for the CMSIS related symbols.
Bluetooth configdefault depends on NWP driver. It is more accurate to
depend on the Si91x Bluetooth driver.
Finally, configdefault is supposed to be only used in Kconfig.defconfig
files. So, relocate BT_HCI_ACL_FLOW_CONTROL.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
A flash manager thread is created and allocated to
process Flash Manager Process.
Definition of KConfigs STM32WBA_FLASH_MNGR_THREAD_STACK_SIZE,
and STM32WBA_FLASH_MNGR_THREAD_PRIO to configure the
flash manager thread.
STM32WBA_FLASH_MNGR_THREAD_STACK_SIZE is setting by default
to 768 bytes. This value was chosen empirically since reasonable
to cover generic cases.
Signed-off-by: Vincent Tardy <vincent.tardy@st.com>
Force users to explicitly opt-in to the deprecated platform symbols,
instead of enabling `DEPRECATED` symbols by default for all nRF54, nRF71
and nRF92 builds.
Fixes#109802.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Added autonomous analog CTDAC for PSE84 device.
This implementation uses the autonomous controller (MFD)
that is shared with other autanalog drivers.
The CTDAC stands for Continuous Time DAC. It is a programmable DAC
residing inside the autonomous (aut) analog subsystem. It is
controlled using the autonomous controller (AC), which is a
programmable state machine. The AC is shared across all autonomous
analog peripherals including the SAR, PRB, PTComp, CTB, and CTDAC.
The DAC output can either be software controlled or be driven
through the AC hardware by loading through an internal LUT memory.
AC MFD references the DAC configuration, and brings together all
other autanalog peripherals into a single AC setup for the application.
Assisted-by: Claude:claude-opus-4.6
Signed-off-by: Richard Mc Sweeney <Richard.McSweeney@infineon.com>
The MCXE31x SoC requires ECC-protected SRAM and TCM to be initialised
by a 64-bit master on destructive reset before any 32-bit master access
is allowed. The init routine is currently wired to soc_reset_hook,
which runs after the early portion of z_arm_reset that may already
touch SRAM.
Wire the init routine to soc_early_reset_hook instead, which is the
arch-defined hook that fires before any RAM access is performed by
reset.S. This matches what the S32K3 series does in
soc/nxp/s32/s32k3/s32k3xx_startup.S for the same hardware constraint.
The hook body itself only uses registers (no stack), as required by
the soc_early_reset_hook contract. The previous 'bl SystemInit' tail
call is moved out of this ASM hook into soc_early_init_hook in soc.c,
where the full C environment (.bss zeroed, .data copied) is guaranteed
to be ready. SystemInit comes from the NXP SDK and may touch globals,
so it must run after C startup is complete, not from within the early
reset hook.
Reported in zephyrproject-rtos/zephyr#107699.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Linker script pulls libdrivers__timer.a:esp32c6_sys_timer into
IRAM but the actual driver object is esp32_sys_timer, so the
match fails and the timer code stays in flash. Update the
pattern to esp32_sys_timer.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
