Implement comprehensive Memory Protection Unit (MPU) support for
Xilinx Versal RPU with the following enhancements:
MPU Region Configuration:
- Add arm_mpu_regions.c with MPU region definitions supporting
multiple memory layouts:
* TCM-only layout
* Contiguous DDR layout
* Non-contiguous DDR layout for Linux shared memory scenarios
- Configure memory regions for PL, PS peripherals, and DDR with
appropriate memory attributes (Normal, Device, Strongly-ordered)
SoC Initialization:
- Add soc_early_init_hook() for instruction and data cache
enablement during early boot
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
Remove the unused CRL_RST_TTC register address definition from soc.h.
This macro is not referenced anywhere in the codebase.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
Regroup the Kconfig.defconfig.<soc> files of various series which have
identical contents for all SoCs into the per-series root file instead
(stm32XXx/Kconfig.defconfig). This reduces the number of files and is
easier to understand.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Add DT helper file for PIC32CM-PL family devices to support
SoC-specific device tree definitions and utilities.
Signed-off-by: Arunprasath P <arunprasath.p@microchip.com>
Add CONFIG_SOC_NRF71_WIFI_BOOT, so that ns sample does not start Wi-Fi,
this is because wicr and lmac is initialised to some gibberish value
when it is not loaded this breaks the CI.
Signed-off-by: Travis Lam <travis.lam@nordicsemi.no>
On siwx91x, no data cache is associated with the main flash. Therefore,
all accesses to data stored in flash penalizes performances (22 CPU cycles
for 1 data access). This patch allow the user to enable
CONFIG_SLOW_FLASH_DATA
The benefit of this option depends of the workload. Some kernel benchmarks
(tests/benchmarks/app_kernel/) run up to 300% faster, while the typical
improvement is around 10-50%.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
RAIL depends on the LDMA and TIMER peripherals when Bluetooth Channel
Sounding support has been enabled, so be sure to include those in the
build for such configurations.
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
The clock initialization for RX devices is not appropriate when it is
placed under the root clock node. Without an external fixed clock on the
board, the clock is never initialized. Therefore, the clock
setup must be handled inside soc_early_init_hook.
Signed-off-by: Y Huynh <y.huynh.xw@renesas.com>
Add BLEPLAT_AesCcmCrypt() function required by
the stm32wba ble library in the release
STM32Cube_FW_WBA_V1.8.0
Signed-off-by: Vincent Tardy <vincent.tardy@st.com>
Kconfig enhancement for mcx series
MCXN: adds comments + begins splitting MCXN547 vs MCXN547_CPU0
(to reflect per-core feature differences similarly).
MCXW2xx: adds new part number MCXW235BIHNAR,
and moves CPU feature selects into the series Kconfig.
Signed-off-by: Hake Huang <hake.huang@nxp.com>
The NUM_IRQS value for MCXW2xx was incorrectly set to 63. According to
the device reference manual, the correct number of interrupts is 61.
Fixes: #98279
Signed-off-by: Jason Yu <zejiang.yu@nxp.com>
Includes file for mapping DFP macros to follow a common
macro name for sercom uart g1 driver
Signed-off-by: Fabin V Martin <Fabinv.Martin@microchip.com>
Add config SOC_RA_DYNAMIC_INTERRUPT_NUMBER to indicate the SoC
support the dynamic interrupt number assignment feature.
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Add DT helper file for PIC32CM-JH family devices to support
SoC-specific device tree definitions and utilities.
Signed-off-by: Arunprasath P <arunprasath.p@microchip.com>
Add support for configuring lfxo external clock source based on
lfxo configuration in devicetree. The addition both selects
bypass mode if external-clock-source is set, and adds a build
assert to catch invalid configuration of internal load capacitors
in case external-clock-source is used.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Add support for the Ensemble E4 series and the AE402FA0E5597LE0
SoC within this series. The SoC contains two Cortex-M55 cores:
one configured to maximize power efficiency (RTSS-HE - High
Efficiency Real Time Subsystem) and the other to maximize compute
performance (RTSS-HP - High Performance Real Time Subsystem).
The E4 series uses SOC_FAMILY_ENSEMBLE_RTSS helper symbol
introduced earlier to share the CPU architecture configuration
with the E6 and E8 series.
Link: https://alifsemi.com/products/ensemblegenai/
Link: https://alifsemi.com/ensemble-e4-series/
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Add support for the Ensemble E6 series and the AE612FA0E5597LS0
SoC within this series. The SoC contains two Cortex-M55 cores:
one configured to maximize power efficiency (RTSS-HE - High
Efficiency Real Time Subsystem) and the other to maximize compute
performance (RTSS-HP - High Performance Real Time Subsystem).
The E6 series uses SOC_FAMILY_ENSEMBLE_RTSS helper symbol
introduced earlier to share the CPU architecture configuration
with the E8 series.
Link: https://alifsemi.com/products/ensemblegenai/
Link: https://alifsemi.com/ensemble-e6-series/
Signed-off-by: Silesh C V <silesh@alifsemi.com>
All RTSS cores in the E4, E6 and E8 series SoCs in the Alif
Ensemble family share identical Cortex-M55 CPU configuration.
Introduce SOC_FAMILY_ENSEMBLE_RTSS helper symbol at the family
level to avoid duplicating these selects across series Kconfigs.
The helper will be reused by the E4 and E6 series being added in
subsequent patches.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
When the received data is less than expected, DMA timeout error may occur.
This happens because the DMA transfer is not completed and the TC
(Transfer Complete) flag is never set.
This change adds support for handling cases where the received data length
is smaller than the requested length, preventing false timeout errors.
The CL covers the following scenarios:
1. received < expected (e.g. requested 10 bytes, got 9 bytes)
2. received = expected (e.g. requested 10 bytes, got 10 bytes)
3. received > expected
(e.g. requested 10 bytes, got 10 bytes, but more data is coming, T-bit = 1)
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
- Adds missing flash runner configuration for mcxn/e/w
used for sysbuild multi-image projects.
- Avoids sysbuild multiple resets and mass erases.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
The nrf54l soc init configures power and clock properties like
applying trims, capacitance and setting up regulators. This must
precede the grtc driver initializing the sys clock, as it depends
on these clocks being initialized on the nrf54l series socs.
Update the nrf54l soc init to be EARLY 0, and set grtc sys clock
driver init to EARLY 1. Additionally add comments explaining why
these specific init levels where chosen.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Add initialization ofcritical components for the RTL87x2G
series.
Key initializations include:
- Realtek OS abstraction layer.
- Clock active mode settings.
- Power Management (PM) and dynamic voltage scaling (DVFS).
- PHY and thermal compensation modules.
- Bluetooth controller ROM initialization.
Note: A mechanism is introduced to synchronize the RAM Vector Table between
Realtek's ROM code (which writes raw ISRs) and Zephyr's interrupt
management subsystem (sw_isr_table).
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
This commit introduces the Realtek OSIF (Operating System Interface)
layer, which is the standard OS abstraction layer defined for the
Realtek Bee SoC family.
While OSIF is designed to be common across the Bee SoC family, this
specific implementation adapts the layer for the RTL87x2G series
running on Zephyr.
OSIF encapsulates specific RTOS interfaces to provide a unified API.
This enables Realtek-specific modules—such as PHY, Power Manager,
Clock Manager, and BT Controller—to run on different RTOS environments
without modification, significantly enhancing portability.
The OSIF adaptation maps the following fundamental components to their
corresponding Zephyr kernel APIs:
- Task management and Scheduling
- Message queues
- Synchronization (Semaphores, Mutexes)
- Software timers
- Memory management
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
Add support for MediaTek MT8365 SoC. This includes adding basic
initialization code, IRQ handling, IPI driver, MPU configuration,
and necessary build system files.
Signed-off-by: Andrew Perepech <andrew.perepech@mediatek.com>
Add dtc property node on RX26T dts, and ram section for
dtc_vector_table on RX26T SoC for dtc support
Signed-off-by: Quy Tran <quy.tran.pz@renesas.com>
LVGL BITS_PER_PIXEL and COLOR_DEPTH are closely linked to how the LTDC
is configured on the platform. Move all all STM32 common LVGL
configuration into the common stm32 Kconfig.defconfig.
CONFIG_LV_DPI_DEF and CONFIG_INPUT are application related.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Enable CONFIG_SHARED_INTERRUPTS to allow multiple devices
to register handlers on the same IRQ line.
Replace irq_connect_dynamic() with IRQ_CONNECT() to configure
interrupts at build time, eliminating runtime setup overhead.
Signed-off-by: Manojkumar Konisetty <manoj@aerlync.com>
Signed-off-by: Sayooj K Karun <sayooj@aerlync.com>
- Update low power state exit latency to match SDK
- Enable NBU wakeup source
- Configure 32MHz crystal osc
- Shutdown NBU when it's not used
Signed-off-by: Yassine El Aissaoui <yassine.elaissaoui@nxp.com>
Calibration correction applied to the Fast Internal Reference Clock (FIRC)
configuration in the MCXw7xx System-on-Chip to address OSC32K oscillator
drift issues.
Signed-off-by: Xavier Razavet <xavier.razavet@nxp.com>
