drivers: firmware: scmi: add cpu domain protocol

Added helpers for NXP SCMI cpu dmomain protocol.

Signed-off-by: Qiang Zhao <qiang.zhao@nxp.com>
This commit is contained in:
Qiang Zhao 2025-03-07 09:19:52 +05:30 committed by Benjamin Cabé
commit c412ee4597
7 changed files with 177 additions and 0 deletions

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@ -139,6 +139,8 @@ Currently, Zephyr has support for the following standard protocols:
#. **Clock management**
#. **Pin Control**
NXP-specific protocols:
#. **CPU domain management**
Power domain management
***********************
@ -178,6 +180,16 @@ supported command is ``PINCTRL_SETTINGS_CONFIGURE``.
call into the SCMI pin control protocol function implementing the
``PINCTRL_SETTINGS_CONFIGURE`` command.
NXP - CPU domain management
***************************
This protocol is intended for management of cpu states.
This is done via a set of functions implementing various commands, for
example, ``CPU_SLEEP_MODE_SET``.
.. note::
This driver is NXP-specific. As such, it may only be used on NXP
system that uses SCMI for cpu domain management operations.
Enabling the SCMI support
*************************

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@ -1,3 +1,5 @@
# SPDX-License-Identifier: Apache-2.0
zephyr_library()
zephyr_library_sources_ifdef(CONFIG_ARM_SCMI_NXP_VENDOR_EXTENSIONS shmem.c)
zephyr_library_sources_ifdef(CONFIG_NXP_SCMI_CPU_DOMAIN_HELPERS cpu.c)

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@ -6,3 +6,14 @@ config ARM_SCMI_NXP_VENDOR_EXTENSIONS
select CRC
help
When enabled, additional SCMI features specific to NXP will be available
if ARM_SCMI_NXP_VENDOR_EXTENSIONS
config NXP_SCMI_CPU_DOMAIN_HELPERS
bool "Helper functions for SCMI cpu domain protocol"
default y
depends on DT_HAS_NXP_SCMI_CPU_ENABLED
help
Enable support for SCMI cpu domain protocol helper functions.
endif # ARM_SCMI_NXP_VENDOR_EXTENSIONS

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@ -0,0 +1,46 @@
/*
* Copyright 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <string.h>
#include <zephyr/drivers/firmware/scmi/nxp/cpu.h>
DT_SCMI_PROTOCOL_DEFINE_NODEV(DT_INST(0, nxp_scmi_cpu), NULL);
int scmi_cpu_sleep_mode_set(struct scmi_cpu_sleep_mode_config *cfg)
{
struct scmi_protocol *proto = &SCMI_PROTOCOL_NAME(SCMI_PROTOCOL_CPU_DOMAIN);
struct scmi_message msg, reply;
int status, ret;
/* sanity checks */
if (!proto || !cfg) {
return -EINVAL;
}
if (proto->id != SCMI_PROTOCOL_CPU_DOMAIN) {
return -EINVAL;
}
msg.hdr = SCMI_MESSAGE_HDR_MAKE(SCMI_CPU_DOMAIN_MSG_CPU_SLEEP_MODE_SET, SCMI_COMMAND,
proto->id, 0x0);
msg.len = sizeof(*cfg);
msg.content = cfg;
reply.hdr = msg.hdr;
reply.len = sizeof(status);
reply.content = &status;
ret = scmi_send_message(proto, &msg, &reply);
if (ret < 0) {
return ret;
}
if (status != SCMI_SUCCESS) {
return scmi_status_to_errno(status);
}
return 0;
}

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@ -0,0 +1,13 @@
# Copyright 2025 NXP
# SPDX-License-Identifier: Apache-2.0
description: System Control and Management Interface (SCMI) cpu domain protocol
compatible: "nxp,scmi-cpu"
include: [base.yaml]
properties:
reg:
required: true
const: [0x82]

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@ -0,0 +1,67 @@
/*
* Copyright 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief SCMI power domain protocol helpers
*/
#ifndef _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_CPU_H_
#define _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_CPU_H_
#include <zephyr/drivers/firmware/scmi/protocol.h>
#if __has_include("scmi_cpu_soc.h")
#include <scmi_cpu_soc.h>
#endif
#define SCMI_CPU_SLEEP_FLAG_IRQ_MUX 0x1U
#define SCMI_PROTOCOL_CPU_DOMAIN 130
/**
* @struct scmi_cpu_sleep_mode_config
*
* @brief Describes the parameters for the CPU_STATE_SET
* command
*/
struct scmi_cpu_sleep_mode_config {
uint32_t cpu_id;
uint32_t flags;
uint32_t sleep_mode;
};
/**
* @brief CPU domain protocol command message IDs
*/
enum scmi_cpu_domain_message {
SCMI_CPU_DOMAIN_MSG_PROTOCOL_VERSION = 0x0,
SCMI_CPU_DOMAIN_MSG_PROTOCOL_ATTRIBUTES = 0x1,
SCMI_CPU_DOMAIN_MSG_PROTOCOL_MESSAGE_ATTRIBUTES = 0x2,
SCMI_CPU_DOMAIN_MSG_CPU_DOMAIN_ATTRIBUTES = 0x3,
SCMI_CPU_DOMAIN_MSG_CPU_START = 0x4,
SCMI_CPU_DOMAIN_MSG_CPU_STOP = 0x5,
SCMI_CPU_DOMAIN_MSG_CPU_RESET_VECTOR_SET = 0x6,
SCMI_CPU_DOMAIN_MSG_CPU_SLEEP_MODE_SET = 0x7,
SCMI_CPU_DOMAIN_MSG_CPU_IRQ_WAKE_SET = 0x8,
SCMI_CPU_DOMAIN_MSG_CPU_NON_IRQ_WAKE_SET = 0x9,
SCMI_CPU_DOMAIN_MSG_CPU_PD_LPM_CONFIG_SET = 0xA,
SCMI_CPU_DOMAIN_MSG_CPU_PER_LPM_CONFIG_SET = 0xB,
SCMI_CPU_DOMAIN_MSG_CPU_INFO_GET = 0xC,
SCMI_CPU_DOMAIN_MSG_NEGOTIATE_PROTOCOL_VERSION = 0x10,
};
/**
* @brief Send the CPU_SLEEP_MODE_SET command and get its reply
*
* @param cfg pointer to structure containing configuration
* to be set
*
* @retval 0 if successful
* @retval negative errno if failure
*/
int scmi_cpu_sleep_mode_set(struct scmi_cpu_sleep_mode_config *cfg);
#endif /* _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_CPU_H_ */

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@ -0,0 +1,26 @@
/*
* Copyright 2025 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_NXP_IMX95_SCMI_CPU_SOC_H_
#define ZEPHYR_NXP_IMX95_SCMI_CPU_SOC_H_
#define CPU_IDX_M33P 0U
#define CPU_IDX_M7P 1U
#define CPU_IDX_A55C0 2U
#define CPU_IDX_A55C1 3U
#define CPU_IDX_A55C2 4U
#define CPU_IDX_A55C3 5U
#define CPU_IDX_A55C4 6U
#define CPU_IDX_A55C5 7U
#define CPU_IDX_A55P 8U
#define CPU_NUM_IDX 9U
#define CPU_SLEEP_MODE_RUN 0U
#define CPU_SLEEP_MODE_WAIT 1U
#define CPU_SLEEP_MODE_STOP 2U
#define CPU_SLEEP_MODE_SUSPEND 3U
#endif /* ZEPHYR_NXP_IMX95_SCMI_CPU_SOC_H_ */