drivers: firmware: scmi: add cpu domain protocol
Added helpers for NXP SCMI cpu dmomain protocol. Signed-off-by: Qiang Zhao <qiang.zhao@nxp.com>
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@ -139,6 +139,8 @@ Currently, Zephyr has support for the following standard protocols:
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#. **Clock management**
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#. **Pin Control**
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NXP-specific protocols:
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#. **CPU domain management**
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Power domain management
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***********************
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@ -178,6 +180,16 @@ supported command is ``PINCTRL_SETTINGS_CONFIGURE``.
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call into the SCMI pin control protocol function implementing the
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``PINCTRL_SETTINGS_CONFIGURE`` command.
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NXP - CPU domain management
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***************************
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This protocol is intended for management of cpu states.
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This is done via a set of functions implementing various commands, for
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example, ``CPU_SLEEP_MODE_SET``.
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.. note::
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This driver is NXP-specific. As such, it may only be used on NXP
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system that uses SCMI for cpu domain management operations.
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Enabling the SCMI support
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*************************
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@ -1,3 +1,5 @@
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# SPDX-License-Identifier: Apache-2.0
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zephyr_library()
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zephyr_library_sources_ifdef(CONFIG_ARM_SCMI_NXP_VENDOR_EXTENSIONS shmem.c)
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zephyr_library_sources_ifdef(CONFIG_NXP_SCMI_CPU_DOMAIN_HELPERS cpu.c)
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@ -6,3 +6,14 @@ config ARM_SCMI_NXP_VENDOR_EXTENSIONS
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select CRC
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help
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When enabled, additional SCMI features specific to NXP will be available
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if ARM_SCMI_NXP_VENDOR_EXTENSIONS
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config NXP_SCMI_CPU_DOMAIN_HELPERS
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bool "Helper functions for SCMI cpu domain protocol"
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default y
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depends on DT_HAS_NXP_SCMI_CPU_ENABLED
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help
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Enable support for SCMI cpu domain protocol helper functions.
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endif # ARM_SCMI_NXP_VENDOR_EXTENSIONS
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46
drivers/firmware/scmi/nxp/cpu.c
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46
drivers/firmware/scmi/nxp/cpu.c
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@ -0,0 +1,46 @@
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/*
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* Copyright 2025 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <string.h>
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#include <zephyr/drivers/firmware/scmi/nxp/cpu.h>
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DT_SCMI_PROTOCOL_DEFINE_NODEV(DT_INST(0, nxp_scmi_cpu), NULL);
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int scmi_cpu_sleep_mode_set(struct scmi_cpu_sleep_mode_config *cfg)
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{
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struct scmi_protocol *proto = &SCMI_PROTOCOL_NAME(SCMI_PROTOCOL_CPU_DOMAIN);
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struct scmi_message msg, reply;
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int status, ret;
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/* sanity checks */
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if (!proto || !cfg) {
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return -EINVAL;
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}
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if (proto->id != SCMI_PROTOCOL_CPU_DOMAIN) {
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return -EINVAL;
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}
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msg.hdr = SCMI_MESSAGE_HDR_MAKE(SCMI_CPU_DOMAIN_MSG_CPU_SLEEP_MODE_SET, SCMI_COMMAND,
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proto->id, 0x0);
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msg.len = sizeof(*cfg);
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msg.content = cfg;
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reply.hdr = msg.hdr;
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reply.len = sizeof(status);
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reply.content = &status;
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ret = scmi_send_message(proto, &msg, &reply);
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if (ret < 0) {
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return ret;
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}
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if (status != SCMI_SUCCESS) {
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return scmi_status_to_errno(status);
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}
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return 0;
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}
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13
dts/bindings/firmware/nxp,scmi-cpu.yaml
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dts/bindings/firmware/nxp,scmi-cpu.yaml
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# Copyright 2025 NXP
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# SPDX-License-Identifier: Apache-2.0
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description: System Control and Management Interface (SCMI) cpu domain protocol
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compatible: "nxp,scmi-cpu"
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include: [base.yaml]
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properties:
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reg:
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required: true
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const: [0x82]
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67
include/zephyr/drivers/firmware/scmi/nxp/cpu.h
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include/zephyr/drivers/firmware/scmi/nxp/cpu.h
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@ -0,0 +1,67 @@
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/*
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* Copyright 2025 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief SCMI power domain protocol helpers
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*/
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#ifndef _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_CPU_H_
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#define _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_CPU_H_
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#include <zephyr/drivers/firmware/scmi/protocol.h>
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#if __has_include("scmi_cpu_soc.h")
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#include <scmi_cpu_soc.h>
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#endif
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#define SCMI_CPU_SLEEP_FLAG_IRQ_MUX 0x1U
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#define SCMI_PROTOCOL_CPU_DOMAIN 130
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/**
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* @struct scmi_cpu_sleep_mode_config
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*
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* @brief Describes the parameters for the CPU_STATE_SET
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* command
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*/
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struct scmi_cpu_sleep_mode_config {
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uint32_t cpu_id;
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uint32_t flags;
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uint32_t sleep_mode;
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};
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/**
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* @brief CPU domain protocol command message IDs
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*/
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enum scmi_cpu_domain_message {
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SCMI_CPU_DOMAIN_MSG_PROTOCOL_VERSION = 0x0,
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SCMI_CPU_DOMAIN_MSG_PROTOCOL_ATTRIBUTES = 0x1,
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SCMI_CPU_DOMAIN_MSG_PROTOCOL_MESSAGE_ATTRIBUTES = 0x2,
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SCMI_CPU_DOMAIN_MSG_CPU_DOMAIN_ATTRIBUTES = 0x3,
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SCMI_CPU_DOMAIN_MSG_CPU_START = 0x4,
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SCMI_CPU_DOMAIN_MSG_CPU_STOP = 0x5,
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SCMI_CPU_DOMAIN_MSG_CPU_RESET_VECTOR_SET = 0x6,
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SCMI_CPU_DOMAIN_MSG_CPU_SLEEP_MODE_SET = 0x7,
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SCMI_CPU_DOMAIN_MSG_CPU_IRQ_WAKE_SET = 0x8,
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SCMI_CPU_DOMAIN_MSG_CPU_NON_IRQ_WAKE_SET = 0x9,
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SCMI_CPU_DOMAIN_MSG_CPU_PD_LPM_CONFIG_SET = 0xA,
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SCMI_CPU_DOMAIN_MSG_CPU_PER_LPM_CONFIG_SET = 0xB,
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SCMI_CPU_DOMAIN_MSG_CPU_INFO_GET = 0xC,
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SCMI_CPU_DOMAIN_MSG_NEGOTIATE_PROTOCOL_VERSION = 0x10,
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};
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/**
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* @brief Send the CPU_SLEEP_MODE_SET command and get its reply
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*
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* @param cfg pointer to structure containing configuration
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* to be set
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*
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* @retval 0 if successful
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* @retval negative errno if failure
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*/
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int scmi_cpu_sleep_mode_set(struct scmi_cpu_sleep_mode_config *cfg);
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#endif /* _INCLUDE_ZEPHYR_DRIVERS_FIRMWARE_SCMI_CPU_H_ */
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soc/nxp/imx/imx9/imx95/scmi_cpu_soc.h
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soc/nxp/imx/imx9/imx95/scmi_cpu_soc.h
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/*
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* Copyright 2025 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_NXP_IMX95_SCMI_CPU_SOC_H_
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#define ZEPHYR_NXP_IMX95_SCMI_CPU_SOC_H_
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#define CPU_IDX_M33P 0U
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#define CPU_IDX_M7P 1U
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#define CPU_IDX_A55C0 2U
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#define CPU_IDX_A55C1 3U
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#define CPU_IDX_A55C2 4U
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#define CPU_IDX_A55C3 5U
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#define CPU_IDX_A55C4 6U
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#define CPU_IDX_A55C5 7U
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#define CPU_IDX_A55P 8U
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#define CPU_NUM_IDX 9U
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#define CPU_SLEEP_MODE_RUN 0U
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#define CPU_SLEEP_MODE_WAIT 1U
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#define CPU_SLEEP_MODE_STOP 2U
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#define CPU_SLEEP_MODE_SUSPEND 3U
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#endif /* ZEPHYR_NXP_IMX95_SCMI_CPU_SOC_H_ */
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