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soc: cva6: Implement missing cache management APIs

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In hardware, cva6 currently only provides global disable/enable
functions for the Dcache and Icache. Disabling and re-enabling them also
has the effect of flushing and invalidating the cache.
Future cva6 SoCs will add support RISC-V's standardized cache management
operations.
This commit provides a default implementation for all methods currently
part of the cache API. These implementations can be overwritten at board
or SoC level, as they use weak linking.

Signed-off-by: Eric Ackermann <eric.ackermann@cispa.de>
This commit is contained in:
Eric Ackermann 2025-04-11 18:18:39 +02:00 • committed by Benjamin Cabé
commit 6ba7691e96
3 changed files with 87 additions and 4 deletions
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2
soc/openhwgroup/cva6/CMakeLists.txt
View file

@ -3,6 +3,6 @@
add_subdirectory(${SOC_SERIES})
zephyr_library_sources_ifdef(CONFIG_SOC_FAMILY_CVA6_PROVIDE_NONSTANDARD_CACHE_OPTIONS soc_cache_management.c)
zephyr_library_sources_ifdef(CONFIG_CACHE_MANAGEMENT soc_cache_management.c)
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/riscv/common/linker.ld CACHE INTERNAL "")

3
soc/openhwgroup/cva6/Kconfig
View file

@ -3,9 +3,6 @@
if SOC_FAMILY_OPENHWGROUP_CVA6
config SOC_FAMILY_CVA6_PROVIDE_NONSTANDARD_CACHE_OPTIONS
bool "Include non-standard cache management operations (currently global cache disable)"
rsource "*/Kconfig"
endif # SOC_FAMILY_OPENHWGROUP_CVA6

86
soc/openhwgroup/cva6/soc_cache_management.c
View file

@ -21,6 +21,49 @@ void __weak arch_dcache_disable(void)
csr_write(SOC_CVA6_CUSTOM_CSR_DCACHE, SOC_CVA6_CUSTOM_CSR_DCACHE_DISABLE);
}
int __weak arch_dcache_flush_all(void)
{
arch_dcache_disable();
arch_dcache_enable();
return 0;
}
int __weak arch_dcache_invd_all(void)
{
return arch_dcache_flush_all();
}
int __weak arch_dcache_flush_and_invd_all(void)
{
return arch_dcache_flush_all();
}
/* FIXME currently not supported by all CVA6 - overwrite at board or SoC level */
int __weak arch_dcache_flush_range(void *addr, size_t size)
{
ARG_UNUSED(addr);
ARG_UNUSED(size);
return arch_dcache_flush_all();
}
int __weak arch_dcache_invd_range(void *addr, size_t size)
{
ARG_UNUSED(addr);
ARG_UNUSED(size);
return arch_dcache_flush_all();
}
int __weak arch_dcache_flush_and_invd_range(void *addr, size_t size)
{
ARG_UNUSED(addr);
ARG_UNUSED(size);
return arch_dcache_flush_all();
}
void __weak arch_icache_enable(void)
{
csr_write(SOC_CVA6_CUSTOM_CSR_ICACHE, SOC_CVA6_CUSTOM_CSR_ICACHE_ENABLE);
@ -31,6 +74,49 @@ void __weak arch_icache_disable(void)
csr_write(SOC_CVA6_CUSTOM_CSR_ICACHE, SOC_CVA6_CUSTOM_CSR_ICACHE_DISABLE);
}
int __weak arch_icache_flush_all(void)
{
arch_icache_disable();
arch_icache_enable();
return 0;
}
int __weak arch_icache_invd_all(void)
{
return arch_icache_flush_all();
}
int __weak arch_icache_flush_and_invd_all(void)
{
return arch_icache_flush_all();
}
/* FIXME currently not supported by all CVA6 - overwrite at board or SoC level */
int __weak arch_icache_flush_range(void *addr, size_t size)
{
ARG_UNUSED(addr);
ARG_UNUSED(size);
return arch_icache_flush_all();
}
int __weak arch_icache_invd_range(void *addr, size_t size)
{
ARG_UNUSED(addr);
ARG_UNUSED(size);
return arch_icache_flush_all();
}
int __weak arch_icache_flush_and_invd_range(void *addr, size_t size)
{
ARG_UNUSED(addr);
ARG_UNUSED(size);
return arch_icache_flush_all();
}
/* FIXME there is no common implementation for RISC-V, so we provide a SoC-level definition */
/* this prevents a linker error when the function is not defined */
void __weak arch_cache_init(void)