soc: arm: ambiq: apollo510: Add support for Apollo510 SoC
Add all required parts (new SoC family/series, device tree) for the Ambiq Apollo510 SoC. Signed-off-by: Hao Luo <hluo@ambiq.com>
This commit is contained in:
parent
eaa1addb5e
commit
c188125165
13 changed files with 580 additions and 2 deletions
276
dts/arm/ambiq/ambiq_apollo510.dtsi
Normal file
276
dts/arm/ambiq/ambiq_apollo510.dtsi
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@ -0,0 +1,276 @@
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/* Copyright (c) 2025 Ambiq Micro Inc. */
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/* SPDX-License-Identifier: Apache-2.0 */
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#include <arm/armv8.1-m.dtsi>
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#include <mem.h>
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#include <freq.h>
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#include <apollo510/am_apollo510.h>
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#include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
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#include <zephyr/dt-bindings/adc/adc.h>
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#include <zephyr/dt-bindings/i2c/i2c.h>
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#include <zephyr/dt-bindings/gpio/gpio.h>
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/ {
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clocks {
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uartclk: apb-pclk {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(24)>;
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#clock-cells = <0>;
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};
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xo32m_xtal: xo32m_xtal {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(32)>;
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#clock-cells = <0>;
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};
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xo32m_ext: xo32m_ext {
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compatible = "fixed-clock";
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clock-frequency = <DT_FREQ_M(32)>;
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#clock-cells = <0>;
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};
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xo32k_xtal: xo32k_xtal {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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};
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xo32k_ext: xo32k_ext {
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compatible = "fixed-clock";
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clock-frequency = <32768>;
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#clock-cells = <0>;
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};
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extrefclk: extrefclk {
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compatible = "fixed-clock";
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clock-frequency = <0>;
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#clock-cells = <0>;
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};
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m55";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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cpu-power-states = <&idle &suspend_to_ram>;
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itm: itm@e0000000 {
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compatible = "arm,armv8m-itm";
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reg = <0xe0000000 0x1000>;
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swo-ref-frequency = <DT_FREQ_M(48)>;
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};
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mpu: mpu@e000ed90 {
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compatible = "arm,armv8m.1-mpu";
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reg = <0xe000ed90 0x40>;
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};
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};
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power-states {
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idle: idle {
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compatible = "zephyr,power-state";
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power-state-name = "suspend-to-idle";
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min-residency-us = <2000>;
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exit-latency-us = <5>;
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};
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suspend_to_ram: suspend_to_ram {
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compatible = "zephyr,power-state";
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power-state-name = "suspend-to-ram";
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min-residency-us = <5000>;
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exit-latency-us = <125>;
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};
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};
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};
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/* MRAM region */
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flash0: flash@MRAM_BASE_NAME {
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compatible = "soc-nv-flash";
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reg = <MRAM_BASE_ADDR MRAM_MAX_SIZE>;
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};
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/* TCM */
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itcm: itcm@ITCM_BASE_NAME {
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compatible = "zephyr,memory-region";
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reg = <ITCM_BASE_ADDR ITCM_MAX_SIZE>;
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zephyr,memory-region = "ITCM";
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};
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dtcm: dtcm@DTCM_BASE_NAME {
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compatible = "zephyr,memory-region";
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reg = <DTCM_BASE_ADDR DTCM_MAX_SIZE>;
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zephyr,memory-region = "DTCM";
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};
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/* SRAM */
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sram: memory@SSRAM_BASE_NAME {
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compatible = "mmio-sram";
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reg = <SSRAM_BASE_ADDR SSRAM_MAX_SIZE>;
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};
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soc {
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compatible = "ambiq,apollo510", "ambiq,apollo5x", "simple-bus";
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pwrcfg: pwrcfg@PWRCTRL_BASE_NAME {
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compatible = "ambiq,pwrctrl";
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reg = <PWRCTRL_REG_BASE PWRCTRL_REG_SIZE>;
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#pwrcfg-cells = <2>;
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};
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stimer0: stimer@STIMER_BASE_NAME {
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compatible = "ambiq,stimer";
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reg = <STIMER_REG_BASE STIMER_REG_SIZE>;
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interrupts = <32 0>;
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status = "okay";
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};
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wdt0: watchdog@WDT_BASE_NAME {
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compatible = "ambiq,watchdog";
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reg = <WDT_REG_BASE WDT_REG_SIZE>;
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interrupts = <1 0>;
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clock-frequency = <16>;
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status = "disabled";
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};
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uart0: uart@UART0_BASE_NAME {
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compatible = "ambiq,uart", "arm,pl011";
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reg = <UART0_REG_BASE UART0_REG_SIZE>;
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interrupts = <15 0>;
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interrupt-names = "UART0";
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status = "disabled";
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clocks = <&uartclk>;
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ambiq,pwrcfg = <&pwrcfg 0x4 0x200>;
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};
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uart1: uart@UART1_BASE_NAME {
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compatible = "ambiq,uart", "arm,pl011";
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reg = <UART1_REG_BASE UART1_REG_SIZE>;
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interrupts = <16 0>;
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interrupt-names = "UART1";
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status = "disabled";
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clocks = <&uartclk>;
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ambiq,pwrcfg = <&pwrcfg 0x4 0x400>;
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};
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uart2: uart@UART2_BASE_NAME {
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compatible = "ambiq,uart", "arm,pl011";
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reg = <UART2_REG_BASE UART2_REG_SIZE>;
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interrupts = <17 0>;
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interrupt-names = "UART2";
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status = "disabled";
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clocks = <&uartclk>;
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ambiq,pwrcfg = <&pwrcfg 0x4 0x800>;
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};
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uart3: uart@UART3_BASE_NAME {
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compatible = "ambiq,uart", "arm,pl011";
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reg = <UART3_REG_BASE UART3_REG_SIZE>;
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interrupts = <18 0>;
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interrupt-names = "UART3";
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status = "disabled";
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clocks = <&uartclk>;
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ambiq,pwrcfg = <&pwrcfg 0x4 0x1000>;
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};
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pinctrl: pin-controller@GPIO_BASE_NAME {
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compatible = "ambiq,apollo5-pinctrl";
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reg = <GPIO_REG_BASE GPIO_REG_SIZE>;
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#address-cells = <1>;
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#size-cells = <0>;
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gpio: gpio@GPIO_BASE_NAME {
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compatible = "ambiq,gpio";
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gpio-map-mask = <0xffffffe0 0xffffffc0>;
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gpio-map-pass-thru = <0x1f 0x3f>;
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gpio-map = <
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0x00 0x0 &gpio0_31 0x0 0x0
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0x20 0x0 &gpio32_63 0x0 0x0
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0x40 0x0 &gpio64_95 0x0 0x0
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0x60 0x0 &gpio96_127 0x0 0x0
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0x80 0x0 &gpio128_159 0x0 0x0
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0xA0 0x0 &gpio160_191 0x0 0x0
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0xC0 0x0 &gpio192_223 0x0 0x0
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>;
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reg = <GPIO_REG_BASE>;
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#gpio-cells = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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ranges;
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gpio0_31: gpio0_31@0 {
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compatible = "ambiq,gpio-bank";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0>;
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interrupts = <56 0>;
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status = "disabled";
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};
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gpio32_63: gpio32_63@80 {
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compatible = "ambiq,gpio-bank";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x80>;
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interrupts = <57 0>;
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status = "disabled";
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};
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gpio64_95: gpio64_95@100 {
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compatible = "ambiq,gpio-bank";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x100>;
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interrupts = <58 0>;
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status = "disabled";
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};
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gpio96_127: gpio96_127@180 {
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compatible = "ambiq,gpio-bank";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x180>;
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interrupts = <59 0>;
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status = "disabled";
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};
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gpio128_159: gpio128_159@200 {
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compatible = "ambiq,gpio-bank";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x200>;
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interrupts = <60 0>;
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status = "disabled";
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};
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gpio160_191: gpio160_191@280 {
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compatible = "ambiq,gpio-bank";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x280>;
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interrupts = <61 0>;
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status = "disabled";
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};
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gpio192_223: gpio192_223@300 {
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compatible = "ambiq,gpio-bank";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x300>;
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interrupts = <62 0>;
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status = "disabled";
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};
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};
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <4>;
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};
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@ -5,7 +5,7 @@
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config AMBIQ_HAL
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bool "Ambiq HAL drivers support"
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depends on SOC_SERIES_APOLLO3X || SOC_SERIES_APOLLO4X
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depends on SOC_SERIES_APOLLO3X || SOC_SERIES_APOLLO4X || SOC_SERIES_APOLLO5X
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help
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Use the Ambiq HAL
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11
soc/ambiq/apollo5x/CMakeLists.txt
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11
soc/ambiq/apollo5x/CMakeLists.txt
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# Copyright (c) 2025 Ambiq Micro Inc.
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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zephyr_sources(soc.c)
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zephyr_include_directories(.)
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zephyr_sources_ifdef(CONFIG_PM power.c)
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zephyr_include_directories(${ZEPHYR_BASE}/soc/arm/common/cortex_m)
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
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21
soc/ambiq/apollo5x/Kconfig
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soc/ambiq/apollo5x/Kconfig
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# SPDX-License-Identifier: Apache-2.0
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#
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# Copyright (c) 2025 Ambiq Micro Inc.
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config SOC_SERIES_APOLLO5X
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select ARM
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select CPU_CORTEX_M55
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select CPU_CORTEX_M_HAS_DWT
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select CPU_CORTEX_M_HAS_VTOR
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select CPU_HAS_ARM_SAU
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select CPU_HAS_ARM_MPU
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select CPU_HAS_FPU
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select ARMV8_M_DSP
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select ARMV8_1_M_MVEI
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select ARMV8_1_M_MVEF
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select ARMV8_1_M_PMU
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select HAS_SWO
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select AMBIQ_HAL
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select HAS_PM
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select SOC_EARLY_INIT_HOOK
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select REQUIRES_FULL_LIBC
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21
soc/ambiq/apollo5x/Kconfig.defconfig
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21
soc/ambiq/apollo5x/Kconfig.defconfig
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# SPDX-License-Identifier: Apache-2.0
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#
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# Copyright (c) 2025 Ambiq Micro Inc.
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if SOC_SERIES_APOLLO5X
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rsource "Kconfig.defconfig.apollo5*"
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config CACHE_MANAGEMENT
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default y
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config AMBIQ_CACHEABLE_DMA_BUFFER_ALIGNMENT
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int
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default DCACHE_LINE_SIZE
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# Need to enlarge the IDLE stack size because the power
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# management operations are executed in the idle task
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config IDLE_STACK_SIZE
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default 2048 if PM
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endif # SOC_SERIES_APOLLO5X
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10
soc/ambiq/apollo5x/Kconfig.defconfig.apollo510
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10
soc/ambiq/apollo5x/Kconfig.defconfig.apollo510
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# SPDX-License-Identifier: Apache-2.0
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#
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# Copyright (c) 2025 Ambiq Micro Inc.
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if SOC_APOLLO510
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config NUM_IRQS
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default 134
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endif # SOC_APOLLO510
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23
soc/ambiq/apollo5x/Kconfig.soc
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23
soc/ambiq/apollo5x/Kconfig.soc
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# SPDX-License-Identifier: Apache-2.0
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#
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# Copyright (c) 2025 Ambiq Micro Inc.
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config SOC_SERIES_APOLLO5X
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bool
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select SOC_FAMILY_AMBIQ
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help
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Apollo5 Series MCU
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config SOC_APOLLO510
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bool
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select SOC_SERIES_APOLLO5X
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config ARMV8_1_M_PMU_EVENTCNT
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int
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default 8
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config SOC_SERIES
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default "apollo5x" if SOC_SERIES_APOLLO5X
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config SOC
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default "apollo510" if SOC_APOLLO510
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87
soc/ambiq/apollo5x/pinctrl_soc.h
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87
soc/ambiq/apollo5x/pinctrl_soc.h
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/*
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* Copyright (c) 2025 Ambiq Micro Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_SOC_ARM_AMBIQ_APOLLO5_PINCTRL_SOC_H_
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#define ZEPHYR_SOC_ARM_AMBIQ_APOLLO5_PINCTRL_SOC_H_
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#include <zephyr/dt-bindings/pinctrl/ambiq-apollo5-pinctrl.h>
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/**
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* @brief Type to hold a pin's pinctrl configuration.
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*/
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struct apollo5_pinctrl_soc_pin {
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/** Pin number 0..223 */
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uint64_t pin_num: 8;
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/** Alternative function (UART, SPI, etc.) */
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uint64_t alt_func: 4;
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/** Enable the pin as an input */
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uint64_t input_enable: 1;
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/** Drive strength, relative to full-driver strength */
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uint64_t drive_strength: 3;
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/** Drive actively high or low */
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uint64_t push_pull: 1;
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/** Drive with open drain */
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uint64_t open_drain: 1;
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/** High impedance mode */
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uint64_t tristate: 1;
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/** Enable the internal pull up resistor */
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uint64_t bias_pull_up: 1;
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/** Enable the internal pull down resistor */
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uint64_t bias_pull_down: 1;
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/** pullup resistor value */
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uint64_t ambiq_pull_up_ohms: 3;
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/** nCE module select */
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uint64_t nce: 6;
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/** nCE module polarity */
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uint64_t nce_pol: 1;
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/** SDIF CD WP pad select */
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uint64_t sdif_cdwp: 3;
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};
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typedef struct apollo5_pinctrl_soc_pin pinctrl_soc_pin_t;
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/**
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* @brief Utility macro to initialize each pin.
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*
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* @param node_id Node identifier.
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* @param prop Property name.
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* @param idx Property entry index.
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*/
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#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \
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{ \
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APOLLO5_GET_PIN_NUM(DT_PROP_BY_IDX(node_id, prop, idx)), \
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APOLLO5_GET_PIN_ALT_FUNC(DT_PROP_BY_IDX(node_id, prop, idx)), \
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DT_PROP(node_id, input_enable), \
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DT_ENUM_IDX(node_id, drive_strength), \
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DT_PROP(node_id, drive_push_pull), \
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DT_PROP(node_id, drive_open_drain), \
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DT_PROP(node_id, bias_high_impedance), \
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DT_PROP(node_id, bias_pull_up), \
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DT_PROP(node_id, bias_pull_down), \
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DT_ENUM_IDX(node_id, ambiq_pull_up_ohms), \
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DT_PROP(node_id, ambiq_nce_src), \
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DT_PROP(node_id, ambiq_nce_pol), \
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DT_PROP(node_id, ambiq_sdif_cdwp), \
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},
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/**
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* @brief Utility macro to initialize state pins contained in a given property.
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*
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* @param node_id Node identifier.
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* @param prop Property name describing state pins.
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*/
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#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
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{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), \
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DT_FOREACH_PROP_ELEM, pinmux, \
|
||||
Z_PINCTRL_STATE_PIN_INIT)}
|
||||
|
||||
#define APOLLO5_GET_PIN_NUM(pinctrl) \
|
||||
(((pinctrl) >> APOLLO5_PIN_NUM_POS) & APOLLO5_PIN_NUM_MASK)
|
||||
#define APOLLO5_GET_PIN_ALT_FUNC(pinctrl) \
|
||||
(((pinctrl) >> APOLLO5_ALT_FUNC_POS) & APOLLO5_ALT_FUNC_MASK)
|
||||
|
||||
|
||||
#endif /* ZEPHYR_SOC_ARM_AMBIQ_APOLLO5_PINCTRL_SOC_H_ */
|
67
soc/ambiq/apollo5x/power.c
Normal file
67
soc/ambiq/apollo5x/power.c
Normal file
|
@ -0,0 +1,67 @@
|
|||
/*
|
||||
* Copyright (c) 2025 Ambiq LLC
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <soc.h>
|
||||
|
||||
#include <zephyr/drivers/interrupt_controller/gic.h>
|
||||
#include <zephyr/kernel.h>
|
||||
#include <zephyr/logging/log.h>
|
||||
#include <zephyr/pm/pm.h>
|
||||
#include <zephyr/init.h>
|
||||
|
||||
LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
|
||||
|
||||
void pm_state_set(enum pm_state state, uint8_t substate_id)
|
||||
{
|
||||
ARG_UNUSED(substate_id);
|
||||
|
||||
__disable_irq();
|
||||
__set_BASEPRI(0);
|
||||
|
||||
switch (state) {
|
||||
case PM_STATE_SUSPEND_TO_IDLE: {
|
||||
/* Put ARM core to normal sleep. */
|
||||
am_hal_sysctrl_sleep(AM_HAL_SYSCTRL_SLEEP_NORMAL);
|
||||
break;
|
||||
}
|
||||
case PM_STATE_SUSPEND_TO_RAM: {
|
||||
/* Put ARM core to deep sleep. */
|
||||
/* Cotex-m: power down, register value preserve.*/
|
||||
/* Cache: power down*/
|
||||
/* MRAM: power down*/
|
||||
/* ITCM + DTCM: retention, active on request*/
|
||||
/* Sram: retention, active on request*/
|
||||
am_hal_sysctrl_sleep(AM_HAL_SYSCTRL_SLEEP_DEEP);
|
||||
break;
|
||||
}
|
||||
default: {
|
||||
LOG_DBG("Unsupported power state %u", state);
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief PM State Exit Post Operations
|
||||
*
|
||||
* For PM_STATE_SUSPEND_TO_IDLE:
|
||||
* Nothing is needed after soc woken up.
|
||||
*
|
||||
* For PM_STATE_SUSPEND_TO_RAM:
|
||||
* Flash, cache, sram automatically switch
|
||||
* to active state on wake up
|
||||
*
|
||||
* @param state PM State
|
||||
* @param substate_id Unused
|
||||
*
|
||||
*/
|
||||
void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
|
||||
{
|
||||
ARG_UNUSED(substate_id);
|
||||
|
||||
__enable_irq();
|
||||
irq_unlock(0);
|
||||
}
|
47
soc/ambiq/apollo5x/soc.c
Normal file
47
soc/ambiq/apollo5x/soc.c
Normal file
|
@ -0,0 +1,47 @@
|
|||
/*
|
||||
* Copyright (c) 2025 Ambiq Micro Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <zephyr/init.h>
|
||||
#include <zephyr/cache.h>
|
||||
#include "soc.h"
|
||||
|
||||
#define SCRATCH0_OEM_RCV_RETRY_MAGIC 0xA86
|
||||
|
||||
void soc_early_init_hook(void)
|
||||
{
|
||||
/* Enable Loop and branch info cache */
|
||||
SCB->CCR |= SCB_CCR_LOB_Msk;
|
||||
__DSB();
|
||||
__ISB();
|
||||
|
||||
if ((MCUCTRL->SCRATCH0 >> 20) == SCRATCH0_OEM_RCV_RETRY_MAGIC) {
|
||||
/*
|
||||
* Clear the scratch register
|
||||
*/
|
||||
MCUCTRL->SCRATCH0 = 0x00;
|
||||
}
|
||||
|
||||
/* Internal timer15 for SPOT manager */
|
||||
IRQ_CONNECT(82, 0, hal_internal_timer_isr, 0, 0);
|
||||
|
||||
/* Initialize for low power in the power control block */
|
||||
am_hal_pwrctrl_low_power_init();
|
||||
|
||||
/* Enable SIMOBUCK for the apollo5 Family */
|
||||
am_hal_pwrctrl_control(AM_HAL_PWRCTRL_CONTROL_SIMOBUCK_INIT, NULL);
|
||||
|
||||
/*
|
||||
* Set default temperature for spotmgr to room temperature
|
||||
*/
|
||||
am_hal_pwrctrl_temp_thresh_t dummy[32];
|
||||
am_hal_pwrctrl_temp_update(25.0f, dummy);
|
||||
|
||||
/* Enable Icache*/
|
||||
sys_cache_instr_enable();
|
||||
|
||||
/* Enable Dcache */
|
||||
sys_cache_data_enable();
|
||||
}
|
12
soc/ambiq/apollo5x/soc.h
Normal file
12
soc/ambiq/apollo5x/soc.h
Normal file
|
@ -0,0 +1,12 @@
|
|||
/*
|
||||
* Copyright (c) 2025 Ambiq Micro Inc.
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef __SOC_H__
|
||||
#define __SOC_H__
|
||||
|
||||
#include <am_mcu_apollo.h>
|
||||
|
||||
#endif /* __SOC_H__ */
|
|
@ -9,3 +9,6 @@ family:
|
|||
socs:
|
||||
- name: apollo3_blue
|
||||
- name: apollo3p_blue
|
||||
- name: apollo5x
|
||||
socs:
|
||||
- name: apollo510
|
||||
|
|
2
west.yml
2
west.yml
|
@ -152,7 +152,7 @@ manifest:
|
|||
groups:
|
||||
- hal
|
||||
- name: hal_ambiq
|
||||
revision: a6dff0a5f49e898f29bc428e01538a8911364460
|
||||
revision: e916e84a103e13ce8bcf8b7f53dafbe57ed0b846
|
||||
path: modules/hal/ambiq
|
||||
groups:
|
||||
- hal
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue