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soc: stm32: use cache peripheral driver

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Use the Zephyr cache API in soc initialization code instead of calling the
HAL directly. The change does not modify the pre-existing cache settings,
just changes the path they are enabled.

Signed-off-by: Henrik Lindblom <henrik.lindblom@vaisala.com>
This commit is contained in:
Henrik Lindblom 2025-04-15 11:20:11 +03:00 • committed by Benjamin Cabé
commit 9de3d6bf64
11 changed files with 64 additions and 62 deletions
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3
soc/st/stm32/Kconfig.defconfig
View file

@ -11,6 +11,9 @@ if SOC_FAMILY_STM32
# can override the defaults given here
rsource "*/Kconfig.defconfig"
config CACHE_STM32
default y if EXTERNAL_CACHE
config CLOCK_CONTROL
default y

13
soc/st/stm32/stm32h5x/Kconfig.defconfig
View file

@ -7,6 +7,19 @@ if SOC_SERIES_STM32H5X
rsource "Kconfig.defconfig.stm32h5*"
config ICACHE
default y
config DCACHE
default y if !SOC_STM32H503XX
config CACHE_MANAGEMENT
default y
choice CACHE_TYPE
default EXTERNAL_CACHE
endchoice
config ROM_START_OFFSET
default 0x400 if BOOTLOADER_MCUBOOT

6
soc/st/stm32/stm32h5x/soc.c
View file

@ -11,9 +11,9 @@
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/cache.h>
#include <stm32_ll_bus.h>
#include <stm32_ll_pwr.h>
#include <stm32_ll_icache.h>
#include <zephyr/logging/log.h>
#include <cmsis_core.h>
@ -29,9 +29,7 @@ extern void stm32_power_init(void);
*/
void soc_early_init_hook(void)
{
/* Enable instruction cache in 1-way (direct mapped cache) */
LL_ICACHE_SetMode(LL_ICACHE_1WAY);
LL_ICACHE_Enable();
sys_cache_instr_enable();
/* Update CMSIS SystemCoreClock variable (HCLK) */
/* At reset, system core clock is set to 32 MHz from HSI with a HSIDIV = 2 */

10
soc/st/stm32/stm32l5x/Kconfig.defconfig
View file

@ -7,6 +7,16 @@ if SOC_SERIES_STM32L5X
rsource "Kconfig.defconfig.stm32l5*"
config ICACHE
default y
config CACHE_MANAGEMENT
default y
choice CACHE_TYPE
default EXTERNAL_CACHE
endchoice
config ROM_START_OFFSET
default 0x400 if BOOTLOADER_MCUBOOT

7
soc/st/stm32/stm32l5x/soc.c
View file

@ -11,9 +11,9 @@
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/cache.h>
#include <stm32_ll_bus.h>
#include <stm32_ll_pwr.h>
#include <stm32l5xx_ll_icache.h>
#include <zephyr/logging/log.h>
#include <cmsis_core.h>
@ -29,10 +29,7 @@ extern void stm32_power_init(void);
*/
void soc_early_init_hook(void)
{
/* Enable ICACHE */
while (LL_ICACHE_IsActiveFlag_BUSY()) {
}
LL_ICACHE_Enable();
sys_cache_instr_enable();
/* Update CMSIS SystemCoreClock variable (HCLK) */
/* At reset, system core clock is set to 4 MHz from MSI */

13
soc/st/stm32/stm32u5x/Kconfig.defconfig
View file

@ -10,6 +10,19 @@ rsource "Kconfig.defconfig.stm32u5*"
config ROM_START_OFFSET
default 0x400 if BOOTLOADER_MCUBOOT
config ICACHE
default y
config DCACHE
default y
config CACHE_MANAGEMENT
default y
choice CACHE_TYPE
default EXTERNAL_CACHE
endchoice
if STM32_STOP3_LP_MODE
config COUNTER

25
soc/st/stm32/stm32u5x/power.c
View file

@ -4,6 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/cache.h>
#include <zephyr/pm/pm.h>
#include <soc.h>
#include <zephyr/init.h>
@ -12,7 +13,6 @@
#include <stm32u5xx_ll_bus.h>
#include <stm32u5xx_ll_cortex.h>
#include <stm32u5xx_ll_pwr.h>
#include <stm32u5xx_ll_icache.h>
#include <stm32u5xx_ll_rcc.h>
#include <stm32u5xx_ll_system.h>
#include <clock_control/clock_stm32_ll_common.h>
@ -35,22 +35,6 @@ static void pwr_stop3_isr(const struct device *dev)
/* Clear all wake-up flags */
LL_PWR_ClearFlag_WU();
}
static void disable_cache(void)
{
/* Disabling ICACHE */
LL_ICACHE_Disable();
while (LL_ICACHE_IsEnabled() == 1U) {
}
/* Wait until ICACHE_SR.BUSYF is cleared */
while (LL_ICACHE_IsActiveFlag_BUSY() == 1U) {
}
/* Wait until ICACHE_SR.BSYENDF is set */
while (LL_ICACHE_IsActiveFlag_BSYEND() == 0U) {
}
}
#endif
void set_mode_stop(uint8_t substate_id)
@ -82,7 +66,7 @@ void set_mode_stop(uint8_t substate_id)
LL_PWR_ClearFlag_SB();
LL_PWR_ClearFlag_WU();
disable_cache();
sys_cache_instr_disable();
LL_PWR_SetPowerMode(LL_PWR_STOP3_MODE);
break;
@ -135,10 +119,7 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
} else if (substate_id == 4) {
stm32_clock_control_standby_exit();
LL_ICACHE_SetMode(LL_ICACHE_1WAY);
LL_ICACHE_Enable();
while (LL_ICACHE_IsEnabled() == 0U) {
}
sys_cache_instr_enable();
LL_LPM_DisableSleepOnExit();
LL_LPM_EnableSleep();

6
soc/st/stm32/stm32u5x/soc.c
View file

@ -10,10 +10,10 @@
*/
#include <zephyr/device.h>
#include <zephyr/cache.h>
#include <zephyr/init.h>
#include <stm32_ll_bus.h>
#include <stm32_ll_pwr.h>
#include <stm32_ll_icache.h>
#include <zephyr/logging/log.h>
#include <cmsis_core.h>
@ -29,9 +29,7 @@ extern void stm32_power_init(void);
*/
void soc_early_init_hook(void)
{
/* Enable instruction cache in 1-way (direct mapped cache) */
LL_ICACHE_SetMode(LL_ICACHE_1WAY);
LL_ICACHE_Enable();
sys_cache_instr_enable();
/* Update CMSIS SystemCoreClock variable (HCLK) */
/* At reset, system core clock is set to 4 MHz from MSIS */

10
soc/st/stm32/stm32wbax/Kconfig.defconfig
View file

@ -7,6 +7,16 @@ if SOC_SERIES_STM32WBAX
rsource "Kconfig.defconfig.stm32wba*"
config ICACHE
default y
config CACHE_MANAGEMENT
default y
choice CACHE_TYPE
default EXTERNAL_CACHE
endchoice
config STM32_LPTIM_TIMER
default y if PM

27
soc/st/stm32/stm32wbax/power.c
View file

@ -4,6 +4,7 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/kernel.h>
#include <zephyr/cache.h>
#include <zephyr/pm/pm.h>
#include <soc.h>
#include <zephyr/init.h>
@ -13,7 +14,6 @@
#include <stm32wbaxx_ll_bus.h>
#include <stm32wbaxx_ll_cortex.h>
#include <stm32wbaxx_ll_pwr.h>
#include <stm32wbaxx_ll_icache.h>
#include <stm32wbaxx_ll_rcc.h>
#include <stm32wbaxx_ll_system.h>
#include <clock_control/clock_stm32_ll_common.h>
@ -28,22 +28,6 @@ LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
void stm32_power_init(void);
static void disable_cache(void)
{
/* Disabling ICACHE */
LL_ICACHE_Disable();
while (LL_ICACHE_IsEnabled() == 1U) {
}
/* Wait until ICACHE_SR.BUSYF is cleared */
while (LL_ICACHE_IsActiveFlag_BUSY() == 1U) {
}
/* Wait until ICACHE_SR.BSYENDF is set */
while (LL_ICACHE_IsActiveFlag_BSYEND() == 0U) {
}
}
static void set_mode_stop(uint8_t substate_id)
{
@ -53,7 +37,7 @@ static void set_mode_stop(uint8_t substate_id)
/* Erratum 2.2.15:
* Disabling ICACHE is required before entering stop mode
*/
disable_cache();
sys_cache_instr_disable();
#ifdef CONFIG_BT_STM32WBA
scm_setwaitstates(LP);
@ -108,7 +92,7 @@ static void set_mode_suspend_to_ram(void)
LL_PWR_ClearFlag_WU();
LL_RCC_ClearResetFlags();
disable_cache();
sys_cache_instr_disable();
/* Select standby mode */
LL_PWR_SetPowerMode(LL_PWR_MODE_STANDBY);
@ -161,10 +145,7 @@ void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
/* Erratum 2.2.15:
* Enable ICACHE when exiting stop mode
*/
LL_ICACHE_SetMode(LL_ICACHE_1WAY);
LL_ICACHE_Enable();
while (LL_ICACHE_IsEnabled() == 0U) {
}
sys_cache_instr_enable();
LL_LPM_DisableSleepOnExit();
LL_LPM_EnableSleep();

6
soc/st/stm32/stm32wbax/soc.c
View file

@ -11,10 +11,10 @@
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/cache.h>
#include <stm32_ll_bus.h>
#include <stm32_ll_pwr.h>
#include <stm32_ll_rcc.h>
#include <stm32_ll_icache.h>
#include <zephyr/arch/cpu.h>
#include <zephyr/irq.h>
#include <zephyr/logging/log.h>
@ -31,9 +31,7 @@ LOG_MODULE_REGISTER(soc);
*/
void stm32wba_init(void)
{
/* Enable instruction cache in 1-way (direct mapped cache) */
LL_ICACHE_SetMode(LL_ICACHE_1WAY);
LL_ICACHE_Enable();
sys_cache_instr_enable();
#ifdef CONFIG_STM32_FLASH_PREFETCH
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif