Add linker support for OpenAMP sample on Renesas RZ/V2L
Signed-off-by: Phuc Pham <phuc.pham.xr@bp.renesas.com>
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
Create separate memory regions for each OFS register. With a single
region the linker will gap fill the load segment with zeros between
each option setting section that gets placed in the region when
generating the .elf file.
Signed-off-by: Jeremy Dick <jdick@pivotint.com>
This commit updates the GDMA register definitions to align with the
specifications of the chip series.
Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
The .bin file is huge (>1GB) and will probably not be used by anyone if
there are much smaller alternatives. Because of that, disable it by
default for this soc. There is also no support for generating the
CRC32 checksum for the ccfg section in the binary.
Signed-off-by: Fabian Pflug <fabian.pflug@gumulka.eu>
As stated in [0] section 9.2 Customer Configuration:
There are four different CRCs used to validate the CCFG data.
One of the CRCs, the user record CRC, is optional and is the
last four bytes of the 128B user record. The data over which
the CRC is calculated starts at “Data Start Offset” from Table
9-2 and ends at the "CRC Offset". CRC field width is 4 bytes.
Meaning the MCU will not start if the CRC fields are not correct.
TI's tools will automagically set these fields, but other tools have to
do it by hand. Therefore a new post-build-command is introduced to set
the fields at least in the .hex file by generating a new _crc32.hex
file.
[0] https://www.ti.com/lit/ug/swcu193a/swcu193a.pdf
Signed-off-by: Fabian Pflug <fabian.pflug@gumulka.eu>
Although not reproducible locally, it has been observed in CI that the
uicr image will not always be the last image to be run.
To ensure it is the last image to be run we have it depend on the
'image' image when defined.
The uicr image is generated based on all other images in the build and
must therefore run last.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Remove hp_sram_init() call from boot_d3_restore() as it's redundant and
causes TLB access errors. The TLB driver's adsp_mm_restore_context()
already handles all HPSRAM power management and content restoration.
The removed code was attempting to zero memory regions that are
intentionally unmapped by the TLB driver for power optimization, causing
access to disabled TLB entries during D3→D0 transitions.
Additionally, hp_sram_init() powers up all memory banks while the TLB
restore function correctly enables only the banks that were actually
used, maintaining proper power optimization.
Current flow causes errors in simulation which revealed this incorrect
double initialization in test scenarios with minimal firmware
configurations.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Adds initial SoC-level support for the Microchip
PIC32CM JH series, including SoC definition files.
Signed-off-by: Arunprasath P <arunprasath.p@microchip.com>
Add stm32l083xx SoC variants that are similar to stm32l073xx with an added
AES accelerator.
Signed-off-by: Marek Maškarinec <marek.maskarinec@hardwario.com>
Change hardware cycle count (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) to 594
MHz. Move that value to the SoC layer's DT.
Validated with the amp_blinky example - the period of the blinking LED
is exactly 2 seconds, like was programmed.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
Add I2C_TARGET_ALLOW_POWER_SAVING config. Enable this config makes I2C
target device can enter Doze/Deep doze states while the bus is idle.
Ongoing transfers will block low-power entry until they are completed,
ensuring correct communication while still reducing overall power
consumption.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Ensure sw_isr_common, dynamic_isr, and init routines are executed from IRAM
by relocating libarch__common.a section.
Running these from flash prevents the board from booting properly, as flash
access is not available during early initialization.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add FPU power management for suspend to RAM procedures.
Add FPU save/restore procedures when `FPU_SHARING` feature
is disabled.
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
- Add ``R_BSP_SecondaryCoreStart`` for the primary core to start
the secondary core
- Disable ``clock_init`` for the secondary core
Signed-off-by: Khoa Nguyen <khoa.nguyen.xh@renesas.com>
Use DRAM region 1 as the default spill area for the `.noinit`
section if appcpu is not present
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
add support for SHUTDOWN operating mode in TI MSPM0 series for power-off
operation. Uses HWINFO for reset cause detection to handle shutdown IO
release on low power wakeup.
Signed-off-by: Sanjay Vallimanalan <sanjay@linumiz.com>
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
TI MSPM0 series supports range of power modes (RUN/SLEEP, STOP, STANDBY)
supporting low power operations. Provides automatic restoration to
RUN mode on wakeup from any low power state.
Signed-off-by: Sanjay Vallimanalan <sanjay@linumiz.com>
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Other targets that define this symbol do it in the Kconfig file, and
gate it with a SOC_ model or series symbol. Defining a default in the
Kconfig.soc instead applies it on every build, which is not desired.
Signed-off-by: Luca Burelli <l.burelli@arduino.cc>
Add support for halting the Radio core immediately after reset. This
ensures that a debugger can attach and take control from the very
first instruction.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
PM on the nrf54h20 has minimal utility if power domains and devices
are not managed at runtime, as these prevent the soc from entering
sleep states in the first place. Enable PM_DEVICE by default if PM,
which in turn enables PM_DEVICE_RUNTIME for devices and power
domains.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Add image properties data structure to Series 2 binaries.
This data structure is used by the SE or bootloader to enforce
secure boot, and by other tools to extract image information.
Use the app version if set, or fall back to the kernel version
for the image version field. Set image type based on Kconfig
options.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Added support for the IronSide bootmode service which allows requesting
a reboot into secondary firmware boot mode. In this mode, the secondary
configuration defined in UICR is applied instead of the primary one.
The service provides the ironside_bootmode_secondary_reboot() function
that can pass message data to the boot report of the CPU booted in the
secondary boot mode.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Do not directly include and use APIs from ksched.h outside of the
kernel. For now do this using more suitable (ipi.h and
kernel_internal.h) internal APIs until more cleanup is done.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The CMC interface controls the entry and exit of the
CPU's low-power mode and the identification of the wake-up source.
To ensure the normal operation of the system's low-power timing sequence,
when transfer IDLE_RUN to IDLE_SLEEP, it is necessary to ensure
that the system is not awakened by the wake-up source during this stage.
Therefore, an IRQ MASK needs to be set on the CMC
Before the CPU enters the low power mode, a wake up mask needs to be set
according to the situation where the interrupt controller is enabled
at that time.
After the cpu exits the low power mode, resume needs to be performed
Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
The insertion of MCUBOOT header will shift the rom code ahead with
0x800 bytes because of memory alignment
Signed-off-by: Andre Heinemans <andre.heinemans@nxp.com>
z_prep_c does not return, mark it as such consistently across
architectures. We had some arches do that, others not. This resolves a
few coding guideline violations in arch code.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Do not use private API prefix and move to architecture interface as
those functions are primarily used across arches and can be defined by
the architecture.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Cleanup init.c code and move early boot code into arch/ and make it
accessible outside of the boot process/kernel.
All of this code is not related to the 'kernel' and is mostly used
within the architecture boot / setup process.
The way it was done, some soc code was including kernel_internal.h
directly, which shouldn't be done.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Restructure the IronSide boot report interface with enhanced error
reporting and boot context information.
Signed-off-by: Sebastian Bøe <sebastian.boe@nordicsemi.no>
Enables low power stop mode for C0.
Code is taken from F4 family, tested on nucleo-c71rb with
samples/basic/blinky.
Power consumption in run mode 3.7 mA, in stop mode ~87 uA.
Signed-off-by: Tomáš Juřena <jurenatomas@gmail.com>
Fixeszephyrproject-rtos/zephyr#92663
Disabled LFXO via devicetree allows pin 0.00 and 0.01 to work correctly
as gpio by assigning it to the app core instead of peripheral. Removed
deprecated Kconfig options so DT is the only config path now.
Signed-off-by: Ivynya Lu <ivy.lu@level.co>
Add initial support for the Versal Net SoC APU, which is based on
the Arm Cortex-A78 processor. It includes basic wiring for memory
regions, UART, interrupt controller, and timer.
The versalnet_apu.dtsi file defines peripherals shared across the SoC,
while versalnet_a78.dtsi captures peripherals private to the Cortex-A78
processor. These device trees lay the groundwork for further APU-based
development on the Versal Net platform.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
