This is the initial commit to support pinctrl driver for Renesas RZ/T2M
Corrected space in the comment.
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Binh Nguyen <binh.nguyen.xw@renesas.com>
Renesas takes over the maintainer of SoC Renesas RZ/T2M to unify with
other RZ devices
- Move soc/renesas/rzt2m to soc/renesas/rz
- Support xSPI boot mode to boot code from flash
- Change to use HAL Renesas
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Binh Nguyen <binh.nguyen.xw@renesas.com>
RAM power configuration is preserved through soft reset,
meaning that there is a risk of accessing powered off RAM blocks
when booting in different application (i.e. bootloader).
Add option to force all RAM blocks to be powered on
before triggering soft reset to prevent this from happening.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
The chip requires a successful sleep entry to change the PLL sequence.
By default, the IT8XXX2 chip enables the I2C0 alternate function, which
can cause the clock/data lines to meet the start condition, preventing
EC from entering sleep mode.
This commit disables the I2C0 alternate function before executing the
PLL sequence change to ensure that the EC can enter sleep mode
successfully.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
STM32F439 SoC is an STM32F429 with an integrated crypto/hash processor
providing hardware acceleration for encryption (AES and TDES) and hash
(MD5, SHA-1 and SHA-2).
Signed-off-by: Mathieu Anquetin <mathieu.anquetin@groupe-cahors.com>
Convert z_clock_hw_cycles_per_sec to unsigned int to increase
supported frequency range.
Signed-off-by: Anisetti Avinash Krishna <anisetti.avinash.krishna@intel.com>
This is the initial commit to support pinctrl driver for Renesas RZ/V2L
Signed-off-by: Quang Le <quang.le.eb@bp.renesas.com>
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Add support for the RPU, real-time processing unit on Versal NET SoC.
It is based on Cortext-R52 processor.
The patch contains initial wiring and configuration for generic board
with OCM(1MB) and DDR(2G) memories, cpu, interrupt controller, global
timer and UART.
versalnet.dtsi contains common peripherals integrated into Versal NET
SoC, and versalnet_r52.dtsi has peripherals which are private to
Cortex-R52 processor.
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
Signed-off-by: Mubin Sayyed <mubin.sayyed@amd.com>
Check if the option bits DT nodes are enabled before including them in
the linker script for all RA SoCs. These must be disabled for targets
that provide a separate bootloader.
This commit adds the DT_NODE_HAS_STATUS_OKAY gates to all RA-series SoC
linker scripts, converting existing ones to the new macro.
The changes in this commit have been mechanically generated using find
and awk tools.
Signed-off-by: Luca Burelli <l.burelli@arduino.cc>
- Add new device tree source include file for DA14697 SoC
- Update Kconfig and soc.yml to support the new device
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
if CONFIG_PM=y, board will enter low power,
which will cause problem for debugger.
So for ztest cases, we need enable this to avoid problem.
This used to apply to soc/platform level, now remove them.
Signed-off-by: Hake Huang <hake.huang@nxp.com>
Add .resource_table section to the linker script for the
i.MX95. This section is used by intercore communication to
publish features and configurations to the remote
Signed-off-by: Andre Heinemans <andre.heinemans@nxp.com>
Enable support for using an external clock as the main clock.
When bypass mode is enabled, the external crystal oscillator is bypassed,
and the main clock is directly driven by an external clock signal.
Signed-off-by: Perry Hung <perry@mosi.io>
It is defined as spis120 rather than spi120,
because spi120 is already used for SPIM120 hardware instance,
but their base address is different.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
Add ULP Coprocessor board support for C6.
This requires a change in the board qualifier depending on the build
target.
Update esp32c6 overlay and configuration files to the proper name.
Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
This maps to Zephyr power state Standby. In this power
state the OS Timer cannot be used as a wakeup source as
it will be powered off. Hence the counter is enabled
and RTC is used to keep track of system ticks and wakeup
the system.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Since the clock source when running in PM mode 3 is the
slower 1KHx clock, we adjust the SYS_CLOCK_TICKS_PER_SEC
value to get better accuracy.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
This clock is used for certain peripherals such
as RTC.
On certain RW612 boards such as rd_rw612_bga, XTAL32K
and ENET share pins. Add code to check if ENET and
XTAL32 are enabled at the same time.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Add calls to sys_trace_idle and sys_trace_idle_exit in nrf54h specific
idle states to allow measuring CPU load on nrf54h20 when power
management is enabled.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
These socs were missing a config line to disable SYSTICK if the LPTMR is
configured for the system timer, similar to how other SOCs do this for
alternative system timers than systick.
This fixes build errors in the case where that lptmr kconfig is enabled.
Also, the LPTMR kconfig should be default no because it is a secondary
option for the system timer, being lower resolution than systick. This
also resolves build errors.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Migrate LINKLAYER_PLAT_EnableIRQ and LINKLAYER_PLAT_DisableIRQ
from linklayer_plat.c (hal/stm32 module).
Signed-off-by: Nidhal BEN OTHMEN <nidhal.benothmen@st.com>
Migrate LINKLAYER_PLAT_EnableRadioIT and LINKLAYER_PLAT_DisableRadioIT
from linklayer_plat.c (hal/stm32 module) and adapt it using irq
Zephyr APIs.
Correct casting of irq type between using NVIC APIs or irq Zephyr APIs
Signed-off-by: Nidhal BEN OTHMEN <nidhal.benothmen@st.com>
Increase the link layer thread priority to be more than the BLE CTRL
thread and more than the Zephyr BLE stack threads.
Signed-off-by: Nidhal BEN OTHMEN <nidhal.benothmen@st.com>
What is the change?
This commit adds support for Armv8.1-M MPU architecture's PXN attribute.
This includes support for configuring MPU regions with PXN via
custom mpu_config, devicetree and static mpu_config.
The existing MPU region attribute macros are updated to retain existing
behaviour with this change with an addition of REGION_RAM_ATTR_PXN to be
used if one needs to configure a RAM region with PXN MPU attribute.
Why do we need this change?
Armv8.1-M architecture introduced a new MPU region attribute called
Privilege eXecute Never (PXN).
If an MPU region is configured with the PXN attribute set and if the,
processor attempts to execute code in this region while at
privileged level, a Memory Management Fault exception is triggered.
This ensures that specific tasks are executed only in unprivileged mode
and helps in preventing secure privilege escalation attacks.
Signed-off-by: Sudan Landge <sudan.landge@arm.com>
Add a warning in the build system if both `CONFIG_PM` and
`STM32_ENABLE_DEBUG_SLEEP_STOP` are enabled at the same time. The first
is likely only enabled if the SoC is intended to be driven into low
power states to save power, while the later prevents the SoC from being
as low power as it can be.
Signed-off-by: Jordan Yates <jordan@embeint.com>
