Tests like log_backend_uart include an emulated UART driver which
gets selected for ITCM code relocation, as part of drivers__serial.
Filter by FILE instead of LIBRARY to avoid this.
Fixes#104275
Signed-off-by: Josuah Demangeon <me@josuah.net>
Includes files for mapping DFP macros to follow a common
macro name across multiple SoC for sercom uart g1 driver
Signed-off-by: Fabin V Martin <Fabinv.Martin@microchip.com>
When CPU_FREQ is enabled with CORTEX_M_SYSTICK on MCXN, the system
timer frequency changes dynamically as the core clock is scaled.
Update cpu_freq_pstate_set() to:
- Notify the system timer driver of the new frequency by calling
z_sys_clock_hw_cycles_per_sec_update() when CORTEX_M_SYSTICK is used
- Add a compile-time check to ensure
CONFIG_SYSTEM_CLOCK_HW_CYCLES_PER_SEC_RUNTIME_UPDATE is enabled when
using CPU_FREQ with SysTick, as this combination requires runtime
frequency update support
Also update Kconfig.defconfig to:
- Remove the default enabling of MCUX_OS_TIMER when CPU_FREQ is set
- Enable SYSTEM_CLOCK_HW_CYCLES_PER_SEC_RUNTIME_UPDATE by default when
both CPU_FREQ and CORTEX_M_SYSTICK are enabled
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Replace hardcoded -Wno-misleading-indentation flag with the new
warning_no_misleading_indentation compiler property for both C and C++
compilation in imx91 and imx943 SoCs. This ensures compiler-agnostic
handling of misleading indentation warnings.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
The RV32 core does not implement RISC-V mtime, so add a new system
timer driver uses a peripheral timer for this functionality.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
Adds support for the secondary risc-v core on all applicable max32
family socs. The zero-riscy core supports the following instructions:
- RV32I Base Integer Instruction Set
- RV32E Base Integer Instruction Set (optional)
- RV32C Standard Extension for Compressed Instructions
- RV32M Integer Multiplication and Division Instruction Set Extension
(optional)
Includes support for using pinctrl for setting up RV32 debug pin access,
and improved support for launcing the secodary core from the primary ARM
core.
See https://pulp-platform.org/docs/user_manual.pdf
Signed-off-by: Maureen Helm <maureen.helm@analog.com>
Clean up the SWD-JTAG port configuration code for STM32F1 series:
- remove check for DT_NODE_HAS_PROP() because there's default in binding
- use a wrapper around DT_ENUM_HAS_VALUE() instead of a bare DT_ENUM_IDX()
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
A special SYS_INIT() callback with hardcoded PRE_KERNEL_1 level 0 priority
inside the STM32 pinctrl driver was configuring the SWD-JTAG ports on
STM32F1 series.
Since this is the only series which requires such configuration, move this
code to the SoC-specific init hook instead (which has almost the same
priority as PRE_KERNEL_1 level 0 - it runs just slightly earlier).
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Add support for configuring the "PERIPHCONF stage" that is set
when the application core is started by IronSide SE. This configures
which permissions the application has when calling the IronSide
PERIPHCONF write API at boot time.
The new option is part of the new version 2.1 of the UICR format.
IronSide SE versions that do not support the 2.1 format version
will fail the boot if given a UICR with that version number.
To avoid forcing users to upgrade IronSide, the UICR generator
only sets the UICR format version to 2.1 if a PERIPHCONF stage policy
is explicitly set, otherwise it will default to the 2.0 version.
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
Add a config that can be disabled to keep the PERIPHCONF data in the
firmware binary rather than stripping it. When the option is disabled
for a given image, the UICR generator does not include that image's
PERIPHCONF data in the UICR PERIPHCONF blob, instead it is expected that
it is loaded separately via an IronSide API call.
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
We add the initial enablement of SoC managed PM (CONFIG_PM) for
Microchip MEC174x, MEC175x, and MEC165xB series. Common SoC
PM handling code was added with support for light and deep
sleep (standby and suspend respectively). The code includes
initial save and restore for peripherals that do not obey
the MEC PCR block sleep signals. This initial commit implements
save and restore for basic timers and UARTs. The code builds
and runs the Zephyr SoC managed PM subsystem test.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Add a hwinfo backend for GD32 providing:
- device unique ID readout from the 96-bit UID registers
- reset cause reporting via the RCU_RSTSCK reset status register
Reset cause mapping uses the hal_gigadevice RCU_RSTSCK flag definitions
and reports supported causes based on the macros available in the HAL.
Signed-off-by: Aleksandr Senin <al@meshium.net>
Replace hardcoded wsr.MISC0 with the build-generated ZSR_CPU_STR
macro to write the correct Xtensa special register for the CPU
pointer.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
We are no longer able to enable CONFIG_PM.
This Kconfig depends on HAS_PM, which is no longer
selected by the MCXW23 platform.
Signed-off-by: Yassine El Aissaoui <yassine.elaissaoui@nxp.com>
Use the IRONSIDE_SUPPORT_DIR cmake variable to determine the location
of the UICR generator script location, to allow overriding the location
if needed.
Since the CMake that would normally set this variable in
modules/hal_nordic/ironside/se/CMakeLists.txt is not actually run in the
gen_uicr image, refactor the logic for setting the variable so that it
can be included in the gen_uicr image directly.
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
Add pin control driver for Alif SoCs. The driver manages
pin muxing (alternate function selection) and pad configuration
for Alif SoCs.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Ensemble is a family of processors from Alif Semiconductor
targeted at low-end to high-end intelligent IoT endpoint
applications. Series (E1-E8) within the family scale up from
single-core MCUs to quad-core MCU/MPU fusion processors.
Add support for the Ensemble family and the E8 series with the
AE822FA0E5597LS0 SoC. The SoC contains two Cortex-M55 cores: one
configured to maximize power efficiency (RTSS-HE - High Efficiency
Real Time Subsystem) and the other to maximize compute performance
(RTSS-HP - High Performance Real Time Subsystem).
Link: https://alifsemi.com/products/ensemble/
Link: https://alifsemi.com/products/ensemblegenai/
Link: https://alifsemi.com/ensemble-e8-series/
Co-authored-by: Tanay Rami <tanay@alifsemi.com>
Co-authored-by: Prabhakar Kumar <prabhakar.kumar@alifsemi.com>
Signed-off-by: Silesh C V <silesh@alifsemi.com>
SOC_COMPATIBLE_NRF7120_ENGA was erroneously being used in
KConfig filter and therefore not being applied, since soc configs are
generated at compile time. Created SOC_COMPATIBLE_NRF71 to be used at
KConfig build stage.
Signed-off-by: Robert Robinson <robert.robinson@nordicsemi.no>
Any leading -D passed to target_compile_definitions on an item will
be removed, here remove them to make code style consistent.
Signed-off-by: Paul He <pawpawhe@gmail.com>
Add clock control driver
Implement bootup clock initialization, on, off, configure and get_rate API
Signed-off-by: Sunil Abraham <sunil.abraham@microchip.com>
Add a SoC-level power management hook in stm32wbax power support
to handle the case when the radio is enabled.
This ensures the power configuration remains consistent with
RF activity and avoids entering low-power states that are
incompatible with the radio being active.
The new helper is wired into the STM32WBAX power control logic,
so that radio-related constraints are taken into account during
power state transitions.
Signed-off-by: Alessandro Manganaro <alessandro.manganaro@st.com>
Some of the peripherals might be used in the bootloader
and not cleaned up properly for the next image in the boot chain.
Ensure that affected registers are always cleaned up before use.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
The SK-AM62 and SK-AM62B-P1 board variants both use the AM6254
SoC, not AM6234. Update board configuration to reference the
correct SoC variant.
This changes the board identifiers from sk_am62/am6234/* to
sk_am62/am6254/* for both M4 and A53 cores.
Documentation updated to mention both board variants:
- SK-AM62 (base variant)
- SK-AM62B-P1 (variant with integrated PMIC)
Signed-off-by: Soumya Tripathy <s-tripathy@ti.com>
added SOC_AMEBA_NP_IMAGE to handle ameba blobs to run a different
architecture CPU inside the SOC.
Signed-off-by: zjian zhang <zjian_zhang@realsil.com.cn>
Adds a common-place for Kconfigs needed by TF-M instead of
mass-duplicating them in every board that uses these SoCs
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Since the audio DSP is not using the architecture boot path,
the BSS is not cleared/zeroed at boot. So we need to manually
zero out the BSS via arch_bss_zero().
Also, the _bss_table_start/_end symbols are no longer needed
since we are not using the arch boot code. Saves a few bytes.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Removing cpu0 reference from mcxw72 target
as only cpu0 should be targeted on this device.
Signed-off-by: Emilio Benavente <emilio.benavente@nxp.com>
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
Change logic from the offset to the absolute address as the
DT_REG_ADDR(..) macro now returns the absolute address and cannot be
compared with the value of the CONFIG_FLASH_LOAD_ADDRESS.
Signed-off-by: Tomasz Chyrowicz <tomasz.chyrowicz@nordicsemi.no>
If MCUboot is enabled, the start address of the radio core firmware is
offset by MCUboot header.
Normally, the header is accounted for by setting the
CONFIG_ROM_START_OFFSET value to match the header size.
Signed-off-by: Tomasz Chyrowicz <tomasz.chyrowicz@nordicsemi.no>
Workaround has been reverted and different approach is taken.
Removing UART_NRFX_UARTE_SPURIOUS_RXTO_WORKAROUND from nrf54lm20a
Kconfig.defconfig.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
The base address was written to an incorrect register, which caused
incorrect data to be read from the I2C target. This has been fixed by
writing to the correct register.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Fix macros/symbols that broke after changes were merged to get the
absolute address through ranges property
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
