Handle GAMC register with device memory-mapped input/output management.
As the MMIO is used, remove the MMU configurations for GMAC accordingly.
Signed-off-by: Tony Han <tony.han@microchip.com>
Wi-Fi on PSRAM-enabled builds was failing because the shared multi
heap overlapped relocated .ext_ram.data noinit content. Anchor the
heap on the linker-reserved window, size esp32c5 and esp32s3 ext
segments to the cache window and bump the Wi-Fi SPIRAM heap floor.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The STM32Cube HAL2 uses different hooks for assertion failures.
Attempting to enable HAL assertions on series using HAL2 right now
results in a build failure because we don't provide these hooks.
For example:
west build samples/net/dhcpv4_client/ -b nucleo_c5a3zg
-DCONFIG_ASSERT=y -DCONFIG_USE_STM32_ASSERT=y -p
results in the following messages (shortened for clarity):
[293/298] Linking C executable zephyr/zephyr_pre0.elf
FAILED: zephyr/zephyr_pre0.elf zephyr/zephyr_pre0.map
ld.bfd: in function `HAL_RCC_PSI_GetConfig':
.../stm32c5xx/drivers/hal/stm32c5xx_hal_rcc.c:1596:
undefined reference to `assert_dbg_param_failed'
ld.bfd: in function `HAL_ETH_SetConfig':
.../stm32c5xx/drivers/hal/stm32c5xx_hal_eth.c:1465:
undefined reference to `assert_dbg_state_failed'
Add glue code needed for compatibility with HAL2 and, while at it, also
clean up the HAL1-specific hook.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Add initial support for nuvoton numaker m031x SoC series
including basic init and device tree source include.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
ESP32-S2, S3 and C5 select CPU_HAS_DCACHE so CONFIG_DCACHE is
always y on these series. Gating CACHE_MANAGEMENT on ESP_SPIRAM
left CONFIG_DCACHE_LINE_SIZE undefined when PSRAM was disabled,
which broke any driver that reads it under CONFIG_DCACHE such as
the USB device controller buffer macros.
Drop the ESP_SPIRAM condition so CACHE_MANAGEMENT defaults to y
whenever the series is selected, matching the ESP32-P4 defconfig.
The cache line size is a CPU property that exists regardless of
PSRAM, and internal SRAM DMA paths also benefit from coherent
sys_cache_data_* operations.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Added autanalog CTB support for PSE84 device.
This implementation uses the autnonomous controller (MFD)
that is shared with other autanalog drivers.
The CTB stands for Continuous Time Block. It is a set of opamps
residing inside the autonomous (aut) analog subsystem. It is
controlled using the autonomous controller (AC), which is a
programmable state machine. The AC is shared across all autonomous
analog peripherals including the SAR, PRB, PTComp, CTB, and CTDAC.
Each CTB block contains two opamps, which need to be configured
together and accessed using the AC. A CTB MFD is used to bring
together the two opamp configurations. AC MFD then references the
combined CTB MFD configuration, and brings together all other
autanalog peripherals into a single AC setup for the application.
Assisted-by: Claude:claude-opus-4.6
Signed-off-by: Richard Mc Sweeney <Richard.McSweeney@infineon.com>
In AP mode, there is not enough heap memory in NWP for a WPA2 connection's
crypto operations. This issue was reported earlier and was fixed in NWP
by reserving 5kB extra memory in TCP/IP bypass mode. However this was
pushed as a hotfix and the fix was lost in the next release.
The NWP code is frozen now and the workaround to fix this issue is to
enable a feature which reserves ~5kB memory.
Removing this macro enables WPS and reserves an 5k extra memory in NWP.
It does not affect any other functionality (such as Wi-Fi IEs).
Signed-off-by: Muzaffar Ahmed <muzaffar.ahmed@silabs.com>
Migrate NXP MCXC, MCXA, MCXN and KE1xZ system PM hooks to the
idle-owned IRQ restore contract.
Select PM_STATE_SET_IRQ_LOCKED for the migrated SoCs. Their pm_state_set()
and pm_state_exit_post_ops() no longer dispatch wake-source IRQs before PM
resume bookkeeping completes.
Remove SoC-side irq_unlock(0) calls. Use the arch PM helpers next to the
low-power instruction in implementations that execute WFI directly.
Keep power_mgmt_soc coverage enabled for the migrated MCXC boards.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Select CPU_HAS_DCACHE on ESP32-S2, S3 and C5 and auto-enable
CACHE_MANAGEMENT in each defconfig when ESP_SPIRAM is selected.
This activates the cache_esp32 driver where it is useful, so
portable sys_cache_data_* calls keep PSRAM and DMA buffers
coherent.
The L1 dcache line size is declared via the cpu@0 devicetree
node so the generic DCACHE_LINE_SIZE Kconfig default picks it
up automatically. SoCs without writeback cache (ESP32, C2, C3,
C6 and H2) are left untouched.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
- Renamed power states to use runtime-idle
for sleep, and suspend-to-idle for deepsleep
- Added soft-off for hibernate
- Added poweroff support mapping to hibernate
Signed-off-by: Richard Mc Sweeney <Richard.McSweeney@infineon.com>
Added PTComp support to PSE84.
This implementation uses the shared autonomous controller (MFD)
with other autanalog drivers.
The PTComp is a programmable threshold comparator inside the
autonomous (aut) analog subsystem. It is controlled using the
autonomous controller (AC), which is a programmable state machine.
The AC is shared across all autonomous analog peripherals including
the SAR, PRB, PTComp, CTB, and CTDAC.
The PTComp block contains two comparators for edge detection and
with a capability for boolean post-processing. These two comparator
instances need to be configured together and accessed using the AC.
A PTComp MFD is used to bring together the two comparator
configurations. AC MFD then references the combined PTComp MFD
configuration, and brings together all other autanalog peripherals
into a single AC setup for the application.
Assisted-by: Claude:claude-opus-4.6
Signed-off-by: Richard Mc Sweeney <Richard.McSweeney@infineon.com>
Add CPU clock-frequency to the bcm2711 device tree and use it to
derive SYS_CLOCK_HW_CYCLES_PER_SEC instead of relying on a
hard-coded value.
Also enable cache management by default for the BCM2711 SoC.
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
Following the removal of the internal Haltium and Lumos platform
abstractions in favor of explicit SOC_SERIES_* checks, add
backward-compatibility aliases so out-of-tree code that still
references the old names keeps building during the deprecation
period, with a clear warning pointing to the new names.
All aliases are tagged [DEPRECATED] and slated for removal in a
future release.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
This commit introduces a new clock control driver for NXP MCXW series
microcontrollers, replacing the previous hardcoded clock initialization
in soc.c with a devicetree-based approach.
Signed-off-by: Albort Xue <yao.xue@nxp.com>
Add support for CONFIG_PM_CUSTOM_TICKS_HOOK.
Enable CONFIG_PM_CUSTOM_TICKS_HOOK if CONFIG_PM and CONFIG_BT are set.
Signed-off-by: Ali Hozhabri <ali.hozhabri@st.com>
Edited help text for Kconfig options related to AP-Protect.
NCSDK-38220 and sdk-nrf#28677.
Follow-up to NCSDK-36611 and sdk-nrf#27088.
Signed-off-by: Grzegorz Ferenc <Grzegorz.Ferenc@nordicsemi.no>
Insert an explicit `. = ALIGN(0x10)` at the end of the flash
text region in every Espressif SoC linker script. The flash MMU
maps code in fixed-size segments and image headers record each
segment with a 16-byte-multiple length, so the boundary between
the text region and whatever follows must land on a clean 16-byte
address. Relying on the preceding `. += 16` padding or `ALIGN(4)`
only guaranteed 4-byte alignment, which left the segment size
off-grid on builds where prior input sections happened to end at
an unaligned offset.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Set DROM_SEG_ORG equal to IROM_SEG_ORG and add a NOLOAD dummy
section in drom0_0_seg that advances past the end of .text.
The MMU allocator advances free_head by irom_len + drom_len
assuming the two segments are adjacent. The previous 8MB gap
left the rodata virtual range unreserved, causing 8MB PSRAM
mapping to overrun .rodata.
Place the esp_psram object in IRAM so PSRAM init does not
depend on flash reads while MSPI clock and tuning registers
are transitioning. Split esp_init_psram into chip-init plus
mmu-map steps and invalidate the flash IROM/DROM ranges in
between so the next flash fetch reloads with the final MSPI
settings.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add power management support for MCXE24x SoC series with
four power states defined in device tree (runtime-idle and
three suspend-to-idle substates: STOP, PSTOP1, PSTOP2).
Implement pm_state_set() to handle state transitions using
the SMC (System Mode Controller) for STOP mode configuration.
When CONFIG_XIP=y, the WFI is executed from a __ramfunc so the
core does not fetch instructions from internal program flash
across the low power entry boundary.
Implement pm_state_exit_post_ops() to restore normal operation
after wakeup. No wake-up controller is required to wake the
core from these substates on this part.
Enable HAS_PM capability for the SoC series. Applications that
opt in to PM should also designate lptmr0 as the system timer
via the 'zephyr,system-timer' chosen property and enable the
node, so the LPTMR tickless driver keeps time across
STOP/PSTOPx without needing a SysTick + LPTMR companion-timer
arrangement.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Configure lptmr0 to use the RTC32K clock source at 32 kHz
(clk-source = 2) instead of the default 1 kHz LPO configuration so
the LPTMR can serve as the Zephyr system timer when an application
designates it via the 'zephyr,system-timer' chosen property and
enables the lptmr0 node.
Switching to LPTMR as the system timer is the preferred path for
PM-capable applications: SysTick's 24-bit counter at high core
frequencies yields a very short maximum sleep window and would
otherwise require a companion idle timer. Leaving the chosen
property unset at the SoC level keeps SysTick as the default for
non-PM applications, so this commit only stages the DT and
Kconfig groundwork; an application or board overlay opts in by
setting 'zephyr,system-timer = &lptmr0' and enabling the node.
Resolve SYS_CLOCK_HW_CYCLES_PER_SEC from the chosen system-timer
node so the value tracks the selected timer, and set
SYS_CLOCK_TICKS_PER_SEC to 1000 when LPTMR is the system timer.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
RT7xx CM33 cores have D-cache enabled on SRAM by default. The SEGGER
RTT control block and ring buffers, when placed in regular .bss, are
held in D-cache after CPU writes and never reach physical SRAM that
J-Link reads — JLinkRTTViewer finds the control block (magic was
written before cache effects accumulated) but no buffer data ever
flows.
When CONFIG_USE_SEGGER_RTT=y, default CONFIG_SEGGER_RTT_SECTION_NONE=y
so the SEGGER source leaves the control block and buffers in plain
.bss subsections under -fdata-sections, then contribute an input
section snippet to the existing CONFIG_NOCACHE_MEMORY region pulling
_SEGGER_RTT, _acUpBuffer and _acDownBuffer into the MPU
non-cacheable area.
Reuses the Zephyr nocache infrastructure with zero SRAM overhead
when RTT is not enabled, and auto-sizes when buffer sizes change.
Verified on mimxrt700_evk/mimxrt798s/cm33_cpu0 with both
samples/basic/blinky (printf + CONFIG_RTT_CONSOLE=y) and
samples/subsys/logging/logger (CONFIG_LOG_BACKEND_RTT=y).
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Certain macros were missing in the NPCK platform, leading to compilation
errors. This commit adds the necessary definitions to restore a
successful build.
Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
Add the MCXC power management implementation and wire it into the SoC
build and Kconfig flow.
Default MCUX_LPTMR_TIMER to y when CONFIG_PM is enabled and the
zephyr,system-timer chosen property points to an LPTMR node, so the
LPTMR serves as the tickless system timer in PM use cases. (Zephyr
4.5 stopped auto-defaulting MCUX_LPTMR_TIMER from the chosen property,
matching the convention later adopted for MCXW7XX.) When LPTMR is
selected, override the SoC-side SysTick default, set
SYS_CLOCK_TICKS_PER_SEC=1024 and derive SYS_CLOCK_HW_CYCLES_PER_SEC
from the chosen LPTMR's clock-frequency. Default WUC to y whenever PM
and an LLWU node are enabled, so the LPTMR system timer driver can
register itself as a wakeup source through the WUC API.
Set OSC0_CR.EREFSTEN once at PM init so the system OSC keeps running
across STOP modes. This keeps ERCLK32K alive as the LPTMR system-timer
clock source while the CPU is suspended; without it the timer would
lose its clock on STOP entry and never wake the CPU.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Both GPIO and RTC IO pad types support pad hold function.
Current implementation is only covering digital GPIOs. If the user
selects an RTC IO pin with `sleep-hold-en`, an `abort()` inside the
HAL can happen, depending on the SoC. Extend the implementation to
handle RTC IO pads through the correct hold path and add proper
validation with a warning for pads that support neither hold type.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
When the MCAN is activated in the DT, configure it's register region
with strong ordered, read and write access.
As CANx accesses the lower or upper 64K SRAM is selected by bits in
register 'SFR_CAN_SRAM_SEL', also configure SRAM and SFR region with
strong ordered, read and write access.
Configure the generic clocks for CANx when it is enabled in the dt.
Signed-off-by: Tony Han <tony.han@microchip.com>
Derive SYS_CLOCK_HW_CYCLES_PER_SEC from the mtimer clock-frequency
devicetree property instead of hard-coding the generic Mi-V default in
Kconfig.
The mtimer clock frequency depends on the Mi-V integration. Add the
corresponding clock-frequency property to the m2gl025_miv board to preserve
the existing 4 MHz behavior.
The PolarFire SoC Mi-V port is left unchanged because it uses a common
1 MHz mtimer clock that is expected to be configured independently of the
CPU clock.
Signed-off-by: Takumi Ando <takumi@spacecubics.com>
Add two cheap sanity checks: data_len must be 4-byte aligned
(ELF segment data always is) and must not exceed the SoC's
DROM mapping window (which bounds the largest possible
legitimate segment). Replace the magic 16 with
ESP_IMAGE_MAX_SEGMENTS and fix the post-loop bound check,
which was off by one due to the post-increment in the while
condition.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
When TF-m is enabled on 54L the ROM_START_OFFSET should
not be overridden, even if MCUboot is enabled.
Signed-off-by: Dag Erik Gjørvad <dag.erik.gjorvad@nordicsemi.no>
Adds initial SoC-level support for the Microchip
PIC32CK GC series, including SoC definition files.
Signed-off-by: Hariharan Arumugam <hariharan.arumugam@microchip.com>
Add MEC175x SoC series support to the Microchip XEC ADC driver.
Refactor the driver to use DTS-encoded GIRQ and PCR properties
instead of series-specific ifdefs, enabling a unified driver
across MEC150x, MEC172x, and MEC175x.
Update mec_adc.h register definitions to support all three SoC
series with proper Kconfig guards for 16-channel ADC variants.
Signed-off-by: Srinivas Edireswarapu <srinivas.edireswarapu@microchip.com>
Include file for mapping DFP macros to follow a common
macro name across multiple SoC for sercom uart g1 driver
Signed-off-by: Fabin V Martin <Fabinv.Martin@microchip.com>
Fix issue in case of rng device is used before
get rng device has been done.
Before calling the entropy_get_entropy_isr()
function, add get rng device procedure.
Signed-off-by: Vincent Tardy <vincent.tardy@st.com>
Edge devices have multiple addresses for the external memory.
SAHB (0x60.., 0x70.. for ns and s access respectively) which
are uncached but programmable and CBUS (0x08.. and 0x18..
for ns and s access respectively) which are cached and improve
performance.
Additionally, cm33 can use both SAHB aliases and CBUS alises
but cm55 can only use SAHB aliases.
Therefore this commit redefines entirely the memory map to
use mapped partitions are offsets from the base region and
selecting the base region accordingly for
the three use cases. (cm33s, cm33ns - for eval board, cm55).
To this selected set USE_DT_CODE_PARTITION
to yes for all cores in defconfig.
Additionally cleaned up config BUILD_OUTPUT_ADJUST_LMA to be
more clear in its use.
Updated the custom linker script with the mapped partitions
updates that were added to the base linker ascript in arm.
Updated the metadata function to handle the addresses
gymnastics.
Signed-off-by: Laura Carlesso <laura.carlesso@infineon.com>
