Setting symbol default value without 'configdefault', or without
explicit 'if' checks of dependencies, results in dependency weakening.
In this case, CACHE_MANAGEMENT is redefined and set to the given
default value even if dependencies D/ICACHE are not enabled.
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
Setting symbol default value without 'configdefault', or without
explicit 'if' checks of dependencies, results in dependency weakening.
In this case, CACHE_MANAGEMENT is redefined and set to the given
default value even if dependencies D/ICACHE are not enabled.
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
Setting symbol default value without 'configdefault', or without
explicit 'if' checks of dependencies, results in dependency weakening.
In this case, ICACHE_LINE_SIZE is redefined and set to the given default
value even if dependency ICACHE is not enabled.
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
Setting symbol default value without 'configdefault', or without
explicit 'if' checks of dependencies, results in dependency weakening.
In this case, DCACHE_LINE_SIZE is redefined and set to the given default
value even if dependency DCACHE is not enabled.
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
Setting symbol default value without 'configdefault', or without
explicit 'if' checks of dependencies, results in dependency weakening.
In this case, ICACHE is redefined and set to the given default value
even if dependencies CPU_HAS_ICACHE is not enabled.
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
Setting symbol default value without 'configdefault', or without
explicit 'if' checks of dependencies, results in dependency weakening.
In this case, DCACHE is redefined and set to the given default value
even if dependencies CPU_HAS_DCACHE is not enabled.
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
Setting symbol default value without 'configdefault', or without
explicit 'if' checks of dependencies, results in dependency weakening.
In this case, DCACHE is redefined and set to the given default value
even if dependencies CPU_HAS_DCACHE is not enabled.
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
Setting symbol default value without 'configdefault', or without
explicit 'if' checks of dependencies, results in dependency weakening.
In this case, DCACHE is redefined and set to the given default value
even if dependencies CPU_HAS_DCACHE is not enabled.
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
Setting symbol default value without 'configdefault', or without
explicit 'if' checks of dependencies, results in dependency weakening.
In this case, DCACHE is redefined and set to the given default value
even if dependencies CPU_HAS_DCACHE is not enabled.
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
Select CPU_HAS_DCACHE in Kconfig directly.
Setting symbol default value without 'configdefault', or without
explicit 'if' checks of dependencies, results in dependency weakening.
So use configdefault to set CONFIG_DCACHE, CONFIG_CACHE_MANAGEMENT
and CONFIG_NOCACHE_MEMORY
And select ARCH_HAS_NOCACHE_MEMORY_SUPPORT as well since it is
not selected at Xtensa arch level.
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
Set the NWP power profile at boot, rather than postponing it until
Bluetooth is enabled. The workaround to postpone it is no longer
needed, as recent NWP firmware versions support setting power
profile prior to configuring Bluetooth TX power.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Introduce the minimum PMC clocks support for sama5d2 SoCs for running
simple Zephyr examples on sama5d2.
Note that the full support for sama5d2 PMC clocks needs to be
implemented later.
Signed-off-by: Tony Han <tony.han@microchip.com>
Add initialization of GPU2D in soc.c to ensure proper hardware setup
during early boot.
Signed-off-by: Radhika Changela <radhika.changela@siliconsignals.io>
Add baseline support for the nRF7120e SoC.
Add nRF7120 support for nrfutil recover, missing previously.
Signed-off-by: Robert Robinson <robert.robinson@nordicsemi.no>
Add board, SoC, and devicetree support for ElemRV-H, an open-source
RISC-V microcontroller built on the Hydrogen platform.
The Hydrogen SoC integrates a VexiiRiscv core (RV32I_Zicsr_Zifencei)
clocked at 50 MHz with UART, GPIO, and pin multiplexer peripherals.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
GPPI resources (channels and group channels) need to be managed on a
single core (cpuapp). If companion cores wants to control PPI
connection then connection need to be established by cpuapp and
companion core can later on control it (enable, disable channels).
GPPI external allocator is a service for allocating and freeing DPPI
connections using IPC communication messages.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Assisted-by: Cursor:auto
Add a SUPC (Supply Controller) source file with a driver API to
control the internal voltage reference (VREF) output used by
ADC/DAC input channels: enable/disable the reference output and
select/read the reference voltage level.
Wire up SUPC initialization in the SoC reset hook. soc_supc_init()
reads the standby-regulator-sel, vref-on-demand, and
vref-standby-mode properties from the supc devicetree node and
configures the voltage regulator and voltage reference behavior
accordingly during early boot.
Convert the common SoC CMakeLists.txt to use zephyr_library() so
the new supc_mchp.c source can be added via
zephyr_library_sources().
Signed-off-by: Syed Maaz <Syed.Maaz@microchip.com>
Cortex-A53 SBC on the Broadcom BCM2710 (BCM2837 die). Adds the
soc/brcm/bcm2710 SoC with the native BCM283x interrupt controllers
(no GIC), booting single-core with the mini-UART console at 115200.
Signed-off-by: Jonathan E. Peace <jep@alphabetiq.com>
The BCM283x GPIO/pinctrl block is register-compatible across the
family, so keep a single definition in soc/brcm/common instead of a
copy per SoC. No functional change.
Signed-off-by: Jonathan E. Peace <jep@alphabetiq.com>
the clang linker does not like quotation marks
in the name, if the memory region has been
defined before without them. The build will
fail if they are not the same. This fixes it.
Signed-off-by: Fin Maaß <info@finmaass.de>
Enable secure boot signing for MAX32672 to support the secure-boot variant
of the SoC.
Add a Kconfig choice for signing algorithm selection (RSA2048/ECDSA256)
with per-SoC defaults set via defconfig choice re-open. Configure
signature section size in the linker script based on the selected
algorithm instead of being hardcoded to 256 bytes.
Various fixes to CMake signing script as follows:
- Enable environment variables in key path by resolving config before
calling sign_app.
- Uppercase applied to SOC name so sign_app can determine the device
correctly.
- Prevent sign_app from running with undefined key path.
Signed-off-by: Ryan Wiebe <ryan.wiebe@analog.com>
Move the BT_RX_STACK_SIZE default out of the HCI driver Kconfig
and into the common Espressif defconfig, next to the other
Bluetooth subsystem defaults.
The BT_ESP32 block is now shared by both architectures instead of
being duplicated under RISCV and XTENSA, so the stack default also
applies to the Xtensa targets.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Replace "WB0x" with full "STM32WB0 series" in one comment of the Kconfig
file for consistency with another comment in the same file and with
the overall naming convention used for STM32 across Zephyr.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Reorganize `select` directives in the per-SoC `Kconfig` files to follow
a consistent logic. The options are separated in three distinct groups,
separated by an empty line and ordered as follows:
- architecture options & CPU model
- generic HW options
- generic SW options
- STM32-specific options
Options inside a group (or subgroup) are sorted in ascending name order.
The "architecture options & CPU model" group shall select these options
in the following order:
- architecture option: `select ARM`
- architecture extensions options: `select ARMxx_xxx`
(for example: `ARMV8_M_DSP`, `ARM_TRUSTZONE_M`)
- CPU model option: `select CPU_CORTEX_Mmm`
Note: this organization is such that sorting by ascending option names
should place options in the proper subgroup automatically.
The "generic HW options" shall select options in the following order:
- General Cortex CPU options: `select CPU_CORTEX_M_HAS_xxx`
(for example: `CPU_CORTEX_M_HAS_DWT`)
- Model-specific CPU options: `select CPU_CORTEX_Mmm_HAS_xxx`
(for example: `CPU_CORTEX_M0_HAS_VECTOR_TABLE_REMAP`)
- Generic CPU options: `select CPU_HAS_xxx`
(for example: `CPU_HAS_ARM_MPU`, `CPU_HAS_FPU`)
- Generic "has hardware" options: `select HAS_xxx`
(for example: `HAS_SWO`)
Note: this organization is such that sorting by ascending option names
should place options in the proper subgroup automatically.
The "generic SW options" group shall both select options that indicate
implementation of support for a software capability (e.g., `HAS_PM`),
and options that enable a software feature needed by the SoC for proper
operation (e.g., `SOC_EARLY_INIT_HOOK`). There is no ordering logic in
this group other than sorting by ascending option names.
The "STM32-specific options" group shall `select HAS_STM32CUBE` as its
first directive and, for applicable series `select STM32_HAL2` as its
second directive. All other applicable options shall follow with no
ordering logic other than sorting by ascending option names.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Include file for mapping DFP macros to follow a common
macro name across multiple SoC for sercom uart g1 driver
Signed-off-by: Fabin V Martin <Fabinv.Martin@microchip.com>
Add DTS and Kconfig support for the Silicon Labs EFR32BG21 (Blue Gecko)
series, introducing the EFR32BG21B010F1024IM32 variant.
Temporarily point `hal_silabs` to `pull/183/head` to pull in the
required HAL support for this SoC.
Signed-off-by: Martin Moya <martin.moya@focus.uy>
MISRA C:2012 Rule 8.2 requires every parameter in a function type to be
named, including the parameters of function pointer parameters.
The XMC4xxx GPIO interrupt helper and the XMC7200 system interrupt
helper declared their callback parameters with bare types.
Name them after the arguments the documentation or the
definitions already use. No functional change.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Add support for tracking heavy sleep duration on the RTS5912/RTS5915
using the low-frequency RTMR (RTOS Timer) 32KHz clock domain.
- Expose rts5912_clock_capture_low_freq_timer(),
rts5912_clock_compensate_system_timer(), and
rts5912_clock_get_sleep_ticks() in soc_clock.h.
- Capture timer reading prior to WFI in rts5912_heavy_sleep() and
accumulate elapsed sleep cycles upon wake-up after clock restoration.
Signed-off-by: Keith Short <keithshort@google.com>
Assisted-by: Antigravity:gemini-1.5-pro
Use the chosen zephyr,system-timer property to indicate which timer is used
as system timer and move the timer selection from the board to the SoC
itself.
Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>
Add workaround and Kconfig for nRF53 Series Anomaly 166,
that affects VREGMAIN in LDO mode.
Workaround remains disabled by default.
Signed-off-by: Nikodem Kastelik <nikodem.kastelik@nordicsemi.no>
Add the NXP LPC54628 (Cortex-M4F, 512 KB flash, 200 KB SRAM) as a second
SoC in the existing lpc54xxx series, alongside the LPC54114. The series
already provides the shared soc.h, linker script and IOCON pinctrl
header, so only the LPC54628-specific parts are added: the soc.yml and
Kconfig entries, the system PLL clock init in soc.c (clocked from the
external crystal, up to 220 MHz) selected by CONFIG_SOC_LPC54628 in
clock_init(), and the SoC devicetree with syscon/reset, IOCON pinctrl,
GPIO, PINT, GINT, the FLEXCOMM instances, the on-chip IAP flash, and the
two M_CAN instances. SystemInit is provided by the MCUXpresso SDK; the
LPC54628 has no startup assembly and runs it from soc_reset_hook.
Signed-off-by: Marvin Gnad <marvin.gnad@gmail.com>
Run-time FW version check can be performed in the
stm32wb HCI driver, when initializing the Bluetooth IPM.
The wireless firmware information can be retrieved
(using the SHCI_GetWirelessFwInfo()) and verified
if it match or not.
Added FUS version.
Signed-off-by: Eric Mechin <eric.mechin@st.com>
Enable on such boards
- lpcxpresso55s36 (LPC55S36)
- lpcxpresso55s59 (LPC55S6x)
- frdm_mcxn947 (MCXN947)
- frdm_rw612 (RW612)
- rd_rw612_bga (RW612)
For LPCXpresso55S69 board. The PowerQuad uses SRAM4 as private
working memory when enabled.
RT595 and RT685 can't be tested with the tests/subsys/dsp/basicmath/
because the source data is placed in flexspi Flash which can't
be accessed by PowerQuad.
Assisted-by: Claude Code:claude-opus-4-6
Signed-off-by: Jason Yu <zejiang.yu@nxp.com>
Select Arm M-profile Vector Extension support for RA8M1 SoCs.
RA8M1 devices use Cortex-M85 cores, which support integer and floating
point MVE. Model this as an SoC capability instead of deriving it from
CMSIS-DSP sample usage.
Signed-off-by: Mahad Faisal <mf3377@drexel.edu>
Reassign IRQs so that none are of level 3. Modify peripheral mapping
through INPUTMUX and modify IRQ numbers in SoC's DT.
This is due to the fact that the default exception handling level
of the DSP (EXCM_LEVEL) is 2, thus L3 IRQs can't be masked during
critical sections.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
Assisted-by: Claude:claude-opus-4.8
Reassign IRQs so that none are of level 3. Modify peripheral mapping
through INPUTMUX and modify IRQ numbers in SoC's DT.
This is due to the fact that the default exception handling level
of the DSP (EXCM_LEVEL) is 2, thus L3 IRQs can't be masked during
critical sections.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
Assisted-by: Claude:claude-opus-4.8
