Commit graph

5973 commits

Author SHA1 Message Date
Jimmy Zheng
65edd8433c soc: riscv: andes_v5: add Andes EXEC.IT option
Andes EXEC.IT (Execution on Instruction Table) is supported by Andes
toolchain only. Andes toolchain will replaces suitable 32-bit instructions
with the 16-bit "exec.it <INDEX>" in which <INDEX> points to a
corresponding 32-bit instruction in look up table.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-07-17 10:10:31 +00:00
Jimmy Zheng
004e00a0bd soc: riscv: andes_v5: add RV32E_CPU option
Add CONFIG_RV32E_CPU for AE350 platform integrated with Andes RV32E core,
such as N22, D23 core.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-07-17 10:10:31 +00:00
Jimmy Zheng
d5c4bd6830 soc: riscv: andes_v5: support RISC-V C extension
Enable RISC-V C extension for Andes core.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-07-17 10:10:31 +00:00
Jimmy Zheng
9c7f0376b8 soc: riscv: andes_v5: support PMP and USERSPACE
Enable PMP and set PMP granularity to 8 for most of ae350 bitstream.
This commit also make MPU_ALIGN() apply to __rom_region_end in XIP system.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-07-17 10:10:31 +00:00
Jimmy Zheng
bf0e01bee2 soc: riscv: andes_v5: refine Andes PMA
Refine PMA driver and define MPU_ALIGN() to PMA granularity in
RAM_SECTIONS, otherwise MPU_ALIGN() is defined to PMP granularity.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-07-17 10:10:31 +00:00
Jimmy Zheng
de1cd06294 soc: riscv: andes_v5: update ae350 linker.ld
Synchronize ae350 linker.ld with riscv generic linker.ld and workaround
kernel object address may be 0x0 in XIP system.

Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
2023-07-17 10:10:31 +00:00
L Lakshmanan
71244acd22 board: ti_am62x_sk_m4: Added board files for TI AM62X SK
Added configuration and documentation files for the AM62x board
M4 core.

Signed-off-by: L Lakshmanan <l-lakshmanan@ti.com>
2023-07-16 07:33:34 -04:00
L Lakshmanan
0e97c9d14d soc: ti_k3: Added SoC files for Cortex M4F on ti_am62x_sk
Added SoC support files for the Cortex M4F core on the TI AM62X SK EVM.

Signed-off-by: L Lakshmanan <l-lakshmanan@ti.com>
2023-07-16 07:33:34 -04:00
Marc Herbert
35e8e6fa03 soc/xtensa/nxp_adsp/CMakeLists.txt: use new WEST_SIGN_OPTS variable
Align `soc/nxp_adsp` with new `WEST_SIGN_OPTS` option added to
`soc/intel_adsp` by recent commit d98a7c2f8d ("soc: xtensa: cmake: add
new WEST_SIGN_OPTS variable").

This allows per-board rimage customization at the CMake level. Example
in `zephyr/boards/xtensa/nxp_adsp_NEWBOARD/board.cmake`:

  set(WEST_SIGN_OPTS -- -c rimage/config/special.toml)

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2023-07-13 14:19:26 +02:00
Guillaume Gautier
8432081f51 soc: arm: st_stm32: stm32wba: Add LPTIM to Kconfig
For STM32WBA, enable LPTIM if Power management is enabled

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2023-07-12 11:48:10 +02:00
Guillaume Gautier
38722ce9d0 soc: arm: st_stm32: stm32wba: Add Power support
Add Power support

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2023-07-12 11:48:10 +02:00
Tim-Marek Thomas
5d75940ae3 boards: riscv: neorv32: Updates compatibility to neoverse v1.8.6
With NEORV32 v1.8.2 the UART module was changed to a simpler
implementation. This updates the UART driver for the open-source NEORV32
RISC-V compatible processor system (SOC).

Signed-off-by: Tim-Marek Thomas <thomas@sra.uni-hannover.de>
2023-07-11 18:19:55 +00:00
Tim Lin
0960bb3066 ITE: drivers/i2c: Add I2C target driver used buffer mode
Add I2C target driver used buffer mode. The maximum accessible buffer
is 2044 bytes, the default is 256 bytes.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2023-07-11 15:50:13 +02:00
Guillaume Gautier
3bd3f8d1c6 soc: arm: st_stm32: stm32wba: Add soc config for STM32WBA
Add soc config for STM32WBA SoC series

Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
2023-07-11 15:05:05 +02:00
Mykola Kvach
634e73dd21 soc: arm64: add PFC files to Renesas r8a77961 Gen3 SoC
Add Pin Function Controller tables of registers and their bits
for ARM64 Renesas R-Car family. With this changes we can use
Renesas PFC driver for configuring bias and driving capabilities.

Add only needed driver strength and bias pins to PFC,
e.g. SDx and UART TX/RX pins.

Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
2023-07-11 11:17:41 +02:00
Mykola Kvach
38675f2b92 soc: arm64: add support of r8a77961
Add support of r8a77961 SoC to gen3 series.
Create a dtsi file with a common part for both r8a77951 and r8a77961.

Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
2023-07-11 11:17:41 +02:00
Mykola Kvach
e0cf31483b soc: arm64: add PFC files to Renesas r8a77951 Gen3 SoC
Add Pin Function Controller tables of registers and their bits
for ARM64 Renesas R-Car family. With this changes we can use
Renesas PFC driver for configuring bias and driving capabilities.

Note: some of files copy-pasted from Renesas Arm 32
      SoC directory and this commit is a temporary
      solution, we need to rework it in order to use
      the same source files for both architectures.

Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
2023-07-11 11:17:41 +02:00
Mykola Kvach
d0472aae7a soc: arm64: add Renesas Rcar Gen3 SoC support
Add files for supporting arm64 Renesas r8a77951 SoC.
Add config option CPU_CORTEX_A57.

Enable build of clock_control_r8a7795_cpg_mssr.c for
a new ARM64 SoC R8A77951.

Signed-off-by: Mykola Kvach <mykola_kvach@epam.com>
2023-07-11 11:17:41 +02:00
Bill Waters
541482ff20 driver: i2c: infineon: Adding XMC4 I2C driver
- This includes the driver, test app, and sample app
- Only the boards\arm\xmc47_relax_kit board is supported for now

Signed-off-by: Bill Waters <bill.waters@infineon.com>
2023-07-11 09:43:19 +02:00
Daniel Leung
25c6553edd soc: intel_adsp/ace: use functions to do CPU power control
Instead of relying on direct memory access via structs to
control CPU power and status, using inline functions instead
to hide the details. This makes reading the common code a bit
cleaner.

The function names are generic and not architecture or
platform specific, in an attempt to ease future arch or
platform additions with code reuse. Or else we would need to
rename these.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2023-07-10 16:13:03 +02:00
Tomasz Leman
3764814831 intel_adsp: boot: d3: hp sram reinit
Adding HP SRAM initialization in D3 power state exit procedure.

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2023-07-10 16:08:32 +02:00
Marek Matej
0038620b37 soc: xtensa: disable SPIRAM when MCUBOOT
Some boards has ESP_SPIRAM enabled by default, which is
causing issues when MCUboot is used as 2nd bootloader.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2023-07-10 15:10:14 +02:00
Nikolay Agishev
a983abe426 ARC: Turn off stack checking for hsdk4xd
Turn off unsupported configuration for hsdk4xd

Signed-off-by: Nikolay Agishev <agishev@synopsys.com>
2023-07-10 09:29:43 +02:00
Iuliana Prodan
dc49a314fd west: sign.py: fix sign when CONFIG_KERNEL_BIN_NAME is used
This fixes the following build error:
```
zephyr/zephyr.elf', needed by 'zephyr/zephyr.ri', missing and no known
rule to make it
```
This appears when CONFIG_KERNEL_BIN_NAME is used.

Therefore, do not use zephyr.elf since some samples might be called
based on CONFIG_KERNEL_BIN_NAME.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
2023-07-10 09:29:33 +02:00
Daniel Mangum
43b057a7ce soc: neorv32: Fix spelling in reset.S
Fixes minor misspelling of instruction in the neorv32 reset.S.

Signed-off-by: Daniel Mangum <georgedanielmangum@gmail.com>
2023-07-09 17:50:09 +00:00
Florian Grandel
38e2eb8fe6 soc: ti: cc13/26xx: clean up include hierarchy
Removes duplicate code and inconsistencies in the naming of the
cc13xx_cc26xx devicetree and RTC driver hierarchy and alignes it with
the actual TI product series naming hierarchy.

Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
2023-07-07 18:46:24 -04:00
Andrzej Kuros
abd90085ac soc: arm: nrf53: workaround pop lr after wfi crash
On nRF5340 net core it was observed that when `wfi` instruction was
followed by `pop {r0, lr}` in the `arch_cpu_idle` function,
the value of `lr` sometimes got read as 0 from memory despite
having correct value stored in the memory.

This commit inserts additional `nop` instruction after waking up
to delay access to the memory.

Signed-off-by: Andrzej Kuroś <andrzej.kuros@nordicsemi.no>
2023-07-07 14:32:27 +02:00
Marc Desvaux
4293835192 soc : arm: st_stm32: stm32h5: add linker for STM32H5X
add some modifications for linker

Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
2023-07-07 10:06:54 +00:00
Mulin Chao
2cf3caa11c driver: wdt: npcx: add WDT_OPT_PAUSE_HALTED_BY_DBG support.
This CL adds WDT_OPT_PAUSE_HALTED_BY_DBG support by enabling freeze mode.

Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
2023-07-07 09:19:50 +02:00
Manuel Arguelles
405160ca62 boards: mr_canhubk3: enable LPUART serial driver
Reuse existing MCUX-based shim driver for LPUART that is compatible with
the hardware block in S32K344. DMA is not yet supported.

Use the board's debug connector (P6 / LPUART2) as default console.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-07-06 14:19:23 -05:00
Manuel Arguelles
00125a4d1e soc: nxp_s32: generalize pinctrl header for all family
Unify the pinctrl_soc.h header for all the NXP S32 family by using
the HAL macros that expose the features supported on specific
devices. This approach still need a different binding for each device to
expose in DT different properties and allowed values.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-07-06 14:19:23 -05:00
Manuel Arguelles
8a47dd5ff8 soc: nxp: s32k3: enable clock control
Enable clock control by default on S32K344 SoCs and add clock
definitions.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-07-06 14:19:23 -05:00
Manuel Arguelles
b22f1162f3 soc: nxp: s32k: support minimal power and reset
Introduce minimal power initialization for NXP S32 SoCs and allow to
reset the SoC through the sys_reboot() API.

Presently only S32K3 SoCs is supported but it can be extended later to
other NXP S32 SoCs, hence it's placed in a common directory.

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-07-06 14:19:23 -05:00
Manuel Arguelles
d2985f118a soc: arm: introduce support for NXP S32K344
The S32K3 MCUs are 32-bit Arm Cortex-M7-based microcontrollers with a
focus on automotive and industrial applications. The S32K344 features
a lock-step core, internal flash, RAM and TCM with ECC.

Co-authored-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
Co-authored-by: Cong Nguyen Huu <cong.nguyenhuu@nxp.com>
Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-07-06 14:19:23 -05:00
Benedikt Schmidt
42051fc2d4 dts: arm: st: add STM32L451
Add the MCU STM32L451.

Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
2023-07-06 09:46:14 +00:00
Gerard Marull-Paretas
fcaa259e22 soc: arm: remove all unnecessary NMI_INIT() calls
NMI_INIT() is now a no-op, so remove it from all SoC code. Also remove
the irq lock/unlock pattern as it was likely a cause of copy&paste when
NMI_INIT() was called.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-07-05 09:15:36 +02:00
Sumit Batra
0ae7010946 soc: rt10xx: fix the sequence of Enet2 ref clk enablement
This patch sets ENET2 ref clock to be generated by External OSC

ENET2 ref clock direction as output

ENET2 ref clk frequency to 50MHz

Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
2023-07-03 15:24:00 -05:00
Manimaran A
f6eeb9dc84 soc: MEC1701: Removed Microchip MEC1701
Removed MEC1701 SOC specific sources

Signed-off-by: Manimaran A <manimaran.a@microchip.com>
2023-07-01 12:38:07 +02:00
Manuel Argüelles
c651dfbb2b soc: nuvoton_numaker: add guard in defconfg
It must be guarded so the option selection doesn't appear at root level.

Fixes #59876

Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
2023-06-30 16:47:51 +02:00
Keith Packard
710422ec5e include/zephyr: Fix linker scripts to define _end after all static RAM data
The Zephyr linker scripts have inconsistent ordering of various chunks of
data which lands in RAM at runtime. This leads to the value of _end not
being consistently defined as the maximum address of static variables used
in the application.

Create a helper linker fragment, zephyr/linker/ram-end.ld, which can be
included after the last possible definition of RAM data, that consistently
sets _image_ram_end, _end and z_mapped_end.

Signed-off-by: Keith Packard <keithp@keithp.com>
2023-06-28 08:41:02 +00:00
Serhiy Katsyuba
431108d89e intel_adsp: ace: Restore IDC interrupt on D3 exit
After exiting D3 state if IMR context save is enabled, IDC interrupt
must be re-enabled again for all cores.

Signed-off-by: Serhiy Katsyuba <serhiy.katsyuba@intel.com>
2023-06-28 06:50:27 +00:00
cyliang tw
51d57f612d drivers: pinctrl: add pin group for NuMaker pinctrl
Update Nuvoton numaker series pinctrl, let support pin group.

Signed-off-by: cyliang tw <cyliang@nuvoton.com>
2023-06-28 06:49:38 +00:00
Manojkumar Subramaniam
6e887e3f61 soc: riscv: Add initial support for Efinix Sapphire SoC
- It's a riscv privilege spec SoC

Signed-off-by: Manojkumar Subramaniam <manoj@electrolance.com>
2023-06-27 12:09:57 +00:00
Anas Nashif
7584c17374 intel_adsp: restructure dmic headers and move regs to soc
The ifdefs in in dmic headers is getting out of control and makes
maintainence very ddifficult, especially when having to maintain out of
tree SoCs sharing the same data and information.

Keep header clean and per SoC and share some common registers in one
place instead avoiding confusion and making it easier to read and
maintain.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-06-23 14:27:44 -04:00
Anas Nashif
c62e55973b intel_adsp: remove deprecated cache macros
SOC_DCACHE_FLUSH and SOC_DCACHE_INVALIDATE are not being used anywhere.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2023-06-23 11:14:08 -04:00
Alberto Escolar Piedras
7ee41b8776 soc inf (native): Refactor into a top and bottom
Where the bottom is the only one which interacts with
the host operating system.
And the top the only one that interacts or is aware
of the hosted operating system (Zephyr).

The bottom uses the native simulator CPU
start/stop emulation.
By now we replicate its code as a provisional measure,
until the native simulator becomes standard.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2023-06-23 12:16:26 +02:00
Alberto Escolar Piedras
bd66c1d953 arch POSIX: Refactor into a top and bottom
Where the bottom is the only one which interacts with
the host operating system, and does not necessarily
need to know about the Zephyr OS.
This is in preparation for the native simulator,
which which the bottom is also fully Zephy agnostic.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2023-06-23 12:16:26 +02:00
Florian Grandel
b245012ca2 drivers: ieee802154: cc13/26xx_subg: R-to-P link workaround
A known issue exists that does not allow a CC13/26x2R device to
establish a link to a CC13/26x2P device unless the capacitor array is
tuned to a non-default value in the P device.

See SimpleLink(TM) cc13xx_cc26xx SDK 6.20+ Release Notes, Known Issues.

Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
2023-06-23 09:20:55 +02:00
Alberto Escolar Piedras
8b760196df soc posix: Refactor native_tasks into own file
The native_tasks logic is unrelated to the remaining
of the soc logic (which handles CPU start/stopping)
refactor it out into its own file.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2023-06-23 08:59:21 +02:00
Alberto Escolar Piedras
9e3d5c89e9 soc inf (POSIX): Correct Kconfig option description
Let's remove the native_posix part from the SOC description
and just refer to "native".

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2023-06-23 08:59:21 +02:00