Commit graph

5973 commits

Author SHA1 Message Date
Alberto Escolar Piedras
38b9120129 arch posix: native tasks header: Add missing include
The native_tasks header requires the toolchain header.
Let's include it directly instead of requiring users
of this header to include it before.

Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
2023-06-23 08:59:21 +02:00
Andrey Borisovich
23b3cae1b1 inte_adsp: ipc: prevent ipc message send during Device power transition
When CONFIG_PM_DEVICE is enabled IPC Device may be during power transition
during a call to intel_adsp_ipc_send_message function.
Changed signatures of intel_adsp_ipc_send_message and its sync version
to return int and negative error codes on error.
On attempt to send IPC message during Device power transition
-ESHUTDOWN error code is returned, on busy state -EBUSY.
Updated all function references.

Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
2023-06-22 06:14:57 -04:00
Andrey Borisovich
355f8cfe4f intel_adsp: ipc: device support D3 power state change
When option CONFIG_PM_DEVICE is enabled, IPC driver is capable
of entering D3 power state described as PM_DEVICE_ACTION_SUSPEND
(and leaving that state - powering back to PM_DEVICE_ACTION_ACTIVE).
New power control callbacks 'ipc_power_control_api' are introduced for
use during power state transisions. They allow Zephyr application
specific code to be executed.

Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
2023-06-22 06:14:57 -04:00
Andrey Borisovich
1d58b1b83f intel_adsp: mem_window: reinitialize after idle exit
Exiting idle state requires to reinitialize all memory window
instances to flush the cached memory.
Added function that calls initialization of devices during runtime.

Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
2023-06-22 06:14:57 -04:00
Andrey Borisovich
7595cafb02 intel_adsp: timer: implemented sys_clock_idle_exit function
Generic header for system clock allows to define a sys_clock_idle_exit
function for the clock implementation.
Implemented the function in the intel_adsp_timer to reinitialize
device driver after the idle exit state.

Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
2023-06-22 06:14:57 -04:00
Lucas Tamborrino
e229898caf drivers: pinctrl: esp32xx: allow internal loopback
Provides a way to use pinctrl to allow internal loopback
on a peripheral pin for testing purposes.
This is done by using output-enable on a input pin and
input-enable on a output pin.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2023-06-22 08:13:36 +00:00
Florian Grandel
c6c93e394d soc: cc13x2_cc26x2 series: enable RTT support
All Cortex-M processors can support RTT by default. This change enables
RTT support for the cc13xx/cc26xx SoC series (tested in hardware on
CC1352R).

Signed-off-by: Florian Grandel <fgrandel@code-for-humans.de>
2023-06-21 20:02:50 -04:00
Lucas Tamborrino
ba3766a75f debug: coredump: xtensa: add esp32s2
Add coredump support for esp32s2.

Signed-off-by: Lucas Tamborrino <lucas.tamborrino@espressif.com>
2023-06-21 16:06:06 -04:00
Huifeng Zhang
c1ecb8faaa arch: arm: enable FPU and FPU sharing for v8r aarch32
This commit is to enable FPU and FPU_SHARING for v8r aarch32.

Signed-off-by: Huifeng Zhang <Huifeng.Zhang@arm.com>
2023-06-21 16:06:08 +02:00
cyliang tw
c448dceb57 drivers: reset: add support for NuMaker series reset
Add Nuvoton numaker series reset controller support.

Signed-off-by: cyliang tw <cyliang@nuvoton.com>
2023-06-21 09:26:00 +00:00
cyliang tw
4ad399d54d drivers: clock_control: add support for Nuvoton numaker series CLK
Add Nuvoton numaker series clock controller support, including:
1.  Do system clock initialization in z_arm_platform_init().
2.  Support peripheral clock control API equivalent to BSP
    CLK_EnableModuleClock()/CLK_SetModuleClock().

Signed-off-by: cyliang tw <cyliang@nuvoton.com>
2023-06-21 09:26:00 +00:00
cyliang tw
5879810137 drivers: pinctrl: add support for NuMaker series pinctrl
Add Nuvoton numaker series pinctrl support.

Signed-off-by: cyliang tw <cyliang@nuvoton.com>
2023-06-21 09:26:00 +00:00
cyliang tw
512371b75b soc: arm: add support for nuvoton numaker m46x series
Add initial support for nuvoton numaker m46x SoC series including
basic init.

Signed-off-by: cyliang tw <cyliang@nuvoton.com>
2023-06-21 09:26:00 +00:00
Adrian Warecki
64b2246dbc soc: adsp: clk: Add multiple clock sources support for dai
Added a new function to check whether a clock source is supported by a
platform and to retrieve its frequency.

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
2023-06-20 14:19:13 -04:00
Adrian Warecki
1a4bc7580b adsp: Rename cpu clock related functions
The word cpu was added to the names of functions, structs, types
and definitions to disambiguate the names and make room in the namespace
for soc clock control functions.

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
2023-06-20 14:19:13 -04:00
Adrian Warecki
b9e5cf5110 adsp: ace: ace_dfpmccu structure field description
Added ace_dfpmccu structure field descriptions to make the code more
readable.

Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
2023-06-20 14:19:13 -04:00
Jaska Uimonen
a8b28f13c1 soc: intel_adsp: cavs: add simple IMR functionality
Add simple mechanism to load the image from IMR memory. Basically we are
only setting a flag in power off for the next boot to jump to existing
image in IMR.

Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
2023-06-20 09:28:56 +01:00
Piotr Wojnarowski
562716d709 soc: arm64: xenvm: Move GIC version to DT
Move the GIC version to the device tree for xenvm
to improve readability

Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
2023-06-17 08:01:46 -04:00
Piotr Wojnarowski
bc8b234d9c soc: arm64: ls1046a: Move GIC version to DT
Move the GIC version to the device tree for ls1046a
to improve readability

Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
2023-06-17 08:01:46 -04:00
Piotr Wojnarowski
6b004bc1b9 soc: arm64: am6x: Move GIC version to DT
Move the GIC version to the device tree for am6x
to improve readability

Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
2023-06-17 08:01:46 -04:00
Piotr Wojnarowski
0e537bc04e soc: arm64: rk3399: Move GIC version to DT
Move the GIC version to the device tree for rk3399
to improve readability

Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
2023-06-17 08:01:46 -04:00
Piotr Wojnarowski
2ba2e1dc3a soc: arm64: intel_socfpga: Move GIC version to DT
Move the GIC version to the device tree for intel_socfpga
to improve readability

Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
2023-06-17 08:01:46 -04:00
Piotr Wojnarowski
7908d7556c soc: arm64: nxp_imx: Move GIC version to DT
Move the GIC version to the device tree for nxp_imx
to improve readability

Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
2023-06-17 08:01:46 -04:00
Piotr Wojnarowski
7626426f27 soc: arm64: qemu: Move GIC version to DT
Move the GIC version to the device tree for the QEMU platforms
to improve readability

Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
2023-06-17 08:01:46 -04:00
Piotr Wojnarowski
184440239e soc: arm64: mimx9: Move GIC version to DT
Move the GIC version to the device tree for mimx9
to improve readability

Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
2023-06-17 08:01:46 -04:00
Piotr Wojnarowski
03aa363a6c soc: arm64: viper: Move GIC version to DT
Move the GIC version to the device tree for viper
to improve readability

Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
2023-06-17 08:01:46 -04:00
Piotr Wojnarowski
ff9fe7271a soc: arm64: fvp_aemv8: Move GIC version to DT
Move the GIC version to the device tree for fvp_aemv8{a,r}
to improve readability

Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
2023-06-17 08:01:46 -04:00
Piotr Wojnarowski
fc29f73a29 soc: arm: xilinx_zynqmp: Move GIC version to DT
Move the GIC version to the device tree for xilinx_zynqmp
to improve readability

Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
2023-06-17 08:01:46 -04:00
Piotr Wojnarowski
0835a99fac soc: arm: renesas_rcar: Move GIC version to DT
Move the GIC version to the device tree for renesas_rcar
to improve readability

Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
2023-06-17 08:01:46 -04:00
Piotr Wojnarowski
48ba2aec6a soc: arm: cyclonev: Move GIC version to DT
Move the GIC version to the device tree for cyclonev
to improve readability

Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
2023-06-17 08:01:46 -04:00
Piotr Wojnarowski
bca43d3eaf soc: arm: nxp_s32: Move GIC version to DT
Move the GIC version to the device tree for nxp_s32
to improve readability

Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
2023-06-17 08:01:46 -04:00
Piotr Wojnarowski
95c1a7e83f soc: arm: xilinx_zynq7000: Move GIC version to DT
Move the GIC version to the device tree for xilinx_zynq7000
to improve readability

Signed-off-by: Piotr Wojnarowski <pwojnarowski@antmicro.com>
2023-06-17 08:01:46 -04:00
Manimaran A
0f6cb5edcd drivers: ps2: microchip: Low power and wakeup enabled
ps2 driver updated to support low power and wakeup.

Signed-off-by: Manimaran A <manimaran.a@microchip.com>
2023-06-17 07:59:07 -04:00
Marcin Zapolski
f9baca493c soc: arm: stm32l4: Add STM32L4Q5 support
Add STM32L4Q5 to the list of supported SOCs.
Fix copy-paste error in STM32L4P5 SOC file.

Signed-off-by: Marcin Zapolski <mz4pol@gmail.com>
2023-06-17 07:56:49 -04:00
Gerard Marull-Paretas
c0bc9f974f drivers: pinctrl: add TI CC32XX driver
Add a new pinctrl driver for TI CC32XX SoC. The driver has not been
tested, just implemented following datasheet specs and checked that it
compiles. Consider this as a best-effort driver to remove custom pinmux
code in board files.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-06-17 07:55:43 -04:00
Daniel DeGrasse
9c6853c42f soc: arm: nxp_imx: do not enable RT boot header for CM4 core
Disable RT boot header for CM4 core. This will ensure the boot header is
not present when building an application targeting RAM on the CM4.

Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
2023-06-17 07:50:46 -04:00
Carlo Caione
fc480c9382 riscv: privileged: Add support for CLIC vectored mode
Zephyr currently only supports CLINT direct mode and CLINT vectored
mode. Add support for CLIC vectored mode as well.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2023-06-17 07:48:52 -04:00
Carlo Caione
6160383ec7 riscv: Rename RISCV_MTVEC_VECTORED_MODE to RISCV_VECTORED_MODE
Before adding support for the CLIC vectored mode, rename
CONFIG_RISCV_MTVEC_VECTORED_MODE to CONFIG_RISCV_VECTORED_MODE to be
more generic and eventually include also the CLIC vectored mode.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2023-06-17 07:48:52 -04:00
Khor Swee Aun
5bf2260e90 soc: riscv: riscv-privileged: INTEL Nios V/g support
Add support for INTEL FPGA Nios V/g RISC-V based Processors.
Also amended SOC_NIOSV_M to use ATOMIC_OPERATIONS_BUILTIN.

Signed-off-by: Khor Swee Aun <swee.aun.khor@intel.com>
2023-06-17 07:34:05 -04:00
Jaska Uimonen
339b00de11 soc: xtensa: intel_adsp: fix memory bank shutdown
Amount of memory banks should vary depending on platform, otherwise
power down sequence might result in ipc timeout as the memory used by
the ipc itself is shutdown.

Lift the needed defines from sram.c to adsp_memory.h and shorten the
names to avoid collision with sof code. No functional change to sram.c.

Signed-off-by: Jaska Uimonen <jaska.uimonen@linux.intel.com>
2023-06-17 07:31:11 -04:00
Flavio Ceolin
5dfaf23f47 xtensa: intel_adsp: lnl: Fix dspcs struct
This is struct is used to access to contiguous registers for each core
and lnl has 5.

Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
2023-06-17 07:30:21 -04:00
Gerard Marull-Paretas
c59b57c0be soc: esp32*: do not enable HAS_DYNAMIC_DEVICE_HANDLES
It doesn't make sense to select this option at SoC level. This feature
is meant for subsystems/modules that need device handles to be
modifiable at runtime.

Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
2023-06-15 10:09:26 -04:00
Carlo Caione
8eeb5c992e riscv: Move directory to *-privileged
Because the spec is "privileged" not "privilege".

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2023-06-09 11:46:29 -04:00
Carlo Caione
edd3437826 riscv: Rename Kconfig symbol to *_PRIVILEGED
Rename SOC_FAMILY_RISCV_PRIVILEGE to SOC_FAMILY_RISCV_PRIVILEGED because
the spec is "privileged".

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2023-06-09 11:46:29 -04:00
Pierre-Louis Bossart
b871138fae soc/intel_adsp: fix typo in L1EXP definition
The field offset is incorrect, L1EXP is at bit 24 and L1ETP at bit 25.

Fixes: cc6e9c094a ("soc/intel_adsp: Low level HDA driver and tests")
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
2023-06-06 17:20:01 -04:00
Carlo Caione
7a48ad34d9 nordic: Rely on internal busy_wait implementation for QEMU
The Nordic board are selecting CONFIG_ARCH_HAS_CUSTOM_BUSY_WAIT by
default and rely on some HAL code to implement a cycle accurate busy
delay loop.

This is in general fine for real hardware but when QEMU and emulation is
taken into account, a cycle accurate busy wait implementation based on
delay in executing machine code can be misleading.

Let's take for example qemu_cortex_m0 (that is based on the nRF51
chipset) and this code:

  uint32_t before, after;

  while (1) {
      before = k_cycle_get_32();
      k_busy_wait(1000 * 1000);
      after = k_cycle_get_32();
      printk("diff cycles: %d\n", after - before);
  }

With CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=1000000 this diff cycles should
be always around 1000000, in reality when executed with:

  qemu-system-arm -cpu cortex-m0 -machine microbit -nographic
      -kernel build/zephyr/zephyr.elf

This results in something like this:

  diff cycles: 22285
  diff cycles: 24339
  diff cycles: 21483
  diff cycles: 21063
  diff cycles: 21116
  diff cycles: 19633

This is possibly due to the fact that the cycle accurate delay busy loop
is too fast in emulation.

When dealing with QEMU let's use the reliable busy loop implementation
based on k_cycle_get_32() instead.

Signed-off-by: Carlo Caione <ccaione@baylibre.com>
2023-06-05 20:20:54 -04:00
TOKITA Hiroshi
56f64f68ac soc: riscv: gd32vf103: Fix SYS_CLOCK_HW_CYCLES_PER_SEC to 27000000
As a result of the 11a2107d991b("riscv: timer: driver revamp") commit,
gd32vf103 no longer works properly.

In the
c9c04e491e0f("soc: riscv: Add initial support for GigaDevice GD32V SoC")
that is the first commit of implementation of this SoC,
set the CPU frequency to CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC,
and riscv_machine_timer divide the clock with the value of
CONFIG_RISCV_MACHINE_TIMER_SYSTEM_CLOCK_DIVIDER.

The CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC should set the timer's clock,
so I fixed to set the config as 27MHz in this PR.  Also, remove the
unnecessary CONFIG_RISCV_MACHINE_TIMER_SYSTEM_CLOCK_DIVIDER setting.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
2023-06-05 07:08:02 -04:00
Marc Herbert
d98a7c2f8d soc: xtensa: cmake: add new WEST_SIGN_OPTS variable
This allows per-board rimage customization.

Signed-off-by: Marc Herbert <marc.herbert@intel.com>
2023-06-02 15:07:59 -04:00
Marek Matej
02d157b8db soc: esp32: Update soc startup and cache init
Updated the cache init functions
and clean-up the soc startup function.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2023-06-01 10:05:20 +02:00
Marek Matej
548e8b717d soc: esp32: Fix linker scripts
Updated the flash segment alignment on S3,
so that mapping corresponds with the linkage.
Fixed hard-coded flash size for ESP32.

Signed-off-by: Marek Matej <marek.matej@espressif.com>
2023-06-01 10:05:20 +02:00