Update RT5xx and RT6xx clock init to add the code
to set the I3C dividers. This code has been moved
from the I3C driver.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Renamed soc from ace30_ptl to ace30.
We were previously using the wrong soc name.
The correct name is ace30.
There is only one ptl platform, but there can be several ace30 platforms.
Signed-off-by: Grzegorz Bernat <grzegorzx.bernat@intel.com>
No functional changes were made in this update.
Only code formatting issues were corrected.
This commit is necessary to preserve Git history
continuity for future changes involving the switch from ace30_ptl to ace30.
Signed-off-by: Grzegorz Bernat <grzegorzx.bernat@intel.com>
This reverts parts of commit c344771d8b
related to intel_adsp soc.
There is a dependency on device initialization that was missed.
Reverting until we have a proper way for migrating to hooks.
Fixes#78880
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Reverts bus clock settings. Follows MCUXpresso SDK clock settings, and
sets to output of SysPLL2 PFD3 at 198 MHz.
Signed-off-by: Derek Snell <derek.snell@nxp.com>
These static functions in the `pma.c` are used only when
`CONFIG_NOCACHE_MEMORY` is enabled, so guard them accordingly.
Signed-off-by: Yong Cong Sin <ycsin@meta.com>
Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
Provide symbols for the creation of dynamic memory pool.
Update the ROM-code SRAM usage according the IDF main.
Fix static allocations size check.
Increase iram_seg memory size for MCUboot.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Provide symbols for the creation of dynamic memory pool.
Fix the loader ROM buffers start address.
Fix static allocation size check.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Add the `CONFIG_ESP_RUNTIME_HEAP` kconfig.
This allows the memory pool to be created starting
at `z_mapped_end` ending at `_heap_sentry`.
Added choice symbol ESP_WIFI_HEAP_* to select which
heap to use in the ESP WiFi adapter module.
Add file heap.c with code to initialize the runtime heap.
Size of the pool is checked during the runtime.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
This lets the SoC to select the correct kconfigs to show that
it supports coredump, and with the ability to dump privilege
stack.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Currently the RAM allocated for the bootloader is not
enough to use MCUBoot with crypto signatures.
This commit bumps the #defines accordingly to fix
compile errors with ecdsa_p256 and RSA.
Signed-off-by: Brandon Allen <brandon.allen@exacttechnology.com>
Devicetree should be used instead. Example DT snippets are provided to
ease with the transition.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Update CONFIG_ESP_SIMPLE_BOOT to exclude if CONFIG_MCUBOOT=y
Fix usage of the config according to actual definition.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Timer/PWM Module (TPM) initial clock source is not selected.
Add initial clock source selection based on Devicetree configuration.
Rename clock sources definitions from LPUART specific to general names
usable by several modules on the SoC.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
