For Intel cavs2.5, access from LPGPDMAC to Audio Link Hub
RX/TX registers needs to be explicitly enabled before use.
The logic follow hardware initialization done in
SOF project sof/src/platform/intel/cavs/platform.c
Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com>
1. Add support for the USB Full Speed controller
2. Add a Kconfig to specify if a dedicated USB
RAM is available in the SoC.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Add FLEXSPI1 and FLEXSPI2 memory sections for RT5xx SOC. These sections
can be used by the user's application as part of a custom linker script,
if the application needs to relocate a buffer to external SRAM connected
to FLEXSPI1 or FLEXSPI2
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Adds watchdog reset as a reset source at SoC init. This is achieved by:
1. Writing 0x2 to the RESET_EN bitfield register to indicate watchdog
reset is enabled.
2. Writing 0x1 to the CFG_CDC_SYNC register to commit the change.
3. Polling the CFG_CDC_SYNC register until reading 0 to confirm the
change has been processed.
This patch is part of the OpenTitan watchdog (AON Timer) support patch
series. It is needed to ensure that the watchdog reset functionality
is enabled. Note that the timer itself is not enabled here, only the
reset function.
Signed-off-by: Tyler Ng <tkng@rivosinc.com>
1. Fixes the number of interrupts in OpenTitan by default. This should
be 32 + 185 = 217 IRQs, as there are 185 configurable registers,
including interrupt 0.
2. Adds 2ND_LVL_INTR_00_OFFSET Kconfig, which is needed to generate a
PLIC interrupt on IRQ 11.
Signed-off-by: Tyler Ng <tkng@rivosinc.com>
The SoCs/Boards using those headers were dropped, so remove those
remaining headers that were forgotten.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
This commits selects the `CONFIG_SOC_GECKO_SE` option for the BG27 SoC
series. This is required for BLE support, as it enables the inclusion of
the `sl_protocol_crypto` component from SiLabs HAL.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Internal bootloader will only run application image if valid product
header is present on flash. This means product header is required for
application that are not linked to code partition. Other applications
that are linked to code partition are meant to be run by MCUboot and
should not touch product header, with the exception of MCUboot itself
which is also run by internal bootloader so requires product header.
Default flash load offset for applications not linked to code partition
is set to 0x2400 as this is where internal bootloader looks for an
application image to run based on product header written by flasher.
Flash load offset for MCUboot is set from boot partition.
Valid product header is added by ezFlashCLI when using "flash_image"
command.
Co-authored-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Niek Ilmer <niek.ilmer.aj@renesas.com>
Applications that are run from MCUboot should reconfigure cache to
ensure they run from cached ared on flash. Initial cache configuration
is done by internal bootloader and is valid for MCUboot only.
Cache is configured once at boot, then new configuration is applied by
triggering SW reset.
Co-authored-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Niek Ilmer <niek.ilmer.aj@renesas.com>
Flash address is updated to 0x16000000, i.e. actual location instead of
remapped one. FLASH_BASE_ADDRESS is now set via dts.
Co-authored-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Andrzej Kaczmarek <andrzej.kaczmarek@codecoup.pl>
Signed-off-by: Niek Ilmer <niek.ilmer.aj@renesas.com>
Initialize threadptr with 0 during the boot before it possibly be used
since the architectural reset state is undefined.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
This make MCUboot build as Zephyr application.
Providing optinal 2nd stage bootloader to the
IDF bootloader, which is used by default.
This provides more flexibility when building
and loading multiple images and aims to
brings better DX to users by using the sysbuild.
MCUboot and applications has now separate
linker scripts.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
sl_power_manager can only be used if HAL services infrastructure
is enabled, and that is controlled by SOC_GECKO_DEV_INIT kconfig option.
Therefore, SOC_GECKO_PM_BACKEND_PMGR may not be enabled without
SOC_GECKO_DEV_INIT.
Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
Using EM2 or deeper sleep states (where HF clocks are off) requires
special care if BLE radio is used, since BLE radio relies on that clock,
and its power/clock requirements need to be taken into account
On SiLabs, radio PM is implemented as part of RAIL blob, which relies
on sl_power_manager HAL service. I've implemented SoC PM
state changes using sl_power_manager instead of emlib, and added
call to RAIL PM initialization in Gecko HCI driver.
Signed-off-by: Roman Dobrodii <rdobrodii@antmicro.com>
This patch modifies intel_adsp_ipc_is_complete function so it don't
report that IPC is completed when we are still waiting for ACK from
HOST.
This change will allow to solve the problem that occurs during the power
state transitions. Occasionally, the Application decides to enter the
power gating state after sending an IPC message, before receiving an ACK
from the HOST. This results in broken IPC communication when coming back
to Idle state.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
Driver was based on can_sam. SAMC21 has only 1 interrupt for one
can "output", so can interrupt has to executes two lines of
interrupts.
CAN is configured to use OSC48M clock via GLCK7. GLCK7 is set
by divider configured from dts.
Signed-off-by: Kamil Serwus <kserwus@gmail.com>
This patch enables the PLL clock output and PLL ref clock
for second ethernet module in NXP's i.MxRT106x SoCs
Signed-off-by: Sumit Batra <sumit.batra@nxp.com>
Thanks to PR [1] which introduces support for cache management
operations on xtensa architecture NXP SoCs can now use the
Zephyr native cache management API.
This commit enables some configurations that will allow us
to use the native Zephyr cache management API.
[1]: https://github.com/zephyrproject-rtos/zephyr/pull/50136
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
To reduce the interrupt latency of MIWU events, the driver prepares a
dedicated callback function item list for each MIWU group in this PR. We
needn't check the MIWU table and group of the event in ISR. And the
maximum item number of each list is also limited to 8. After applying
this PR, the interrupt latency reduces to ~10us consistently.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
The end of the heap should be the same as _heap_sentry. The current end
marker just covers the range of memory that is explicitly put in
.heap_memand not account until the end of L2_SRAM_BASE +
L2_SRAM_SIZE memory.
Signed-off-by: Flavio Ceolin <flavio.ceolin@intel.com>
Glitches were observed if a GPIO pin was configured by
ROM to a non-default state and then Zephyr PINCTRL
reconfigured the pin. The fix involves using the correct
PINCTRL YAML output enable and state flags. Reading the
current spin state and reflecting into new pin configuration
if the pin is output and the drive low/high properties are
not present. We also take advantage of GPIO hardware reflecing
the alternate output value in the parallel output bit before
enabling parallel output mode. Interpret boolean flags with
both enable and disable as do not touch if neither flag is
present. We give precedence to enable over disable if both
flags mistakenly appear. Note, PINCTRL always clears the
GPIO control input pad disable bit.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
1. Enable os_timer as a wakeup-source in the board
dts file.
2. Enable PM_DEVICE when PM is enabled.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
The macro HW_STATE_CHECK_DELAY represents the number of usec to
busy-wait when waiting for a h/w register state change. This value
has been lowered by 75% to correct a couple of issues related
to Power Management (PM).
1. This resolves a kernel.timer.tickless test failure (see
tests/kernel/timer/timer_api) on the LNL simulator where the test
was taking too long to wake after sleeping for 50 ticks. This
was tracked down to the xtensa SOC power management code where
it was performing a busy wait of 256 usec, which was equivalent
to 2.56 ticks.
2. Furthermore, this delay of 256 usec contradicted the information
in the DTSI (see power-states for d0i3) which states that the
"exit-latency-us" is 100 usec. Reducing this value to 64 helps to
keep that in line.
Signed-off-by: Peter Mitsis <peter.mitsis@intel.com>
This aligns `soc/xtensa/nxp_adsp/` with commit
fad2da39aa ("intel_adsp: move `west sign` from `west flash` to earlier
`west build`")
The --if-tool-available option preserves backwards-compatibility:
nothing happens if rimage is not found.
Signed-off-by: Marc Herbert <marc.herbert@intel.com>
Update the SOC_TOOLCHAIN_NAME to intel_ace15_mtpm so that
we use the correct overlay in Xtensa HAL module. Note that
ace20_lnl will also be using this as well. That will change
once we have a proper toolchain for ace20_lnl.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The ACE 2.0 LNL platform has 5 HIFI4 cores. Change number
of cores to enable 5th core on the platform.
Signed-off-by: Jaroslaw Stelter <Jaroslaw.Stelter@intel.com>
Added logging declaration to soc.c of stm32wl, which resolves build
errors when using this SOC with DEBUG logging level
Fixes: #57655
Signed-off-by: Oliver King <oliver.king@steadconnect.com>
(resubmitting after it has been reverted by 0f2a352cbd ('Revert
"xtensa: remove ELF section address rewriting"')
Now rimage can handle both cached and uncached addresses correctly,
ELF rewriting isn't needed any more.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
board:
- update device tree to use flexcomm devices to the chip design
- enable clocks (soc init file)
- setup connections for loopback test in system controller (board init
file)
tests:
- update board files (overlay, conf)
Signed-off-by: Yves Vandervennet <yves.vandervennet@nxp.com>
Update MCUX ELCDIF driver to use new LCDIF bindings. This
update also adds support for configuring the root clock of
the ELCDIF module based on the pixel-clock property to the
RT11xx SOC clock init, as this SOC series has this IP block
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Update DCNANO LCDIF IP to use shared lcd interface binding. This
requires changes to the RT5xx SOC and RT595 EVK, as this SOC
uses the LCDIF IP, and configures the clock for it based off
the new pixel-clock property.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
Introduce phy-clock property, which is used by MIPI devices to determine
the target clock frequency for the MIPI PHY. This property can vary
depending on the attached display and target framerate.
Update the MIPI DSI MCUX driver to utilize this property to configure
the MIPI host, and update the RT500 clock initialization to configure
the MIPI root clock based on this property.
Remove dphy-clk-div property from the MIPI DSI 2L binding, as it
is redundant with this change.
Signed-off-by: Daniel DeGrasse <daniel.degrasse@nxp.com>
The Mi-V implements the A extension therefore it shouldn't use the C
version. The built-in version generates code with proper machine
opcodes.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Enable UART on the DSP from the i.MX8MP target:
- add corresponding nodes in dtsi and dts;
- create a dts overlay for uart;
- add a config fragment for uart and console configuration.
So, in order to compile an application and enable UART
a user must run west build using DTC_OVERLAY_FILE and CONF_FILE.
Here's an example for hello_world:
west build -p always -b nxp_adsp_imx8m samples/hello_world/
-DDTC_OVERLAY_FILE="boards/xtensa/nxp_adsp_imx8m/
nxp_adsp_imx8m_uart.overlay" -DCONF_FILE="boards/xtensa/nxp_adsp_imx8m/
nxp_adsp_imx8m_uart.conf"
For other applications, like SOF, where we don't need UART, we simply run:
west build -p always -b nxp_adsp_imx8m ../modules/audio/sof/ --
-DTOOLCHAIN=/opt/zephyr-sdk-0.15.2/xtensa-nxp_imx8m_adsp_zephyr-elf/
bin/xtensa-nxp_imx8m_adsp_zephyr-elf -DINIT_CONFIG=imx8m_defconfig
The nxp_adsp_imx8m is using the nxp_imx_iuart driver.
For now, is used in poll mode.
Next step is to enable the interrupt controller in
DSP and use the interrupt driver UART.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
Rename soc to mimx8ml8 to link this board to the
MIMX8ML8 device from nxp_hal/mcux/mcux-sdk/.
We need this in order to use the drivers from mcux-sdk.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
