soc/mediatek/adsp: Source timer rate from DTS

These devices have an architecturally fixed 13 MHz clock device.  But
thankfully you can put a default into a DTS binding so we don't have
to repeat it for all of them.

Signed-off-by: Andy Ross <andyross@google.com>
This commit is contained in:
Andy Ross 2024-11-26 17:57:30 -08:00 committed by Benjamin Cabé
commit b4fb833eb9
2 changed files with 16 additions and 1 deletions

View file

@ -0,0 +1,15 @@
# Copyright 2024 The ChromiumOS Authors
# SPDX-License-Identifier: Apache-2.0
include: base.yaml
# This clock hardware is almost fully described by its register block,
# but needs a binding for the frequency property below (which is
# architecturally fixed at 13 MHz on all known devices)
description: MediaTek Audio DSP Core Clock
compatible: "mediatek,ostimer64"
properties:
freq-hz:
type: int
default: 13000000

View file

@ -37,7 +37,7 @@ config XTENSA_TIMER
default n
config SYS_CLOCK_HW_CYCLES_PER_SEC
default 13000000
default $(dt_node_int_prop_int,$(dt_nodelabel_path,ostimer64),freq-hz)
config MAIN_STACK_SIZE
default 2048