soc: nordic: Introduce the nRF54L05 and nRF54L10
These two new ICs are variants of the nRF54L15 with different memory sizes: - nRF54L05: 500KB RRAM, 96KB RAM - nRF54L10: 1022KB RRAM, 192KB RAM - nRF54L15: 1524KB RRAM, 256KB RAM Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
This commit is contained in:
parent
0b3a15016b
commit
e78832034f
35 changed files with 8563 additions and 941 deletions
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@ -31,7 +31,7 @@ static const uint8_t saadc_psels[NRF_SAADC_AIN7 + 1] = {
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[NRF_SAADC_AIN6] = NRF_PIN_PORT_TO_PIN_NUMBER(6U, 1),
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[NRF_SAADC_AIN7] = NRF_PIN_PORT_TO_PIN_NUMBER(7U, 1),
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};
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#elif defined(CONFIG_SOC_NRF54L15)
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#elif defined(CONFIG_SOC_NRF54L05) || defined(CONFIG_SOC_NRF54L10) || defined(CONFIG_SOC_NRF54L15)
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static const uint32_t saadc_psels[NRF_SAADC_DVDD + 1] = {
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[NRF_SAADC_AIN0] = NRF_PIN_PORT_TO_PIN_NUMBER(4U, 1),
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[NRF_SAADC_AIN1] = NRF_PIN_PORT_TO_PIN_NUMBER(5U, 1),
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@ -667,7 +667,7 @@ static const struct adc_driver_api adc_nrfx_driver_api = {
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#ifdef CONFIG_ADC_ASYNC
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.read_async = adc_nrfx_read_async,
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#endif
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#if defined(CONFIG_SOC_NRF54L15)
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#if defined(CONFIG_SOC_NRF54L05) || defined(CONFIG_SOC_NRF54L10) || defined(CONFIG_SOC_NRF54L15)
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.ref_internal = 900,
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#elif defined(CONFIG_NRF_PLATFORM_HALTIUM)
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.ref_internal = 1024,
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@ -78,7 +78,7 @@ static const uint32_t shim_nrf_comp_ain_map[] = {
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NRF_PIN_PORT_TO_PIN_NUMBER(5U, 1),
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NRF_PIN_PORT_TO_PIN_NUMBER(6U, 1),
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NRF_PIN_PORT_TO_PIN_NUMBER(7U, 1),
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#elif defined(CONFIG_SOC_NRF54L15)
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#elif defined(CONFIG_SOC_NRF54L05) || defined(CONFIG_SOC_NRF54L10) || defined(CONFIG_SOC_NRF54L15)
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NRF_PIN_PORT_TO_PIN_NUMBER(4U, 1),
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NRF_PIN_PORT_TO_PIN_NUMBER(5U, 1),
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NRF_PIN_PORT_TO_PIN_NUMBER(6U, 1),
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@ -49,7 +49,7 @@ static const uint32_t shim_nrf_lpcomp_ain_map[] = {
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NRF_PIN_PORT_TO_PIN_NUMBER(5U, 1),
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NRF_PIN_PORT_TO_PIN_NUMBER(6U, 1),
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NRF_PIN_PORT_TO_PIN_NUMBER(7U, 1),
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#elif defined(CONFIG_SOC_NRF54L15)
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#elif defined(CONFIG_SOC_NRF54L05) || defined(CONFIG_SOC_NRF54L10) || defined(CONFIG_SOC_NRF54L15)
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NRF_PIN_PORT_TO_PIN_NUMBER(4U, 1),
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NRF_PIN_PORT_TO_PIN_NUMBER(5U, 1),
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NRF_PIN_PORT_TO_PIN_NUMBER(6U, 1),
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@ -14,7 +14,7 @@
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#include <zephyr/toolchain.h>
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#include <hal/nrf_vpr.h>
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#if defined(CONFIG_SOC_NRF54L15_CPUAPP) && !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE)
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#if defined(CONFIG_SOC_NRF54L_CPUAPP_COMMON) && !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE)
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#include <hal/nrf_spu.h>
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#endif
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@ -41,7 +41,7 @@ static int nordic_vpr_launcher_init(const struct device *dev)
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}
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#endif
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#if defined(CONFIG_SOC_NRF54L15_CPUAPP) && !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE)
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#if defined(CONFIG_SOC_NRF54L_CPUAPP_COMMON) && !defined(CONFIG_TRUSTED_EXECUTION_NONSECURE)
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nrf_spu_periph_perm_secattr_set(NRF_SPU00, nrf_address_slave_get((uint32_t)config->vpr),
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true);
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#endif
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8
dts/arm/nordic/nrf54l05_cpuapp.dtsi
Normal file
8
dts/arm/nordic/nrf54l05_cpuapp.dtsi
Normal file
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@ -0,0 +1,8 @@
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/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <nordic/nrf54l05.dtsi>
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#include "nrf54l_05_10_15_cpuapp.dtsi"
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8
dts/arm/nordic/nrf54l10_cpuapp.dtsi
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8
dts/arm/nordic/nrf54l10_cpuapp.dtsi
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@ -0,0 +1,8 @@
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/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <nordic/nrf54l10.dtsi>
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#include "nrf54l_05_10_15_cpuapp.dtsi"
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@ -5,84 +5,4 @@
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*/
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#include <nordic/nrf54l15.dtsi>
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cpu: &cpuapp {};
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systick: &cpuapp_systick {};
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nvic: &cpuapp_nvic {};
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/delete-node/ &cpuflpr;
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/delete-node/ &cpuflpr_rram;
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/delete-node/ &cpuflpr_sram;
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/delete-node/ &cpuflpr_clic;
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/ {
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chosen {
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zephyr,bt-hci = &bt_hci_controller;
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&cpuapp_nvic>;
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ranges;
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};
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psa_rng: psa-rng {
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compatible = "zephyr,psa-crypto-rng";
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status = "disabled";
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};
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};
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&bt_hci_controller {
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status = "okay";
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};
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&cpuflpr_vpr {
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cpuapp_vevif_rx: mailbox@1 {
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compatible = "nordic,nrf-vevif-event-rx";
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reg = <0x0 0x1000>;
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status = "disabled";
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interrupts = <76 NRF_DEFAULT_IRQ_PRIORITY>;
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#mbox-cells = <1>;
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nordic,events = <1>;
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nordic,events-mask = <0x00100000>;
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};
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cpuapp_vevif_tx: mailbox@0 {
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compatible = "nordic,nrf-vevif-task-tx";
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reg = <0x0 0x1000>;
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#mbox-cells = <1>;
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nordic,tasks = <7>;
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nordic,tasks-mask = <0x007f0000>;
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status = "disabled";
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};
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};
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&cpuapp_ppb {
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compatible = "simple-bus";
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ranges;
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};
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&grtc {
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#ifdef USE_NON_SECURE_ADDRESS_MAP
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interrupts = <227 NRF_DEFAULT_IRQ_PRIORITY>,
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#else
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interrupts = <228 NRF_DEFAULT_IRQ_PRIORITY>,
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#endif
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<229 NRF_DEFAULT_IRQ_PRIORITY>; /* reserved for Zero Latency IRQs */
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};
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&gpiote20 {
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#ifdef USE_NON_SECURE_ADDRESS_MAP
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interrupts = <218 NRF_DEFAULT_IRQ_PRIORITY>;
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#else
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interrupts = <219 NRF_DEFAULT_IRQ_PRIORITY>;
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#endif
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};
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&gpiote30 {
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#ifdef USE_NON_SECURE_ADDRESS_MAP
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interrupts = <268 NRF_DEFAULT_IRQ_PRIORITY>;
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#else
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interrupts = <269 NRF_DEFAULT_IRQ_PRIORITY>;
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#endif
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};
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#include "nrf54l_05_10_15_cpuapp.dtsi"
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86
dts/arm/nordic/nrf54l_05_10_15_cpuapp.dtsi
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86
dts/arm/nordic/nrf54l_05_10_15_cpuapp.dtsi
Normal file
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@ -0,0 +1,86 @@
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/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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cpu: &cpuapp {};
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systick: &cpuapp_systick {};
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nvic: &cpuapp_nvic {};
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/delete-node/ &cpuflpr;
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/delete-node/ &cpuflpr_rram;
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/delete-node/ &cpuflpr_sram;
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/delete-node/ &cpuflpr_clic;
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/ {
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chosen {
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zephyr,bt-hci = &bt_hci_controller;
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};
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soc {
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compatible = "simple-bus";
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interrupt-parent = <&cpuapp_nvic>;
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ranges;
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};
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psa_rng: psa-rng {
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compatible = "zephyr,psa-crypto-rng";
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status = "disabled";
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};
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};
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&bt_hci_controller {
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status = "okay";
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};
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&cpuflpr_vpr {
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cpuapp_vevif_rx: mailbox@1 {
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compatible = "nordic,nrf-vevif-event-rx";
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reg = <0x0 0x1000>;
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status = "disabled";
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interrupts = <76 NRF_DEFAULT_IRQ_PRIORITY>;
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#mbox-cells = <1>;
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nordic,events = <1>;
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nordic,events-mask = <0x00100000>;
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};
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cpuapp_vevif_tx: mailbox@0 {
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compatible = "nordic,nrf-vevif-task-tx";
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reg = <0x0 0x1000>;
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#mbox-cells = <1>;
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nordic,tasks = <7>;
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nordic,tasks-mask = <0x007f0000>;
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status = "disabled";
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};
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};
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&cpuapp_ppb {
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compatible = "simple-bus";
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ranges;
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};
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&grtc {
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#ifdef USE_NON_SECURE_ADDRESS_MAP
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interrupts = <227 NRF_DEFAULT_IRQ_PRIORITY>,
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#else
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interrupts = <228 NRF_DEFAULT_IRQ_PRIORITY>,
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#endif
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<229 NRF_DEFAULT_IRQ_PRIORITY>; /* reserved for Zero Latency IRQs */
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};
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&gpiote20 {
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#ifdef USE_NON_SECURE_ADDRESS_MAP
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interrupts = <218 NRF_DEFAULT_IRQ_PRIORITY>;
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#else
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interrupts = <219 NRF_DEFAULT_IRQ_PRIORITY>;
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#endif
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};
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&gpiote30 {
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#ifdef USE_NON_SECURE_ADDRESS_MAP
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interrupts = <268 NRF_DEFAULT_IRQ_PRIORITY>;
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#else
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interrupts = <269 NRF_DEFAULT_IRQ_PRIORITY>;
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#endif
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};
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39
dts/common/nordic/nrf54l05.dtsi
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39
dts/common/nordic/nrf54l05.dtsi
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@ -0,0 +1,39 @@
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/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "nrf54l_05_10_15.dtsi"
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&cpuapp_sram {
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reg = <0x20000000 DT_SIZE_K(72)>;
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ranges = <0x0 0x20000000 DT_SIZE_K(72)>;
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};
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/* 72 + 24 = 96KB */
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/ {
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soc {
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cpuflpr_sram: memory@20012000 {
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compatible = "mmio-sram";
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reg = <0x20012000 DT_SIZE_K(24)>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x20012000 DT_SIZE_K(24)>;
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};
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};
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};
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&cpuapp_rram {
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reg = <0x0 DT_SIZE_K(470)>;
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};
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/* 470 + 30 = 500KB */
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&rram_controller {
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cpuflpr_rram: rram@75800 {
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compatible = "soc-nv-flash";
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reg = <0x75800 DT_SIZE_K(30)>;
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erase-block-size = <4096>;
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write-block-size = <16>;
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};
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};
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39
dts/common/nordic/nrf54l10.dtsi
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39
dts/common/nordic/nrf54l10.dtsi
Normal file
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@ -0,0 +1,39 @@
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/*
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* Copyright (c) 2024 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "nrf54l_05_10_15.dtsi"
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&cpuapp_sram {
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reg = <0x20000000 DT_SIZE_K(144)>;
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ranges = <0x0 0x20000000 DT_SIZE_K(144)>;
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};
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/* 144 + 48 = 192KB */
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/ {
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soc {
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cpuflpr_sram: memory@20024000 {
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compatible = "mmio-sram";
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reg = <0x20024000 DT_SIZE_K(48)>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x20024000 DT_SIZE_K(48)>;
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};
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};
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};
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&cpuapp_rram {
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reg = <0x0 DT_SIZE_K(960)>;
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};
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/* 960 + 62 = 1022KB */
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&rram_controller {
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cpuflpr_rram: rram@f0000 {
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compatible = "soc-nv-flash";
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reg = <0xf0000 DT_SIZE_K(62)>;
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erase-block-size = <4096>;
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write-block-size = <16>;
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};
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};
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@ -4,748 +4,36 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <nordic/nrf_common.dtsi>
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#include <zephyr/dt-bindings/adc/nrf-saadc-nrf54l.h>
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#include <zephyr/dt-bindings/regulator/nrf5x.h>
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#include "nrf54l_05_10_15.dtsi"
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/delete-node/ &sw_pwm;
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/* Domain IDs. Can be used to specify channel links in IPCT nodes. */
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#define NRF_DOMAIN_ID_APPLICATION 0
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#define NRF_DOMAIN_ID_FLPR 1
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&cpuapp_sram {
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reg = <0x20000000 DT_SIZE_K(188)>;
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ranges = <0x0 0x20000000 DT_SIZE_K(188)>;
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};
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/* 188 + 68 = 256KB */
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpuapp: cpu@0 {
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compatible = "arm,cortex-m33f";
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reg = <0>;
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device_type = "cpu";
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clock-frequency = <DT_FREQ_M(128)>;
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#address-cells = <1>;
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#size-cells = <1>;
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itm: itm@e0000000 {
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compatible = "arm,armv8m-itm";
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reg = <0xe0000000 0x1000>;
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swo-ref-frequency = <DT_FREQ_M(128)>;
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};
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};
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cpuflpr: cpu@1 {
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compatible = "nordic,vpr";
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reg = <1>;
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device_type = "cpu";
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clock-frequency = <DT_FREQ_M(128)>;
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riscv,isa = "rv32emc";
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nordic,bus-width = <32>;
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};
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};
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clocks {
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lfxo: lfxo {
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compatible = "nordic,nrf-lfxo";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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};
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hfxo: hfxo {
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compatible = "nordic,nrf-hfxo";
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#clock-cells = <0>;
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clock-frequency = <DT_FREQ_M(32)>;
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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#ifdef USE_NON_SECURE_ADDRESS_MAP
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/* intentionally empty because UICR is hardware fixed to Secure */
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#else
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uicr: uicr@ffd000 {
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compatible = "nordic,nrf-uicr";
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reg = <0xffd000 0x1000>;
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};
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#endif
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ficr: ficr@ffc000 {
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compatible = "nordic,nrf-ficr";
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reg = <0xffc000 0x1000>;
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#nordic,ficr-cells = <1>;
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};
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cpuapp_sram: memory@20000000 {
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compatible = "mmio-sram";
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reg = <0x20000000 DT_SIZE_K(188)>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x20000000 0x2f000>;
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};
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cpuflpr_sram: memory@2002f000 {
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compatible = "mmio-sram";
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reg = <0x2002f000 DT_SIZE_K(68)>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x2002f000 0x11000>;
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};
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#ifdef USE_NON_SECURE_ADDRESS_MAP
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global_peripherals: peripheral@40000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x40000000 0x10000000>;
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#else
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global_peripherals: peripheral@50000000 {
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#address-cells = <1>;
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#size-cells = <1>;
|
||||
ranges = <0x0 0x50000000 0x10000000>;
|
||||
#endif
|
||||
|
||||
dppic00: dppic@42000 {
|
||||
compatible = "nordic,nrf-dppic";
|
||||
reg = <0x42000 0x808>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ppib00: ppib@43000 {
|
||||
compatible = "nordic,nrf-ppib";
|
||||
reg = <0x43000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ppib01: ppib@44000 {
|
||||
compatible = "nordic,nrf-ppib";
|
||||
reg = <0x44000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi00: spi@4a000 {
|
||||
/*
|
||||
* This spi node can be either SPIM or SPIS,
|
||||
* for the user to pick:
|
||||
* compatible = "nordic,nrf-spim" or
|
||||
* "nordic,nrf-spis".
|
||||
*/
|
||||
compatible = "nordic,nrf-spim";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x4a000 0x1000>;
|
||||
interrupts = <74 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
max-frequency = <DT_FREQ_M(32)>;
|
||||
easydma-maxcnt-bits = <16>;
|
||||
rx-delay-supported;
|
||||
rx-delay = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart00: uart@4a000 {
|
||||
compatible = "nordic,nrf-uarte";
|
||||
reg = <0x4a000 0x1000>;
|
||||
interrupts = <74 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
endtx-stoptx-supported;
|
||||
frame-timeout-supported;
|
||||
};
|
||||
|
||||
cpuflpr_vpr: vpr@4c000 {
|
||||
compatible = "nordic,nrf-vpr-coprocessor";
|
||||
reg = <0x4c000 0x1000>;
|
||||
ranges = <0x0 0x4c000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
status = "disabled";
|
||||
|
||||
cpuflpr_clic: interrupt-controller@f0000000 {
|
||||
compatible = "nordic,nrf-clic";
|
||||
reg = <0xf0000000 0x1780>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
#address-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
gpio2: gpio@50400 {
|
||||
compatible = "nordic,nrf-gpio";
|
||||
gpio-controller;
|
||||
reg = <0x50400 0x300>;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <11>;
|
||||
status = "disabled";
|
||||
port = <2>;
|
||||
};
|
||||
|
||||
timer00: timer@55000 {
|
||||
compatible = "nordic,nrf-timer";
|
||||
status = "disabled";
|
||||
reg = <0x55000 0x1000>;
|
||||
cc-num = <6>;
|
||||
max-bit-width = <32>;
|
||||
interrupts = <85 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
max-frequency = <DT_FREQ_M(128)>;
|
||||
prescaler = <0>;
|
||||
};
|
||||
|
||||
dppic10: dppic@82000 {
|
||||
compatible = "nordic,nrf-dppic";
|
||||
reg = <0x82000 0x808>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ppib10: ppib@83000 {
|
||||
compatible = "nordic,nrf-ppib";
|
||||
reg = <0x83000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ppib11: ppib@84000 {
|
||||
compatible = "nordic,nrf-ppib";
|
||||
reg = <0x84000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer10: timer@85000 {
|
||||
compatible = "nordic,nrf-timer";
|
||||
status = "disabled";
|
||||
reg = <0x85000 0x1000>;
|
||||
cc-num = <8>;
|
||||
max-bit-width = <32>;
|
||||
interrupts = <133 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
max-frequency = <DT_FREQ_M(32)>;
|
||||
prescaler = <0>;
|
||||
};
|
||||
|
||||
egu10: egu@87000 {
|
||||
compatible = "nordic,nrf-egu";
|
||||
reg = <0x87000 0x1000>;
|
||||
interrupts = <135 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
radio: radio@8a000 {
|
||||
compatible = "nordic,nrf-radio";
|
||||
reg = <0x8a000 0x1000>;
|
||||
interrupts = <138 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
dfe-supported;
|
||||
ieee802154-supported;
|
||||
ble-2mbps-supported;
|
||||
ble-coded-phy-supported;
|
||||
cs-supported;
|
||||
|
||||
ieee802154: ieee802154 {
|
||||
compatible = "nordic,nrf-ieee802154";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* Note: In the nRF Connect SDK the SoftDevice Controller
|
||||
* is added and set as the default Bluetooth Controller.
|
||||
*/
|
||||
bt_hci_controller: bt_hci_controller {
|
||||
compatible = "zephyr,bt-hci-ll-sw-split";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
dppic20: dppic@c2000 {
|
||||
compatible = "nordic,nrf-dppic";
|
||||
reg = <0xc2000 0x808>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ppib20: ppib@c3000 {
|
||||
compatible = "nordic,nrf-ppib";
|
||||
reg = <0xc3000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ppib21: ppib@c4000 {
|
||||
compatible = "nordic,nrf-ppib";
|
||||
reg = <0xc4000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ppib22: ppib@c5000 {
|
||||
compatible = "nordic,nrf-ppib";
|
||||
reg = <0xc5000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c20: i2c@c6000 {
|
||||
compatible = "nordic,nrf-twim";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xc6000 0x1000>;
|
||||
interrupts = <198 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
easydma-maxcnt-bits = <16>;
|
||||
status = "disabled";
|
||||
zephyr,pm-device-runtime-auto;
|
||||
};
|
||||
|
||||
spi20: spi@c6000 {
|
||||
/*
|
||||
* This spi node can be either SPIM or SPIS,
|
||||
* for the user to pick:
|
||||
* compatible = "nordic,nrf-spim" or
|
||||
* "nordic,nrf-spis".
|
||||
*/
|
||||
compatible = "nordic,nrf-spim";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xc6000 0x1000>;
|
||||
interrupts = <198 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
max-frequency = <DT_FREQ_M(8)>;
|
||||
easydma-maxcnt-bits = <16>;
|
||||
rx-delay-supported;
|
||||
rx-delay = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart20: uart@c6000 {
|
||||
compatible = "nordic,nrf-uarte";
|
||||
reg = <0xc6000 0x1000>;
|
||||
interrupts = <198 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
endtx-stoptx-supported;
|
||||
frame-timeout-supported;
|
||||
};
|
||||
|
||||
i2c21: i2c@c7000 {
|
||||
compatible = "nordic,nrf-twim";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xc7000 0x1000>;
|
||||
interrupts = <199 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
easydma-maxcnt-bits = <16>;
|
||||
status = "disabled";
|
||||
zephyr,pm-device-runtime-auto;
|
||||
};
|
||||
|
||||
spi21: spi@c7000 {
|
||||
/*
|
||||
* This spi node can be either SPIM or SPIS,
|
||||
* for the user to pick:
|
||||
* compatible = "nordic,nrf-spim" or
|
||||
* "nordic,nrf-spis".
|
||||
*/
|
||||
compatible = "nordic,nrf-spim";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xc7000 0x1000>;
|
||||
interrupts = <199 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
max-frequency = <DT_FREQ_M(8)>;
|
||||
easydma-maxcnt-bits = <16>;
|
||||
rx-delay-supported;
|
||||
rx-delay = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart21: uart@c7000 {
|
||||
compatible = "nordic,nrf-uarte";
|
||||
reg = <0xc7000 0x1000>;
|
||||
interrupts = <199 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
endtx-stoptx-supported;
|
||||
frame-timeout-supported;
|
||||
};
|
||||
|
||||
i2c22: i2c@c8000 {
|
||||
compatible = "nordic,nrf-twim";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xc8000 0x1000>;
|
||||
interrupts = <200 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
easydma-maxcnt-bits = <16>;
|
||||
status = "disabled";
|
||||
zephyr,pm-device-runtime-auto;
|
||||
};
|
||||
|
||||
spi22: spi@c8000 {
|
||||
/*
|
||||
* This spi node can be either SPIM or SPIS,
|
||||
* for the user to pick:
|
||||
* compatible = "nordic,nrf-spim" or
|
||||
* "nordic,nrf-spis".
|
||||
*/
|
||||
compatible = "nordic,nrf-spim";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xc8000 0x1000>;
|
||||
interrupts = <200 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
max-frequency = <DT_FREQ_M(8)>;
|
||||
easydma-maxcnt-bits = <16>;
|
||||
rx-delay-supported;
|
||||
rx-delay = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart22: uart@c8000 {
|
||||
compatible = "nordic,nrf-uarte";
|
||||
reg = <0xc8000 0x1000>;
|
||||
interrupts = <200 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
endtx-stoptx-supported;
|
||||
frame-timeout-supported;
|
||||
};
|
||||
|
||||
egu20: egu@c9000 {
|
||||
compatible = "nordic,nrf-egu";
|
||||
reg = <0xc9000 0x1000>;
|
||||
interrupts = <201 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer20: timer@ca000 {
|
||||
compatible = "nordic,nrf-timer";
|
||||
status = "disabled";
|
||||
reg = <0xca000 0x1000>;
|
||||
cc-num = <6>;
|
||||
max-bit-width = <32>;
|
||||
interrupts = <202 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
prescaler = <0>;
|
||||
};
|
||||
|
||||
timer21: timer@cb000 {
|
||||
compatible = "nordic,nrf-timer";
|
||||
status = "disabled";
|
||||
reg = <0xcb000 0x1000>;
|
||||
cc-num = <6>;
|
||||
max-bit-width = <32>;
|
||||
interrupts = <203 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
prescaler = <0>;
|
||||
};
|
||||
|
||||
timer22: timer@cc000 {
|
||||
compatible = "nordic,nrf-timer";
|
||||
status = "disabled";
|
||||
reg = <0xcc000 0x1000>;
|
||||
cc-num = <6>;
|
||||
max-bit-width = <32>;
|
||||
interrupts = <204 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
prescaler = <0>;
|
||||
};
|
||||
|
||||
timer23: timer@cd000 {
|
||||
compatible = "nordic,nrf-timer";
|
||||
status = "disabled";
|
||||
reg = <0xcd000 0x1000>;
|
||||
cc-num = <6>;
|
||||
max-bit-width = <32>;
|
||||
interrupts = <205 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
prescaler = <0>;
|
||||
};
|
||||
|
||||
timer24: timer@ce000 {
|
||||
compatible = "nordic,nrf-timer";
|
||||
status = "disabled";
|
||||
reg = <0xce000 0x1000>;
|
||||
cc-num = <6>;
|
||||
max-bit-width = <32>;
|
||||
interrupts = <206 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
prescaler = <0>;
|
||||
};
|
||||
|
||||
pdm20: pdm@d0000 {
|
||||
compatible = "nordic,nrf-pdm";
|
||||
status = "disabled";
|
||||
reg = <0xd0000 0x1000>;
|
||||
interrupts = <208 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
};
|
||||
|
||||
pdm21: pdm@d1000 {
|
||||
compatible = "nordic,nrf-pdm";
|
||||
status = "disabled";
|
||||
reg = <0xd1000 0x1000>;
|
||||
interrupts = <209 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
};
|
||||
|
||||
pwm20: pwm@d2000 {
|
||||
compatible = "nordic,nrf-pwm";
|
||||
status = "disabled";
|
||||
reg = <0xd2000 0x1000>;
|
||||
interrupts = <210 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
pwm21: pwm@d3000 {
|
||||
compatible = "nordic,nrf-pwm";
|
||||
status = "disabled";
|
||||
reg = <0xd3000 0x1000>;
|
||||
interrupts = <211 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
pwm22: pwm@d4000 {
|
||||
compatible = "nordic,nrf-pwm";
|
||||
status = "disabled";
|
||||
reg = <0xd4000 0x1000>;
|
||||
interrupts = <212 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
adc: adc@d5000 {
|
||||
compatible = "nordic,nrf-saadc";
|
||||
reg = <0xd5000 0x1000>;
|
||||
interrupts = <213 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
|
||||
nfct: nfct@d6000 {
|
||||
compatible = "nordic,nrf-nfct";
|
||||
reg = <0xd6000 0x1000>;
|
||||
interrupts = <214 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
temp: temp@d7000 {
|
||||
compatible = "nordic,nrf-temp";
|
||||
reg = <0xd7000 0x1000>;
|
||||
interrupts = <215 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio1: gpio@d8200 {
|
||||
compatible = "nordic,nrf-gpio";
|
||||
gpio-controller;
|
||||
reg = <0xd8200 0x300>;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <16>;
|
||||
status = "disabled";
|
||||
port = <1>;
|
||||
gpiote-instance = <&gpiote20>;
|
||||
};
|
||||
|
||||
gpiote20: gpiote@da000 {
|
||||
compatible = "nordic,nrf-gpiote";
|
||||
reg = <0xda000 0x1000>;
|
||||
status = "disabled";
|
||||
instance = <20>;
|
||||
};
|
||||
|
||||
i2s20: i2s@dd000 {
|
||||
compatible = "nordic,nrf-i2s";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xdd000 0x1000>;
|
||||
interrupts = <221 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qdec20: qdec@e0000 {
|
||||
compatible = "nordic,nrf-qdec";
|
||||
reg = <0xe0000 0x1000>;
|
||||
interrupts = <224 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qdec21: qdec@e1000 {
|
||||
compatible = "nordic,nrf-qdec";
|
||||
reg = <0xe1000 0x1000>;
|
||||
interrupts = <225 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
grtc: grtc@e2000 {
|
||||
compatible = "nordic,nrf-grtc";
|
||||
reg = <0xe2000 0x1000>;
|
||||
cc-num = <12>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dppic30: dppic@102000 {
|
||||
compatible = "nordic,nrf-dppic";
|
||||
reg = <0x102000 0x808>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ppib30: ppib@103000 {
|
||||
compatible = "nordic,nrf-ppib";
|
||||
reg = <0x103000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c30: i2c@104000 {
|
||||
compatible = "nordic,nrf-twim";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x104000 0x1000>;
|
||||
interrupts = <260 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
easydma-maxcnt-bits = <16>;
|
||||
status = "disabled";
|
||||
zephyr,pm-device-runtime-auto;
|
||||
};
|
||||
|
||||
spi30: spi@104000 {
|
||||
/*
|
||||
* This spi node can be either SPIM or SPIS,
|
||||
* for the user to pick:
|
||||
* compatible = "nordic,nrf-spim" or
|
||||
* "nordic,nrf-spis".
|
||||
*/
|
||||
compatible = "nordic,nrf-spim";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x104000 0x1000>;
|
||||
interrupts = <260 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
max-frequency = <DT_FREQ_M(8)>;
|
||||
easydma-maxcnt-bits = <16>;
|
||||
rx-delay-supported;
|
||||
rx-delay = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart30: uart@104000 {
|
||||
compatible = "nordic,nrf-uarte";
|
||||
reg = <0x104000 0x1000>;
|
||||
interrupts = <260 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
endtx-stoptx-supported;
|
||||
frame-timeout-supported;
|
||||
};
|
||||
|
||||
comp: comparator@106000 {
|
||||
/*
|
||||
* Use compatible "nordic,nrf-comp" to configure as COMP
|
||||
* Use compatible "nordic,nrf-lpcomp" to configure as LPCOMP
|
||||
*/
|
||||
compatible = "nordic,nrf-comp";
|
||||
reg = <0x106000 0x1000>;
|
||||
status = "disabled";
|
||||
interrupts = <262 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
};
|
||||
|
||||
#ifdef USE_NON_SECURE_ADDRESS_MAP
|
||||
/* intentionally empty because WDT30 is hardware fixed to Secure */
|
||||
#else
|
||||
wdt30: watchdog@108000 {
|
||||
compatible = "nordic,nrf-wdt";
|
||||
reg = <0x108000 0x620>;
|
||||
interrupts = <264 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
};
|
||||
#endif
|
||||
|
||||
wdt31: watchdog@109000 {
|
||||
compatible = "nordic,nrf-wdt";
|
||||
reg = <0x109000 0x620>;
|
||||
interrupts = <265 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio0: gpio@10a000 {
|
||||
compatible = "nordic,nrf-gpio";
|
||||
gpio-controller;
|
||||
reg = <0x10a000 0x300>;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <5>;
|
||||
status = "disabled";
|
||||
port = <0>;
|
||||
gpiote-instance = <&gpiote30>;
|
||||
};
|
||||
|
||||
gpiote30: gpiote@10c000 {
|
||||
compatible = "nordic,nrf-gpiote";
|
||||
reg = <0x10c000 0x1000>;
|
||||
status = "disabled";
|
||||
instance = <30>;
|
||||
};
|
||||
|
||||
clock: clock@10e000 {
|
||||
compatible = "nordic,nrf-clock";
|
||||
reg = <0x10e000 0x1000>;
|
||||
interrupts = <270 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
power: power@10e000 {
|
||||
compatible = "nordic,nrf-power";
|
||||
reg = <0x10e000 0x1000>;
|
||||
ranges = <0x0 0x10e000 0x1000>;
|
||||
interrupts = <270 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
gpregret1: gpregret1@51c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "nordic,nrf-gpregret";
|
||||
reg = <0x51c 0x1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpregret2: gpregret2@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "nordic,nrf-gpregret";
|
||||
reg = <0x520 0x1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
regulators: regulator@120000 {
|
||||
compatible = "nordic,nrf54l-regulators";
|
||||
reg = <0x120000 0x1000>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
vregmain: regulator@120600 {
|
||||
compatible = "nordic,nrf5x-regulator";
|
||||
reg = <0x120600 0x1>;
|
||||
status = "disabled";
|
||||
regulator-name = "VREGMAIN";
|
||||
regulator-initial-mode = <NRF5X_REG_MODE_LDO>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
rram_controller: rram-controller@5004b000 {
|
||||
compatible = "nordic,rram-controller";
|
||||
reg = <0x5004b000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <75 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
|
||||
cpuapp_rram: rram@0 {
|
||||
compatible = "soc-nv-flash";
|
||||
reg = <0x0 DT_SIZE_K(1428)>;
|
||||
erase-block-size = <4096>;
|
||||
write-block-size = <16>;
|
||||
};
|
||||
cpuflpr_rram: rram@165000 {
|
||||
compatible = "soc-nv-flash";
|
||||
reg = <0x165000 DT_SIZE_K(96)>;
|
||||
erase-block-size = <4096>;
|
||||
write-block-size = <16>;
|
||||
};
|
||||
};
|
||||
|
||||
cpuapp_ppb: cpuapp-ppb-bus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpuapp_nvic: interrupt-controller@e000e100 {
|
||||
#address-cells = <1>;
|
||||
compatible = "arm,v8m-nvic";
|
||||
reg = <0xe000e100 0xc00>;
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
cpuapp_systick: timer@e000e010 {
|
||||
compatible = "arm,armv8m-systick";
|
||||
reg = <0xe000e010 0x10>;
|
||||
status = "disabled";
|
||||
};
|
||||
ranges = <0x0 0x2002f000 DT_SIZE_K(68)>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&cpuapp_rram {
|
||||
reg = <0x0 DT_SIZE_K(1428)>;
|
||||
};
|
||||
|
||||
/* 1428 + 96 = 1524KB */
|
||||
&rram_controller {
|
||||
cpuflpr_rram: rram@165000 {
|
||||
compatible = "soc-nv-flash";
|
||||
reg = <0x165000 DT_SIZE_K(96)>;
|
||||
erase-block-size = <4096>;
|
||||
write-block-size = <16>;
|
||||
};
|
||||
};
|
||||
|
|
734
dts/common/nordic/nrf54l_05_10_15.dtsi
Normal file
734
dts/common/nordic/nrf54l_05_10_15.dtsi
Normal file
|
@ -0,0 +1,734 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Nordic Semiconductor ASA
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <mem.h>
|
||||
#include <nordic/nrf_common.dtsi>
|
||||
#include <zephyr/dt-bindings/adc/nrf-saadc-nrf54l.h>
|
||||
#include <zephyr/dt-bindings/regulator/nrf5x.h>
|
||||
|
||||
/delete-node/ &sw_pwm;
|
||||
|
||||
/* Domain IDs. Can be used to specify channel links in IPCT nodes. */
|
||||
#define NRF_DOMAIN_ID_APPLICATION 0
|
||||
#define NRF_DOMAIN_ID_FLPR 1
|
||||
|
||||
/ {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpuapp: cpu@0 {
|
||||
compatible = "arm,cortex-m33f";
|
||||
reg = <0>;
|
||||
device_type = "cpu";
|
||||
clock-frequency = <DT_FREQ_M(128)>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
itm: itm@e0000000 {
|
||||
compatible = "arm,armv8m-itm";
|
||||
reg = <0xe0000000 0x1000>;
|
||||
swo-ref-frequency = <DT_FREQ_M(128)>;
|
||||
};
|
||||
};
|
||||
|
||||
cpuflpr: cpu@1 {
|
||||
compatible = "nordic,vpr";
|
||||
reg = <1>;
|
||||
device_type = "cpu";
|
||||
clock-frequency = <DT_FREQ_M(128)>;
|
||||
riscv,isa = "rv32emc";
|
||||
nordic,bus-width = <32>;
|
||||
};
|
||||
};
|
||||
|
||||
clocks {
|
||||
lfxo: lfxo {
|
||||
compatible = "nordic,nrf-lfxo";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
hfxo: hfxo {
|
||||
compatible = "nordic,nrf-hfxo";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <DT_FREQ_M(32)>;
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
#ifdef USE_NON_SECURE_ADDRESS_MAP
|
||||
/* intentionally empty because UICR is hardware fixed to Secure */
|
||||
#else
|
||||
uicr: uicr@ffd000 {
|
||||
compatible = "nordic,nrf-uicr";
|
||||
reg = <0xffd000 0x1000>;
|
||||
};
|
||||
#endif
|
||||
ficr: ficr@ffc000 {
|
||||
compatible = "nordic,nrf-ficr";
|
||||
reg = <0xffc000 0x1000>;
|
||||
#nordic,ficr-cells = <1>;
|
||||
};
|
||||
|
||||
cpuapp_sram: memory@20000000 {
|
||||
compatible = "mmio-sram";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
};
|
||||
|
||||
#ifdef USE_NON_SECURE_ADDRESS_MAP
|
||||
global_peripherals: peripheral@40000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x40000000 0x10000000>;
|
||||
#else
|
||||
global_peripherals: peripheral@50000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x50000000 0x10000000>;
|
||||
#endif
|
||||
|
||||
dppic00: dppic@42000 {
|
||||
compatible = "nordic,nrf-dppic";
|
||||
reg = <0x42000 0x808>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ppib00: ppib@43000 {
|
||||
compatible = "nordic,nrf-ppib";
|
||||
reg = <0x43000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ppib01: ppib@44000 {
|
||||
compatible = "nordic,nrf-ppib";
|
||||
reg = <0x44000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
spi00: spi@4a000 {
|
||||
/*
|
||||
* This spi node can be either SPIM or SPIS,
|
||||
* for the user to pick:
|
||||
* compatible = "nordic,nrf-spim" or
|
||||
* "nordic,nrf-spis".
|
||||
*/
|
||||
compatible = "nordic,nrf-spim";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x4a000 0x1000>;
|
||||
interrupts = <74 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
max-frequency = <DT_FREQ_M(32)>;
|
||||
easydma-maxcnt-bits = <16>;
|
||||
rx-delay-supported;
|
||||
rx-delay = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart00: uart@4a000 {
|
||||
compatible = "nordic,nrf-uarte";
|
||||
reg = <0x4a000 0x1000>;
|
||||
interrupts = <74 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
endtx-stoptx-supported;
|
||||
frame-timeout-supported;
|
||||
};
|
||||
|
||||
cpuflpr_vpr: vpr@4c000 {
|
||||
compatible = "nordic,nrf-vpr-coprocessor";
|
||||
reg = <0x4c000 0x1000>;
|
||||
ranges = <0x0 0x4c000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
status = "disabled";
|
||||
|
||||
cpuflpr_clic: interrupt-controller@f0000000 {
|
||||
compatible = "nordic,nrf-clic";
|
||||
reg = <0xf0000000 0x1780>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
#address-cells = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
gpio2: gpio@50400 {
|
||||
compatible = "nordic,nrf-gpio";
|
||||
gpio-controller;
|
||||
reg = <0x50400 0x300>;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <11>;
|
||||
status = "disabled";
|
||||
port = <2>;
|
||||
};
|
||||
|
||||
timer00: timer@55000 {
|
||||
compatible = "nordic,nrf-timer";
|
||||
status = "disabled";
|
||||
reg = <0x55000 0x1000>;
|
||||
cc-num = <6>;
|
||||
max-bit-width = <32>;
|
||||
interrupts = <85 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
max-frequency = <DT_FREQ_M(128)>;
|
||||
prescaler = <0>;
|
||||
};
|
||||
|
||||
dppic10: dppic@82000 {
|
||||
compatible = "nordic,nrf-dppic";
|
||||
reg = <0x82000 0x808>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ppib10: ppib@83000 {
|
||||
compatible = "nordic,nrf-ppib";
|
||||
reg = <0x83000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ppib11: ppib@84000 {
|
||||
compatible = "nordic,nrf-ppib";
|
||||
reg = <0x84000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer10: timer@85000 {
|
||||
compatible = "nordic,nrf-timer";
|
||||
status = "disabled";
|
||||
reg = <0x85000 0x1000>;
|
||||
cc-num = <8>;
|
||||
max-bit-width = <32>;
|
||||
interrupts = <133 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
max-frequency = <DT_FREQ_M(32)>;
|
||||
prescaler = <0>;
|
||||
};
|
||||
|
||||
egu10: egu@87000 {
|
||||
compatible = "nordic,nrf-egu";
|
||||
reg = <0x87000 0x1000>;
|
||||
interrupts = <135 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
radio: radio@8a000 {
|
||||
compatible = "nordic,nrf-radio";
|
||||
reg = <0x8a000 0x1000>;
|
||||
interrupts = <138 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
dfe-supported;
|
||||
ieee802154-supported;
|
||||
ble-2mbps-supported;
|
||||
ble-coded-phy-supported;
|
||||
cs-supported;
|
||||
|
||||
ieee802154: ieee802154 {
|
||||
compatible = "nordic,nrf-ieee802154";
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* Note: In the nRF Connect SDK the SoftDevice Controller
|
||||
* is added and set as the default Bluetooth Controller.
|
||||
*/
|
||||
bt_hci_controller: bt_hci_controller {
|
||||
compatible = "zephyr,bt-hci-ll-sw-split";
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
dppic20: dppic@c2000 {
|
||||
compatible = "nordic,nrf-dppic";
|
||||
reg = <0xc2000 0x808>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ppib20: ppib@c3000 {
|
||||
compatible = "nordic,nrf-ppib";
|
||||
reg = <0xc3000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ppib21: ppib@c4000 {
|
||||
compatible = "nordic,nrf-ppib";
|
||||
reg = <0xc4000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ppib22: ppib@c5000 {
|
||||
compatible = "nordic,nrf-ppib";
|
||||
reg = <0xc5000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c20: i2c@c6000 {
|
||||
compatible = "nordic,nrf-twim";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xc6000 0x1000>;
|
||||
interrupts = <198 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
easydma-maxcnt-bits = <16>;
|
||||
status = "disabled";
|
||||
zephyr,pm-device-runtime-auto;
|
||||
};
|
||||
|
||||
spi20: spi@c6000 {
|
||||
/*
|
||||
* This spi node can be either SPIM or SPIS,
|
||||
* for the user to pick:
|
||||
* compatible = "nordic,nrf-spim" or
|
||||
* "nordic,nrf-spis".
|
||||
*/
|
||||
compatible = "nordic,nrf-spim";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xc6000 0x1000>;
|
||||
interrupts = <198 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
max-frequency = <DT_FREQ_M(8)>;
|
||||
easydma-maxcnt-bits = <16>;
|
||||
rx-delay-supported;
|
||||
rx-delay = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart20: uart@c6000 {
|
||||
compatible = "nordic,nrf-uarte";
|
||||
reg = <0xc6000 0x1000>;
|
||||
interrupts = <198 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
endtx-stoptx-supported;
|
||||
frame-timeout-supported;
|
||||
};
|
||||
|
||||
i2c21: i2c@c7000 {
|
||||
compatible = "nordic,nrf-twim";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xc7000 0x1000>;
|
||||
interrupts = <199 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
easydma-maxcnt-bits = <16>;
|
||||
status = "disabled";
|
||||
zephyr,pm-device-runtime-auto;
|
||||
};
|
||||
|
||||
spi21: spi@c7000 {
|
||||
/*
|
||||
* This spi node can be either SPIM or SPIS,
|
||||
* for the user to pick:
|
||||
* compatible = "nordic,nrf-spim" or
|
||||
* "nordic,nrf-spis".
|
||||
*/
|
||||
compatible = "nordic,nrf-spim";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xc7000 0x1000>;
|
||||
interrupts = <199 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
max-frequency = <DT_FREQ_M(8)>;
|
||||
easydma-maxcnt-bits = <16>;
|
||||
rx-delay-supported;
|
||||
rx-delay = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart21: uart@c7000 {
|
||||
compatible = "nordic,nrf-uarte";
|
||||
reg = <0xc7000 0x1000>;
|
||||
interrupts = <199 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
endtx-stoptx-supported;
|
||||
frame-timeout-supported;
|
||||
};
|
||||
|
||||
i2c22: i2c@c8000 {
|
||||
compatible = "nordic,nrf-twim";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xc8000 0x1000>;
|
||||
interrupts = <200 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
easydma-maxcnt-bits = <16>;
|
||||
status = "disabled";
|
||||
zephyr,pm-device-runtime-auto;
|
||||
};
|
||||
|
||||
spi22: spi@c8000 {
|
||||
/*
|
||||
* This spi node can be either SPIM or SPIS,
|
||||
* for the user to pick:
|
||||
* compatible = "nordic,nrf-spim" or
|
||||
* "nordic,nrf-spis".
|
||||
*/
|
||||
compatible = "nordic,nrf-spim";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xc8000 0x1000>;
|
||||
interrupts = <200 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
max-frequency = <DT_FREQ_M(8)>;
|
||||
easydma-maxcnt-bits = <16>;
|
||||
rx-delay-supported;
|
||||
rx-delay = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart22: uart@c8000 {
|
||||
compatible = "nordic,nrf-uarte";
|
||||
reg = <0xc8000 0x1000>;
|
||||
interrupts = <200 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
endtx-stoptx-supported;
|
||||
frame-timeout-supported;
|
||||
};
|
||||
|
||||
egu20: egu@c9000 {
|
||||
compatible = "nordic,nrf-egu";
|
||||
reg = <0xc9000 0x1000>;
|
||||
interrupts = <201 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
timer20: timer@ca000 {
|
||||
compatible = "nordic,nrf-timer";
|
||||
status = "disabled";
|
||||
reg = <0xca000 0x1000>;
|
||||
cc-num = <6>;
|
||||
max-bit-width = <32>;
|
||||
interrupts = <202 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
prescaler = <0>;
|
||||
};
|
||||
|
||||
timer21: timer@cb000 {
|
||||
compatible = "nordic,nrf-timer";
|
||||
status = "disabled";
|
||||
reg = <0xcb000 0x1000>;
|
||||
cc-num = <6>;
|
||||
max-bit-width = <32>;
|
||||
interrupts = <203 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
prescaler = <0>;
|
||||
};
|
||||
|
||||
timer22: timer@cc000 {
|
||||
compatible = "nordic,nrf-timer";
|
||||
status = "disabled";
|
||||
reg = <0xcc000 0x1000>;
|
||||
cc-num = <6>;
|
||||
max-bit-width = <32>;
|
||||
interrupts = <204 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
prescaler = <0>;
|
||||
};
|
||||
|
||||
timer23: timer@cd000 {
|
||||
compatible = "nordic,nrf-timer";
|
||||
status = "disabled";
|
||||
reg = <0xcd000 0x1000>;
|
||||
cc-num = <6>;
|
||||
max-bit-width = <32>;
|
||||
interrupts = <205 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
prescaler = <0>;
|
||||
};
|
||||
|
||||
timer24: timer@ce000 {
|
||||
compatible = "nordic,nrf-timer";
|
||||
status = "disabled";
|
||||
reg = <0xce000 0x1000>;
|
||||
cc-num = <6>;
|
||||
max-bit-width = <32>;
|
||||
interrupts = <206 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
prescaler = <0>;
|
||||
};
|
||||
|
||||
pdm20: pdm@d0000 {
|
||||
compatible = "nordic,nrf-pdm";
|
||||
status = "disabled";
|
||||
reg = <0xd0000 0x1000>;
|
||||
interrupts = <208 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
};
|
||||
|
||||
pdm21: pdm@d1000 {
|
||||
compatible = "nordic,nrf-pdm";
|
||||
status = "disabled";
|
||||
reg = <0xd1000 0x1000>;
|
||||
interrupts = <209 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
};
|
||||
|
||||
pwm20: pwm@d2000 {
|
||||
compatible = "nordic,nrf-pwm";
|
||||
status = "disabled";
|
||||
reg = <0xd2000 0x1000>;
|
||||
interrupts = <210 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
pwm21: pwm@d3000 {
|
||||
compatible = "nordic,nrf-pwm";
|
||||
status = "disabled";
|
||||
reg = <0xd3000 0x1000>;
|
||||
interrupts = <211 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
pwm22: pwm@d4000 {
|
||||
compatible = "nordic,nrf-pwm";
|
||||
status = "disabled";
|
||||
reg = <0xd4000 0x1000>;
|
||||
interrupts = <212 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
#pwm-cells = <3>;
|
||||
};
|
||||
|
||||
adc: adc@d5000 {
|
||||
compatible = "nordic,nrf-saadc";
|
||||
reg = <0xd5000 0x1000>;
|
||||
interrupts = <213 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
#io-channel-cells = <1>;
|
||||
};
|
||||
|
||||
nfct: nfct@d6000 {
|
||||
compatible = "nordic,nrf-nfct";
|
||||
reg = <0xd6000 0x1000>;
|
||||
interrupts = <214 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
temp: temp@d7000 {
|
||||
compatible = "nordic,nrf-temp";
|
||||
reg = <0xd7000 0x1000>;
|
||||
interrupts = <215 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio1: gpio@d8200 {
|
||||
compatible = "nordic,nrf-gpio";
|
||||
gpio-controller;
|
||||
reg = <0xd8200 0x300>;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <16>;
|
||||
status = "disabled";
|
||||
port = <1>;
|
||||
gpiote-instance = <&gpiote20>;
|
||||
};
|
||||
|
||||
gpiote20: gpiote@da000 {
|
||||
compatible = "nordic,nrf-gpiote";
|
||||
reg = <0xda000 0x1000>;
|
||||
status = "disabled";
|
||||
instance = <20>;
|
||||
};
|
||||
|
||||
i2s20: i2s@dd000 {
|
||||
compatible = "nordic,nrf-i2s";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0xdd000 0x1000>;
|
||||
interrupts = <221 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qdec20: qdec@e0000 {
|
||||
compatible = "nordic,nrf-qdec";
|
||||
reg = <0xe0000 0x1000>;
|
||||
interrupts = <224 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
qdec21: qdec@e1000 {
|
||||
compatible = "nordic,nrf-qdec";
|
||||
reg = <0xe1000 0x1000>;
|
||||
interrupts = <225 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
grtc: grtc@e2000 {
|
||||
compatible = "nordic,nrf-grtc";
|
||||
reg = <0xe2000 0x1000>;
|
||||
cc-num = <12>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
dppic30: dppic@102000 {
|
||||
compatible = "nordic,nrf-dppic";
|
||||
reg = <0x102000 0x808>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
ppib30: ppib@103000 {
|
||||
compatible = "nordic,nrf-ppib";
|
||||
reg = <0x103000 0x1000>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c30: i2c@104000 {
|
||||
compatible = "nordic,nrf-twim";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x104000 0x1000>;
|
||||
interrupts = <260 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
easydma-maxcnt-bits = <16>;
|
||||
status = "disabled";
|
||||
zephyr,pm-device-runtime-auto;
|
||||
};
|
||||
|
||||
spi30: spi@104000 {
|
||||
/*
|
||||
* This spi node can be either SPIM or SPIS,
|
||||
* for the user to pick:
|
||||
* compatible = "nordic,nrf-spim" or
|
||||
* "nordic,nrf-spis".
|
||||
*/
|
||||
compatible = "nordic,nrf-spim";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
reg = <0x104000 0x1000>;
|
||||
interrupts = <260 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
max-frequency = <DT_FREQ_M(8)>;
|
||||
easydma-maxcnt-bits = <16>;
|
||||
rx-delay-supported;
|
||||
rx-delay = <1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
uart30: uart@104000 {
|
||||
compatible = "nordic,nrf-uarte";
|
||||
reg = <0x104000 0x1000>;
|
||||
interrupts = <260 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
endtx-stoptx-supported;
|
||||
frame-timeout-supported;
|
||||
};
|
||||
|
||||
clock: clock@10e000 {
|
||||
compatible = "nordic,nrf-clock";
|
||||
reg = <0x10e000 0x1000>;
|
||||
interrupts = <261 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
power: power@10e000 {
|
||||
compatible = "nordic,nrf-power";
|
||||
reg = <0x10e000 0x1000>;
|
||||
ranges = <0x0 0x10e000 0x1000>;
|
||||
interrupts = <261 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
gpregret1: gpregret1@51c {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "nordic,nrf-gpregret";
|
||||
reg = <0x51c 0x1>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpregret2: gpregret2@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "nordic,nrf-gpregret";
|
||||
reg = <0x520 0x1>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
comp: comparator@106000 {
|
||||
/*
|
||||
* Use compatible "nordic,nrf-comp" to configure as COMP
|
||||
* Use compatible "nordic,nrf-lpcomp" to configure as LPCOMP
|
||||
*/
|
||||
compatible = "nordic,nrf-comp";
|
||||
reg = <0x106000 0x1000>;
|
||||
status = "disabled";
|
||||
interrupts = <262 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
};
|
||||
|
||||
#ifdef USE_NON_SECURE_ADDRESS_MAP
|
||||
/* intentionally empty because WDT30 is hardware fixed to Secure */
|
||||
#else
|
||||
wdt30: watchdog@108000 {
|
||||
compatible = "nordic,nrf-wdt";
|
||||
reg = <0x108000 0x620>;
|
||||
interrupts = <264 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
};
|
||||
#endif
|
||||
|
||||
wdt31: watchdog@109000 {
|
||||
compatible = "nordic,nrf-wdt";
|
||||
reg = <0x109000 0x620>;
|
||||
interrupts = <265 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
gpio0: gpio@10a000 {
|
||||
compatible = "nordic,nrf-gpio";
|
||||
gpio-controller;
|
||||
reg = <0x10a000 0x300>;
|
||||
#gpio-cells = <2>;
|
||||
ngpios = <5>;
|
||||
status = "disabled";
|
||||
port = <0>;
|
||||
gpiote-instance = <&gpiote30>;
|
||||
};
|
||||
|
||||
gpiote30: gpiote@10c000 {
|
||||
compatible = "nordic,nrf-gpiote";
|
||||
reg = <0x10c000 0x1000>;
|
||||
status = "disabled";
|
||||
instance = <30>;
|
||||
};
|
||||
|
||||
regulators: regulator@120000 {
|
||||
compatible = "nordic,nrf54l-regulators";
|
||||
reg = <0x120000 0x1000>;
|
||||
status = "disabled";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
vregmain: regulator@120600 {
|
||||
compatible = "nordic,nrf5x-regulator";
|
||||
reg = <0x120600 0x1>;
|
||||
status = "disabled";
|
||||
regulator-name = "VREGMAIN";
|
||||
regulator-initial-mode = <NRF5X_REG_MODE_LDO>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
rram_controller: rram-controller@5004b000 {
|
||||
compatible = "nordic,rram-controller";
|
||||
reg = <0x5004b000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <75 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
|
||||
cpuapp_rram: rram@0 {
|
||||
compatible = "soc-nv-flash";
|
||||
erase-block-size = <4096>;
|
||||
write-block-size = <16>;
|
||||
};
|
||||
};
|
||||
|
||||
cpuapp_ppb: cpuapp-ppb-bus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
cpuapp_nvic: interrupt-controller@e000e100 {
|
||||
#address-cells = <1>;
|
||||
compatible = "arm,v8m-nvic";
|
||||
reg = <0xe000e100 0xc00>;
|
||||
arm,num-irq-priority-bits = <3>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
cpuapp_systick: timer@e000e010 {
|
||||
compatible = "arm,armv8m-systick";
|
||||
reg = <0xe000e010 0x10>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
};
|
||||
};
|
8
dts/riscv/nordic/nrf54l05_cpuflpr.dtsi
Normal file
8
dts/riscv/nordic/nrf54l05_cpuflpr.dtsi
Normal file
|
@ -0,0 +1,8 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Nordic Semiconductor ASA
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <nordic/nrf54l05.dtsi>
|
||||
#include "nrf54l_05_10_15_cpuflpr.dtsi"
|
8
dts/riscv/nordic/nrf54l10_cpuflpr.dtsi
Normal file
8
dts/riscv/nordic/nrf54l10_cpuflpr.dtsi
Normal file
|
@ -0,0 +1,8 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Nordic Semiconductor ASA
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#include <nordic/nrf54l10.dtsi>
|
||||
#include "nrf54l_05_10_15_cpuflpr.dtsi"
|
|
@ -5,63 +5,4 @@
|
|||
*/
|
||||
|
||||
#include <nordic/nrf54l15.dtsi>
|
||||
|
||||
cpu: &cpuflpr {};
|
||||
clic: &cpuflpr_clic {};
|
||||
|
||||
/delete-node/ &cpuapp;
|
||||
/delete-node/ &cpuapp_rram;
|
||||
/delete-node/ &cpuapp_ppb;
|
||||
/delete-node/ &cpuapp_sram;
|
||||
|
||||
/ {
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&cpuflpr_clic>;
|
||||
ranges;
|
||||
};
|
||||
};
|
||||
|
||||
&cpuflpr {
|
||||
cpuflpr_vevif_rx: mailbox {
|
||||
compatible = "nordic,nrf-vevif-task-rx";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&cpuflpr_clic>;
|
||||
interrupts = <16 NRF_DEFAULT_IRQ_PRIORITY>,
|
||||
<17 NRF_DEFAULT_IRQ_PRIORITY>,
|
||||
<18 NRF_DEFAULT_IRQ_PRIORITY>,
|
||||
<19 NRF_DEFAULT_IRQ_PRIORITY>,
|
||||
<20 NRF_DEFAULT_IRQ_PRIORITY>,
|
||||
<21 NRF_DEFAULT_IRQ_PRIORITY>,
|
||||
<22 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
#mbox-cells = <1>;
|
||||
nordic,tasks = <7>;
|
||||
nordic,tasks-mask = <0x007f0000>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpuflpr_vpr {
|
||||
cpuflpr_vevif_tx: mailbox {
|
||||
compatible = "nordic,nrf-vevif-event-tx";
|
||||
#mbox-cells = <1>;
|
||||
nordic,events = <1>;
|
||||
nordic,events-mask = <0x00100000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
&cpuflpr_clic {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&grtc {
|
||||
interrupts = <226 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
};
|
||||
|
||||
&gpiote20 {
|
||||
interrupts = <218 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
};
|
||||
|
||||
&gpiote30 {
|
||||
interrupts = <268 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
};
|
||||
#include "nrf54l_05_10_15_cpuflpr.dtsi"
|
||||
|
|
65
dts/riscv/nordic/nrf54l_05_10_15_cpuflpr.dtsi
Normal file
65
dts/riscv/nordic/nrf54l_05_10_15_cpuflpr.dtsi
Normal file
|
@ -0,0 +1,65 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Nordic Semiconductor ASA
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
cpu: &cpuflpr {};
|
||||
clic: &cpuflpr_clic {};
|
||||
|
||||
/delete-node/ &cpuapp;
|
||||
/delete-node/ &cpuapp_rram;
|
||||
/delete-node/ &cpuapp_ppb;
|
||||
/delete-node/ &cpuapp_sram;
|
||||
|
||||
/ {
|
||||
soc {
|
||||
compatible = "simple-bus";
|
||||
interrupt-parent = <&cpuflpr_clic>;
|
||||
ranges;
|
||||
};
|
||||
};
|
||||
|
||||
&cpuflpr {
|
||||
cpuflpr_vevif_rx: mailbox {
|
||||
compatible = "nordic,nrf-vevif-task-rx";
|
||||
status = "disabled";
|
||||
interrupt-parent = <&cpuflpr_clic>;
|
||||
interrupts = <16 NRF_DEFAULT_IRQ_PRIORITY>,
|
||||
<17 NRF_DEFAULT_IRQ_PRIORITY>,
|
||||
<18 NRF_DEFAULT_IRQ_PRIORITY>,
|
||||
<19 NRF_DEFAULT_IRQ_PRIORITY>,
|
||||
<20 NRF_DEFAULT_IRQ_PRIORITY>,
|
||||
<21 NRF_DEFAULT_IRQ_PRIORITY>,
|
||||
<22 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
#mbox-cells = <1>;
|
||||
nordic,tasks = <7>;
|
||||
nordic,tasks-mask = <0x007f0000>;
|
||||
};
|
||||
};
|
||||
|
||||
&cpuflpr_vpr {
|
||||
cpuflpr_vevif_tx: mailbox {
|
||||
compatible = "nordic,nrf-vevif-event-tx";
|
||||
#mbox-cells = <1>;
|
||||
nordic,events = <1>;
|
||||
nordic,events-mask = <0x00100000>;
|
||||
status = "disabled";
|
||||
};
|
||||
};
|
||||
|
||||
&cpuflpr_clic {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&grtc {
|
||||
interrupts = <226 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
};
|
||||
|
||||
&gpiote20 {
|
||||
interrupts = <218 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
};
|
||||
|
||||
&gpiote30 {
|
||||
interrupts = <268 NRF_DEFAULT_IRQ_PRIORITY>;
|
||||
};
|
|
@ -44,6 +44,12 @@ zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54H20_CPUPPR NRF54H20_XXAA
|
|||
NRF_PPR)
|
||||
zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54H20_CPUFLPR NRF54H20_XXAA
|
||||
NRF_FLPR)
|
||||
zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54L05 NRF54L05_XXAA)
|
||||
zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54L05_CPUAPP NRF_APPLICATION)
|
||||
zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54L05_CPUFLPR NRF_FLPR)
|
||||
zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54L10 NRF54L10_XXAA)
|
||||
zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54L10_CPUAPP NRF_APPLICATION)
|
||||
zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54L10_CPUFLPR NRF_FLPR)
|
||||
zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54L15 NRF54L15_XXAA)
|
||||
zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54L15_CPUAPP NRF_APPLICATION)
|
||||
zephyr_compile_definitions_ifdef(CONFIG_SOC_NRF54L15_CPUFLPR NRF_FLPR)
|
||||
|
@ -172,7 +178,7 @@ if(DEFINED uicr_path)
|
|||
endif()
|
||||
endif()
|
||||
|
||||
if(CONFIG_SOC_NRF54L15_CPUAPP OR CONFIG_SOC_NRF54L20_ENGA_CPUAPP)
|
||||
if(CONFIG_SOC_NRF54L_CPUAPP_COMMON)
|
||||
dt_prop(clock_frequency PATH "/cpus/cpu@0" PROPERTY "clock-frequency")
|
||||
math(EXPR clock_frequency_mhz "${clock_frequency} / 1000000")
|
||||
zephyr_compile_definitions("NRF_CONFIG_CPU_FREQ_MHZ=${clock_frequency_mhz}")
|
||||
|
@ -222,6 +228,10 @@ mdk_svd_ifdef(CONFIG_SOC_NRF54H20_CPUAPP nrf54h20_application.svd)
|
|||
mdk_svd_ifdef(CONFIG_SOC_NRF54H20_CPUPPR nrf54h20_ppr.svd)
|
||||
mdk_svd_ifdef(CONFIG_SOC_NRF54H20_CPUFLPR nrf54h20_flpr.svd)
|
||||
mdk_svd_ifdef(CONFIG_SOC_NRF54H20_CPURAD nrf54h20_radiocore.svd)
|
||||
mdk_svd_ifdef(CONFIG_SOC_NRF54L05_CPUAPP nrf54l05_application.svd)
|
||||
mdk_svd_ifdef(CONFIG_SOC_NRF54L05_CPUFLPR nrf54l05_flpr.svd)
|
||||
mdk_svd_ifdef(CONFIG_SOC_NRF54L10_CPUAPP nrf54l10_application.svd)
|
||||
mdk_svd_ifdef(CONFIG_SOC_NRF54L10_CPUFLPR nrf54l10_flpr.svd)
|
||||
mdk_svd_ifdef(CONFIG_SOC_NRF54L15_CPUAPP nrf54l15_application.svd)
|
||||
mdk_svd_ifdef(CONFIG_SOC_NRF54L15_CPUFLPR nrf54l15_flpr.svd)
|
||||
mdk_svd_ifdef(CONFIG_SOC_NRF54L20_ENGA_CPUAPP nrf54l20_enga_application.svd)
|
||||
|
|
|
@ -1129,6 +1129,14 @@
|
|||
#include <nrfx_config_nrf54h20_ppr.h>
|
||||
#elif defined(NRF54H20_XXAA) && defined(NRF_FLPR)
|
||||
#include <nrfx_config_nrf54h20_flpr.h>
|
||||
#elif defined(NRF54L05_XXAA) && defined(NRF_APPLICATION)
|
||||
#include <nrfx_config_nrf54l05_application.h>
|
||||
#elif defined(NRF54L05_XXAA) && defined(NRF_FLPR)
|
||||
#include <nrfx_config_nrf54l05_flpr.h>
|
||||
#elif defined(NRF54L10_XXAA) && defined(NRF_APPLICATION)
|
||||
#include <nrfx_config_nrf54l10_application.h>
|
||||
#elif defined(NRF54L10_XXAA) && defined(NRF_FLPR)
|
||||
#include <nrfx_config_nrf54l10_flpr.h>
|
||||
#elif defined(NRF54L15_XXAA) && defined(NRF_APPLICATION)
|
||||
#include <nrfx_config_nrf54l15_application.h>
|
||||
#elif defined(NRF54L15_XXAA) && defined(NRF_FLPR)
|
||||
|
|
1775
modules/hal_nordic/nrfx/nrfx_config_nrf54l05_application.h
Normal file
1775
modules/hal_nordic/nrfx/nrfx_config_nrf54l05_application.h
Normal file
File diff suppressed because it is too large
Load diff
1784
modules/hal_nordic/nrfx/nrfx_config_nrf54l05_flpr.h
Normal file
1784
modules/hal_nordic/nrfx/nrfx_config_nrf54l05_flpr.h
Normal file
File diff suppressed because it is too large
Load diff
1775
modules/hal_nordic/nrfx/nrfx_config_nrf54l10_application.h
Normal file
1775
modules/hal_nordic/nrfx/nrfx_config_nrf54l10_application.h
Normal file
File diff suppressed because it is too large
Load diff
1784
modules/hal_nordic/nrfx/nrfx_config_nrf54l10_flpr.h
Normal file
1784
modules/hal_nordic/nrfx/nrfx_config_nrf54l10_flpr.h
Normal file
File diff suppressed because it is too large
Load diff
|
@ -136,6 +136,15 @@
|
|||
#define NRFX_COMP_CONFIG_LOG_LEVEL 3
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_DPPI_ENABLED
|
||||
*
|
||||
* Boolean. Accepted values: 0 and 1.
|
||||
*/
|
||||
#ifndef NRFX_DPPI_ENABLED
|
||||
#define NRFX_DPPI_ENABLED 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_DPPI_CONFIG_LOG_ENABLED
|
||||
*
|
||||
|
@ -160,6 +169,42 @@
|
|||
#define NRFX_DPPI_CONFIG_LOG_LEVEL 3
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_DPPI00_ENABLED
|
||||
*
|
||||
* Boolean. Accepted values: 0 and 1.
|
||||
*/
|
||||
#ifndef NRFX_DPPI00_ENABLED
|
||||
#define NRFX_DPPI00_ENABLED 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_DPPI10_ENABLED
|
||||
*
|
||||
* Boolean. Accepted values: 0 and 1.
|
||||
*/
|
||||
#ifndef NRFX_DPPI10_ENABLED
|
||||
#define NRFX_DPPI10_ENABLED 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_DPPI20_ENABLED
|
||||
*
|
||||
* Boolean. Accepted values: 0 and 1.
|
||||
*/
|
||||
#ifndef NRFX_DPPI20_ENABLED
|
||||
#define NRFX_DPPI20_ENABLED 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_DPPI30_ENABLED
|
||||
*
|
||||
* Boolean. Accepted values: 0 and 1.
|
||||
*/
|
||||
#ifndef NRFX_DPPI30_ENABLED
|
||||
#define NRFX_DPPI30_ENABLED 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_EGU_ENABLED
|
||||
*
|
||||
|
@ -274,22 +319,13 @@
|
|||
#define NRFX_GRTC_ENABLED 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_GRTC_CONFIG_SLEEP_ALLOWED
|
||||
*
|
||||
* Boolean. Accepted values: 0 and 1.
|
||||
*/
|
||||
#ifndef NRFX_GRTC_CONFIG_SLEEP_ALLOWED
|
||||
#define NRFX_GRTC_CONFIG_SLEEP_ALLOWED 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_GRTC_CONFIG_AUTOEN
|
||||
*
|
||||
* Boolean. Accepted values: 0 and 1.
|
||||
*/
|
||||
#ifndef NRFX_GRTC_CONFIG_AUTOEN
|
||||
#define NRFX_GRTC_CONFIG_AUTOEN 0
|
||||
#define NRFX_GRTC_CONFIG_AUTOEN 1
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
@ -581,6 +617,111 @@
|
|||
#define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_PPIB_ENABLED
|
||||
*
|
||||
* Boolean. Accepted values: 0 and 1.
|
||||
*/
|
||||
#ifndef NRFX_PPIB_ENABLED
|
||||
#define NRFX_PPIB_ENABLED 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_PPIB_CONFIG_LOG_ENABLED
|
||||
*
|
||||
* Boolean. Accepted values: 0 and 1.
|
||||
*/
|
||||
#ifndef NRFX_PPIB_CONFIG_LOG_ENABLED
|
||||
#define NRFX_PPIB_CONFIG_LOG_ENABLED 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_PPIB_CONFIG_LOG_LEVEL
|
||||
*
|
||||
* Integer value.
|
||||
* Supported values:
|
||||
* - Off = 0
|
||||
* - Error = 1
|
||||
* - Warning = 2
|
||||
* - Info = 3
|
||||
* - Debug = 4
|
||||
*/
|
||||
#ifndef NRFX_PPIB_CONFIG_LOG_LEVEL
|
||||
#define NRFX_PPIB_CONFIG_LOG_LEVEL 3
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_PPIB00_ENABLED
|
||||
*
|
||||
* Boolean. Accepted values: 0 and 1.
|
||||
*/
|
||||
#ifndef NRFX_PPIB00_ENABLED
|
||||
#define NRFX_PPIB00_ENABLED 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_PPIB01_ENABLED
|
||||
*
|
||||
* Boolean. Accepted values: 0 and 1.
|
||||
*/
|
||||
#ifndef NRFX_PPIB01_ENABLED
|
||||
#define NRFX_PPIB01_ENABLED 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_PPIB10_ENABLED
|
||||
*
|
||||
* Boolean. Accepted values: 0 and 1.
|
||||
*/
|
||||
#ifndef NRFX_PPIB10_ENABLED
|
||||
#define NRFX_PPIB10_ENABLED 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_PPIB11_ENABLED
|
||||
*
|
||||
* Boolean. Accepted values: 0 and 1.
|
||||
*/
|
||||
#ifndef NRFX_PPIB11_ENABLED
|
||||
#define NRFX_PPIB11_ENABLED 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_PPIB20_ENABLED
|
||||
*
|
||||
* Boolean. Accepted values: 0 and 1.
|
||||
*/
|
||||
#ifndef NRFX_PPIB20_ENABLED
|
||||
#define NRFX_PPIB20_ENABLED 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_PPIB21_ENABLED
|
||||
*
|
||||
* Boolean. Accepted values: 0 and 1.
|
||||
*/
|
||||
#ifndef NRFX_PPIB21_ENABLED
|
||||
#define NRFX_PPIB21_ENABLED 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_PPIB22_ENABLED
|
||||
*
|
||||
* Boolean. Accepted values: 0 and 1.
|
||||
*/
|
||||
#ifndef NRFX_PPIB22_ENABLED
|
||||
#define NRFX_PPIB22_ENABLED 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_PPIB30_ENABLED
|
||||
*
|
||||
* Boolean. Accepted values: 0 and 1.
|
||||
*/
|
||||
#ifndef NRFX_PPIB30_ENABLED
|
||||
#define NRFX_PPIB30_ENABLED 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_PRS_ENABLED
|
||||
*
|
||||
|
@ -1484,15 +1625,6 @@
|
|||
#define NRFX_UARTE_CONFIG_TX_LINK 1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_UARTE_RX_FIFO_FLUSH_WORKAROUND_MAGIC_BYTE
|
||||
*
|
||||
* Integer value. Minimum: 0. Maximum: 255.
|
||||
*/
|
||||
#ifndef NRFX_UARTE_RX_FIFO_FLUSH_WORKAROUND_MAGIC_BYTE
|
||||
#define NRFX_UARTE_RX_FIFO_FLUSH_WORKAROUND_MAGIC_BYTE 171
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY
|
||||
*
|
||||
|
|
|
@ -145,6 +145,15 @@
|
|||
#define NRFX_COREDEP_VPR_LEGACY 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_DPPI_ENABLED
|
||||
*
|
||||
* Boolean. Accepted values: 0 and 1.
|
||||
*/
|
||||
#ifndef NRFX_DPPI_ENABLED
|
||||
#define NRFX_DPPI_ENABLED 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_DPPI_CONFIG_LOG_ENABLED
|
||||
*
|
||||
|
@ -169,6 +178,42 @@
|
|||
#define NRFX_DPPI_CONFIG_LOG_LEVEL 3
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_DPPI00_ENABLED
|
||||
*
|
||||
* Boolean. Accepted values: 0 and 1.
|
||||
*/
|
||||
#ifndef NRFX_DPPI00_ENABLED
|
||||
#define NRFX_DPPI00_ENABLED 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_DPPI10_ENABLED
|
||||
*
|
||||
* Boolean. Accepted values: 0 and 1.
|
||||
*/
|
||||
#ifndef NRFX_DPPI10_ENABLED
|
||||
#define NRFX_DPPI10_ENABLED 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_DPPI20_ENABLED
|
||||
*
|
||||
* Boolean. Accepted values: 0 and 1.
|
||||
*/
|
||||
#ifndef NRFX_DPPI20_ENABLED
|
||||
#define NRFX_DPPI20_ENABLED 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_DPPI30_ENABLED
|
||||
*
|
||||
* Boolean. Accepted values: 0 and 1.
|
||||
*/
|
||||
#ifndef NRFX_DPPI30_ENABLED
|
||||
#define NRFX_DPPI30_ENABLED 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_EGU_ENABLED
|
||||
*
|
||||
|
@ -283,22 +328,13 @@
|
|||
#define NRFX_GRTC_ENABLED 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_GRTC_CONFIG_SLEEP_ALLOWED
|
||||
*
|
||||
* Boolean. Accepted values: 0 and 1.
|
||||
*/
|
||||
#ifndef NRFX_GRTC_CONFIG_SLEEP_ALLOWED
|
||||
#define NRFX_GRTC_CONFIG_SLEEP_ALLOWED 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_GRTC_CONFIG_AUTOEN
|
||||
*
|
||||
* Boolean. Accepted values: 0 and 1.
|
||||
*/
|
||||
#ifndef NRFX_GRTC_CONFIG_AUTOEN
|
||||
#define NRFX_GRTC_CONFIG_AUTOEN 0
|
||||
#define NRFX_GRTC_CONFIG_AUTOEN 1
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
@ -307,7 +343,7 @@
|
|||
* Boolean. Accepted values: 0 and 1.
|
||||
*/
|
||||
#ifndef NRFX_GRTC_CONFIG_AUTOSTART
|
||||
#define NRFX_GRTC_CONFIG_AUTOSTART 1
|
||||
#define NRFX_GRTC_CONFIG_AUTOSTART 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
|
@ -590,6 +626,111 @@
|
|||
#define NRFX_POWER_DEFAULT_CONFIG_IRQ_PRIORITY NRFX_DEFAULT_IRQ_PRIORITY
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_PPIB_ENABLED
|
||||
*
|
||||
* Boolean. Accepted values: 0 and 1.
|
||||
*/
|
||||
#ifndef NRFX_PPIB_ENABLED
|
||||
#define NRFX_PPIB_ENABLED 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_PPIB_CONFIG_LOG_ENABLED
|
||||
*
|
||||
* Boolean. Accepted values: 0 and 1.
|
||||
*/
|
||||
#ifndef NRFX_PPIB_CONFIG_LOG_ENABLED
|
||||
#define NRFX_PPIB_CONFIG_LOG_ENABLED 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_PPIB_CONFIG_LOG_LEVEL
|
||||
*
|
||||
* Integer value.
|
||||
* Supported values:
|
||||
* - Off = 0
|
||||
* - Error = 1
|
||||
* - Warning = 2
|
||||
* - Info = 3
|
||||
* - Debug = 4
|
||||
*/
|
||||
#ifndef NRFX_PPIB_CONFIG_LOG_LEVEL
|
||||
#define NRFX_PPIB_CONFIG_LOG_LEVEL 3
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_PPIB00_ENABLED
|
||||
*
|
||||
* Boolean. Accepted values: 0 and 1.
|
||||
*/
|
||||
#ifndef NRFX_PPIB00_ENABLED
|
||||
#define NRFX_PPIB00_ENABLED 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_PPIB01_ENABLED
|
||||
*
|
||||
* Boolean. Accepted values: 0 and 1.
|
||||
*/
|
||||
#ifndef NRFX_PPIB01_ENABLED
|
||||
#define NRFX_PPIB01_ENABLED 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_PPIB10_ENABLED
|
||||
*
|
||||
* Boolean. Accepted values: 0 and 1.
|
||||
*/
|
||||
#ifndef NRFX_PPIB10_ENABLED
|
||||
#define NRFX_PPIB10_ENABLED 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_PPIB11_ENABLED
|
||||
*
|
||||
* Boolean. Accepted values: 0 and 1.
|
||||
*/
|
||||
#ifndef NRFX_PPIB11_ENABLED
|
||||
#define NRFX_PPIB11_ENABLED 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_PPIB20_ENABLED
|
||||
*
|
||||
* Boolean. Accepted values: 0 and 1.
|
||||
*/
|
||||
#ifndef NRFX_PPIB20_ENABLED
|
||||
#define NRFX_PPIB20_ENABLED 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_PPIB21_ENABLED
|
||||
*
|
||||
* Boolean. Accepted values: 0 and 1.
|
||||
*/
|
||||
#ifndef NRFX_PPIB21_ENABLED
|
||||
#define NRFX_PPIB21_ENABLED 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_PPIB22_ENABLED
|
||||
*
|
||||
* Boolean. Accepted values: 0 and 1.
|
||||
*/
|
||||
#ifndef NRFX_PPIB22_ENABLED
|
||||
#define NRFX_PPIB22_ENABLED 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_PPIB30_ENABLED
|
||||
*
|
||||
* Boolean. Accepted values: 0 and 1.
|
||||
*/
|
||||
#ifndef NRFX_PPIB30_ENABLED
|
||||
#define NRFX_PPIB30_ENABLED 0
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_PRS_ENABLED
|
||||
*
|
||||
|
@ -1484,15 +1625,6 @@
|
|||
#define NRFX_UARTE_CONFIG_TX_LINK 1
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_UARTE_RX_FIFO_FLUSH_WORKAROUND_MAGIC_BYTE
|
||||
*
|
||||
* Integer value. Minimum: 0. Maximum: 255.
|
||||
*/
|
||||
#ifndef NRFX_UARTE_RX_FIFO_FLUSH_WORKAROUND_MAGIC_BYTE
|
||||
#define NRFX_UARTE_RX_FIFO_FLUSH_WORKAROUND_MAGIC_BYTE 171
|
||||
#endif
|
||||
|
||||
/**
|
||||
* @brief NRFX_UARTE_DEFAULT_CONFIG_IRQ_PRIORITY
|
||||
*
|
||||
|
|
|
@ -21,15 +21,27 @@ config SOC_NRF54L_CPUAPP_COMMON
|
|||
select HAS_HW_NRF_RADIO_IEEE802154
|
||||
select HAS_POWEROFF
|
||||
|
||||
config SOC_NRF54L05_CPUAPP
|
||||
select SOC_NRF54L_CPUAPP_COMMON
|
||||
|
||||
config SOC_NRF54L10_CPUAPP
|
||||
select SOC_NRF54L_CPUAPP_COMMON
|
||||
|
||||
config SOC_NRF54L15_CPUAPP
|
||||
select SOC_NRF54L_CPUAPP_COMMON
|
||||
|
||||
config SOC_NRF54L20_ENGA_CPUAPP
|
||||
select SOC_NRF54L_CPUAPP_COMMON
|
||||
config SOC_NRF54L05_CPUFLPR
|
||||
depends on RISCV_CORE_NORDIC_VPR
|
||||
|
||||
config SOC_NRF54L10_CPUFLPR
|
||||
depends on RISCV_CORE_NORDIC_VPR
|
||||
|
||||
config SOC_NRF54L15_CPUFLPR
|
||||
depends on RISCV_CORE_NORDIC_VPR
|
||||
|
||||
config SOC_NRF54L20_ENGA_CPUAPP
|
||||
select SOC_NRF54L_CPUAPP_COMMON
|
||||
|
||||
if SOC_SERIES_NRF54LX
|
||||
|
||||
config SOC_NRF54LX_SKIP_CLOCK_CONFIG
|
||||
|
|
|
@ -1,11 +0,0 @@
|
|||
# Nordic Semiconductor nRF54L15 MCU
|
||||
|
||||
# Copyright (c) 2024 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_NRF54L15_CPUAPP
|
||||
|
||||
config NUM_IRQS
|
||||
default 271
|
||||
|
||||
endif # SOC_NRF54L15_CPUAPP
|
11
soc/nordic/nrf54l/Kconfig.defconfig.nrf54l_05_10_15_cpuapp
Normal file
11
soc/nordic/nrf54l/Kconfig.defconfig.nrf54l_05_10_15_cpuapp
Normal file
|
@ -0,0 +1,11 @@
|
|||
# Nordic Semiconductor nRF54 L05, L10 and L15 MCUs
|
||||
|
||||
# Copyright (c) 2024 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_NRF54L05_CPUAPP || SOC_NRF54L10_CPUAPP || SOC_NRF54L15_CPUAPP
|
||||
|
||||
config NUM_IRQS
|
||||
default 271
|
||||
|
||||
endif # SOC_NRF54L05_CPUAPP || SOC_NRF54L10_CPUAPP || SOC_NRF54L15_CPUAPP
|
|
@ -1,9 +1,9 @@
|
|||
# Nordic Semiconductor nRF54L15 MCU
|
||||
# Nordic Semiconductor nRF54 L05, L10 and L15 MCUs
|
||||
|
||||
# Copyright (c) 2024 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
if SOC_NRF54L15_CPUFLPR
|
||||
if SOC_NRF54L05_CPUFLPR || SOC_NRF54L10_CPUFLPR || SOC_NRF54L15_CPUFLPR
|
||||
|
||||
config NUM_IRQS
|
||||
default 287
|
||||
|
@ -12,4 +12,4 @@ config NUM_IRQS
|
|||
config ASSERT
|
||||
default n
|
||||
|
||||
endif # SOC_NRF54L15_CPUFLPR
|
||||
endif # SOC_NRF54L05_CPUFLPR || SOC_NRF54L10_CPUFLPR || SOC_NRF54L15_CPUFLPR
|
|
@ -3,6 +3,42 @@
|
|||
# Copyright (c) 2024 Nordic Semiconductor ASA
|
||||
# SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
config SOC_NRF54L05
|
||||
bool
|
||||
select SOC_SERIES_NRF54LX
|
||||
help
|
||||
NRF54L05
|
||||
|
||||
config SOC_NRF54L05_CPUAPP
|
||||
bool
|
||||
select SOC_NRF54L05
|
||||
help
|
||||
NRF54L05 CPUAPP
|
||||
|
||||
config SOC_NRF54L05_CPUFLPR
|
||||
bool
|
||||
select SOC_NRF54L05
|
||||
help
|
||||
NRF54L05 CPUFLPR
|
||||
|
||||
config SOC_NRF54L10
|
||||
bool
|
||||
select SOC_SERIES_NRF54LX
|
||||
help
|
||||
NRF54L10
|
||||
|
||||
config SOC_NRF54L10_CPUAPP
|
||||
bool
|
||||
select SOC_NRF54L10
|
||||
help
|
||||
NRF54L10 CPUAPP
|
||||
|
||||
config SOC_NRF54L10_CPUFLPR
|
||||
bool
|
||||
select SOC_NRF54L10
|
||||
help
|
||||
NRF54L10 CPUFLPR
|
||||
|
||||
config SOC_NRF54L15
|
||||
bool
|
||||
select SOC_SERIES_NRF54LX
|
||||
|
@ -40,5 +76,7 @@ config SOC_NRF54L20_ENGA_CPUAPP
|
|||
NRF54L20 ENGA CPUAPP
|
||||
|
||||
config SOC
|
||||
default "nrf54l05" if SOC_NRF54L05
|
||||
default "nrf54l10" if SOC_NRF54L10
|
||||
default "nrf54l15" if SOC_NRF54L15
|
||||
default "nrf54l20" if SOC_NRF54L20
|
||||
|
|
|
@ -21,6 +21,14 @@ family:
|
|||
- name: cpunet
|
||||
- name: nrf54l
|
||||
socs:
|
||||
- name: nrf54l05
|
||||
cpuclusters:
|
||||
- name: cpuapp
|
||||
- name: cpuflpr
|
||||
- name: nrf54l10
|
||||
cpuclusters:
|
||||
- name: cpuapp
|
||||
- name: cpuflpr
|
||||
- name: nrf54l15
|
||||
cpuclusters:
|
||||
- name: cpuapp
|
||||
|
@ -94,6 +102,12 @@ runners:
|
|||
- qualifiers:
|
||||
- nrf9161
|
||||
- nrf9161/ns
|
||||
- qualifiers:
|
||||
- nrf54l05/cpuapp
|
||||
- nrf54l05/cpuflpr
|
||||
- qualifiers:
|
||||
- nrf54l10/cpuapp
|
||||
- nrf54l10/cpuflpr
|
||||
- qualifiers:
|
||||
- nrf54l15/cpuapp
|
||||
- nrf54l15/cpuflpr
|
||||
|
@ -148,6 +162,12 @@ runners:
|
|||
- qualifiers:
|
||||
- nrf9161
|
||||
- nrf9161/ns
|
||||
- qualifiers:
|
||||
- nrf54l05/cpuapp
|
||||
- nrf54l05/cpuflpr
|
||||
- qualifiers:
|
||||
- nrf54l10/cpuapp
|
||||
- nrf54l10/cpuflpr
|
||||
- qualifiers:
|
||||
- nrf54l15/cpuapp
|
||||
- nrf54l15/cpuflpr
|
||||
|
@ -202,6 +222,12 @@ runners:
|
|||
- qualifiers:
|
||||
- nrf9161
|
||||
- nrf9161/ns
|
||||
- qualifiers:
|
||||
- nrf54l05/cpuapp
|
||||
- nrf54l05/cpuflpr
|
||||
- qualifiers:
|
||||
- nrf54l10/cpuapp
|
||||
- nrf54l10/cpuflpr
|
||||
- qualifiers:
|
||||
- nrf54l15/cpuapp
|
||||
- nrf54l15/cpuflpr
|
||||
|
|
|
@ -338,7 +338,7 @@ CHECK_DT_REG(usbreg, NRF_USBREGULATOR);
|
|||
CHECK_DT_REG(vmc, NRF_VMC);
|
||||
CHECK_DT_REG(cpuflpr_clic, NRF_FLPR_VPRCLIC);
|
||||
CHECK_DT_REG(cpuppr_clic, NRF_PPR_VPRCLIC);
|
||||
#if defined(CONFIG_SOC_NRF54L15)
|
||||
#if defined(CONFIG_SOC_NRF54L05) || defined(CONFIG_SOC_NRF54L10) || defined(CONFIG_SOC_NRF54L15)
|
||||
CHECK_DT_REG(cpuflpr_vpr, NRF_VPR00);
|
||||
#elif defined(CONFIG_NRF_PLATFORM_HALTIUM)
|
||||
CHECK_DT_REG(cpuflpr_vpr, NRF_VPR121);
|
||||
|
|
|
@ -26,7 +26,7 @@
|
|||
#define TEST_AREA_SIZE FIXED_PARTITION_SIZE(TEST_AREA)
|
||||
#define TEST_AREA_DEVICE FIXED_PARTITION_DEVICE(TEST_AREA)
|
||||
|
||||
#if defined(CONFIG_SOC_NRF54L15)
|
||||
#if defined(CONFIG_SOC_NRF54L05) || defined(CONFIG_SOC_NRF54L10) || defined(CONFIG_SOC_NRF54L15)
|
||||
#define TEST_FLASH_START (DT_REG_ADDR(DT_MEM_FROM_FIXED_PARTITION(DT_NODELABEL(TEST_AREA))))
|
||||
#define TEST_FLASH_SIZE (DT_REG_SIZE(DT_MEM_FROM_FIXED_PARTITION(DT_NODELABEL(TEST_AREA))))
|
||||
#elif defined(CONFIG_SOC_NRF54H20)
|
||||
|
|
|
@ -10,7 +10,8 @@
|
|||
|
||||
int dummy_value;
|
||||
|
||||
#if defined(CONFIG_SOC_NRF54L15) || defined(CONFIG_SOC_NRF54H20)
|
||||
#if defined(CONFIG_SOC_NRF54L05) || defined(CONFIG_SOC_NRF54L10) || \
|
||||
defined(CONFIG_SOC_NRF54L15) || defined(CONFIG_SOC_NRF54H20)
|
||||
#define EXPECTED_MTU_VALUE (0)
|
||||
#define DATA_TRANSFER_MODE_SUPPORTED (0)
|
||||
#define REMOTE_BUSY_SUPPORTED (0)
|
||||
|
|
|
@ -42,7 +42,8 @@
|
|||
#define DEFAULT_WINDOW_MIN (0U)
|
||||
|
||||
/* Align tests to the specific target: */
|
||||
#if defined(CONFIG_SOC_NRF54L15) || defined(CONFIG_SOC_NRF54H20) || defined(CONFIG_SOC_NRF9280)
|
||||
#if defined(CONFIG_SOC_NRF54L05) || defined(CONFIG_SOC_NRF54L10) || \
|
||||
defined(CONFIG_SOC_NRF54L15) || defined(CONFIG_SOC_NRF54H20) || defined(CONFIG_SOC_NRF9280)
|
||||
#define WDT_TEST_FLAGS \
|
||||
(WDT_DISABLE_SUPPORTED | WDT_FLAG_RESET_SOC_SUPPORTED | \
|
||||
WDT_FLAG_ONLY_ONE_TIMEOUT_VALUE_SUPPORTED | WDT_OPT_PAUSE_IN_SLEEP_SUPPORTED | \
|
||||
|
|
|
@ -56,7 +56,7 @@
|
|||
*/
|
||||
#define IRQ0_PRIO IRQ_DEFAULT_PRIORITY
|
||||
#define IRQ1_PRIO 0x0
|
||||
#elif defined(CONFIG_SOC_NRF54L15_CPUFLPR)
|
||||
#elif defined(CONFIG_SOC_SERIES_NRF54LX) && defined(CONFIG_RISCV_CORE_NORDIC_VPR)
|
||||
#define IRQ0_LINE 16
|
||||
#define IRQ1_LINE 17
|
||||
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue