CS hold time parameter is not correct which may cause bus fault
randomly.
System hang during status register reading after flash progromming which
is caused by parameter accessing in XIP mode.
Add dummy delay for READ command according the flash datasheet which is
required for SDR mode.
Use FlexSPI internal divider for clock updating instead of register in
CCM to avoid potential risk caused by flash access during clock updating
procedure.
Signed-off-by: Raymond Lei <raymond.lei@nxp.com>
Increase the number of HCI command transmit buffers on ESP32 to prevent
sporadic command timeouts. This is a temporary workaround.
Upcoming changes to the BLE proprietary blobs will address the root cause.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
List NEORV32 v1.11.6 as the currently supported version. No changes to the
in-tree drivers needed for the changes between v1.11.3 and v1.11.6.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Previously the clock was not attached to all Flexcomm ports. Some ports
were configured with FRO_12M, others with FRO_HF, some not at all.
Now every Flexcomm port in I2C, SPI or USART mode uses the FRO_HF clock,
if it is enabled in the device tree, to cover all use cases.
Signed-off-by: Fabian Otto <fabian.otto@rohde-schwarz.com>
This patch allows to link the request of the linklayer for a
temperature calibration to the temperature driver.
The linklayer will then adapt and trigger its calibration related to
the current temperature.
Signed-off-by: Romain Jayles <romain.jayles@st.com>
Add LINKLAYER_PLAT_EnableBackupDomainAccess() and
LINKLAYER_PLAT_DisableBackupDomainAccess() to use Zephyr resources
that use a reference counter for access requests, for enabling
and disabling access the BackupDomain resources.
Bump hal_stm32 module to the revision integrating related stm32wba
BLE updates.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Use recently added SoCs functions to request access to SoC backup
domain resources These function use a reference counter to track these
request and ensure the resources are accessible as long as at least a
consumer requires access.
Fixes issue 90942.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Add SoC functions to enable/disable STM32 backup Domain access
and use a reference counter to track requests. These helper functions
may be called from a interrupt context. On domain access enable, the
function loops until written bit is set however this is expected to be
effective after very few clock cycles and seems not even required
(not mentioned in any SoC documentation). The loop is preserved as
used in previous implementation.
Among all supported STM32 SoCs, only STM32C0 and STM32WB0 series do not
implement this mechanism hence add option CONFIG_STM32_BACKUP_PROTECTION
that is enabled for all SoC series but these 2.
Fixes issue 90942.
Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com>
Fixes: commit 5f4b51f9b1 ("soc: intel_adsp: add a debug window slot
descriptor") - restore the maximum debug slot number. The added slot
resides in page 0, not at the end of the array. The bug didn't have
any run-time implications - no access to those high index value slots
is performed, all platforms so far have 3 slots at most, so this is a
pure correctness fix.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Make axisram2 which is used in fsbl mode available as well to
chainloaded application in order not to loose 1M of RAM
In order to avoid conflicts with bootloader, verify that code + ro data
of the loaded application won't go further than bootloader start address.
This is done with a linker assert.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Add support for npck3m8k board that is a development platform to
evaluate the Nuvoton NPCK3 embedded controller.
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
STM32U0 specific changes to enable the PM feature.
Base on the power-related code from the STM32U5 target.
Signed-off-by: Mickael Bosch <mickael.bosch@linux.com>
Use MMIO for device memory mapping, so that the driver can be used
both on MCU and MPU.
Add removed static MMU mapping in some platform accordingly.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
The existing SAI diver cannot initialize the PLL on the
board, so the PLL settings will not be performed in the
driver.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Porting gp_renesas_isr_context variable used in FSP interrupt source
to unify with RZ/V2H and prevent build error since they share the same
hal_renesas source code.
Signed-off-by: Tien Nguyen <tien.nguyen.zg@renesas.com>
- Add support for gpio interrupt on RX130.
- Add support for gpio-keys input subsys on RSK_RX130_512KB boards.
Signed-off-by: Phi Tran <phi.tran.jg@bp.renesas.com>
What is changed?
- Add initial support for the MPS4 Corstone-315 FVP platform, including
board and SoC definitions.The qualifier to build/run application
with board mps4/corstone315 is
`mps4/corstone315/fvp` for secure and
`mps3/corstone315/fvp/ns` for non-secure.
- FVP testing with corstone315 uses the ARM FVP
`FVP_Corstone_SSE-315`.
Why do we need this change?
- This enables FVP support for corstone315.
- A separate FVP variant was added for corstone315 as the TFM board
used for non-secure variant differs for FPGA and FVP.
TFM board `arm/mps4/corstone315` support is present but no FVP support
yet. We can test this by building TF-M with
-DTFM_PLATFORM=arm/mps4/corstone315 and then lauching FVP:
FVP_Corstone_SSE-315 --data "bl1_1.bin"@0x11000000
--data "cm_provisioning_bundle.bin"@0x12024000
--data "dm_provisioning_bundle.bin"@0x1202aa00
--data "bl2_signed.bin"@0x12031400
--data "tfm_s_ns_signed.bin"@0x38000000
Signed-off-by: Shaunak saha <ssaha@tsavoritesi.com>
Fixes: commit a73f20214 ("drivers: wifi: siwx91x: Fix boot_config")
Disabled the 160 MHz feature due to stability issues (mode change)
Signed-off-by: Muzaffar Ahmed <muzaffar.ahmed@silabs.com>
Add gdbstub support to Meteor Lake and a base for other ACE
platforms. Based on the Tiger Lake implementation, but some registers
do differ.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Uses SRAM debug region to pass GDB messages to host, which is exposed
via PTY by cavstool with -d arg or using the SOF kernel driver via a
debugfs file.
Signed-off-by: Noah Klayman <noah.klayman@intel.com>
[guennadi.liakhovetski@linux.intel.com: update to current "main"]
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
Add a debug window slot descriptor for the debug window area in the
first page, where descriptors themselves occupy the first few
hundreds of bytes. This area begins 1024 bytes after the beginning of
the debug window until the end of the page and is therefore 3 * 1024
bytes large. Descriptor 15 will be used to describe it and it will be
used for the GDB stub.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
All debug window slot indices should be defined in
adsp_debug_window.h, move them there and use them consistently.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
When the FLEXCOM is activated in the DT, configure it's register
region with strong ordered, read and write access.
Signed-off-by: Tony Han <tony.han@microchip.com>
Create and select the proper module device tree file which loads the
correct radio config for the MGM240P module.
Signed-off-by: Tamas Jozsi <tamas.jozsi@silabs.com>
This enables the clock_control driver build on bl60x.
It is currently deferred init, due to being incompatible
with current SDK-based boot, to avoid later giant PR.
Signed-off-by: Camille BAUD <mail@massdriver.space>
The current CMakeLists.txt uses hardcoded flash addresses for the
bootloader and application, which may not match the slot defined
in the DTS file. This can lead to inconsistencies when flashing
and running images.
This update introduces support for using CONFIG_FLASH_LOAD_OFFSET
and applies CONFIG_BUILD_OUTPUT_ADJUST_LMA if specified,
ensuring that the final image address aligns with the DTS
and runtime expectations.
Note: For ESP32-C6, a custom workaround is included since the
LPCORE does not support MCUboot images.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Modify the STM32 pinctrl driver and SoC-specific pinctrl macros
to introduce support of the st,stm32n6-pinctrl variant.
Signed-off-by: Mathieu Choplain <mathieu.choplain@st.com>
Set the LTDC buffer alignment to 256 in order to avoid an
issue when accessing to PSRAM via XSPI.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
The SMH attribute when using the XSPI PSRAM is set to EXTERNAL (2)
within the driver hence set default for both LTDC and video
buffer SMH attribute to 2 if all conditions are validated.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Several subsystems have configuration options that allow large buffers
to be placed in specialized memory sections. When PSRAM is enabled, the
MBEDTLS heap and LVGL heap and buffer can be relocated to custom sections
within the PSRAM segment.
Enabling `CONFIG_ESP_SPIRAM` together with any of the following options:
* `CONFIG_MBEDTLS_HEAP_CUSTOM_SECTION`
* `CONFIG_LV_Z_MEMORY_POOL_CUSTOM_SECTION`
* `CONFIG_LV_Z_VDB_CUSTOM_SECTION`
will place the corresponding buffers into the `.mbedtls_heap`,
`.lvgl_heap`, and `.lvgl_buf` sections, respectively.
If none of these custom section options are enabled, the buffers will
fall back to the `.ext_ram.bss` section.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Since the LPSPI drivers no long use MCUX at all, remove the MCUX
branding, to avoid confusion. In the future if an implementation uses
the MCUX SDK driver, it should specifically be called by MCUX in the
name.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
