- Define the HCI node in the SoC series' dtsi.
- Adjust main thread stack sizes and buffer counts required
for Blutooth operation.
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
The RXv2 and RXv3 core support FPU in CPU.
This enable FPU instruction build for the RX140, RX261 and RX26T
Signed-off-by: Duy Nguyen <duy.nguyen.xa@renesas.com>
esp_restart_noos() and esp_system_reset_modules_on_exit() disable the
flash cache before resetting the CPU. Without proper IRAM placement,
these functions remain in flash. After Cache_Disable_Cache() returns,
the CPU attempts to fetch the next instruction from flash-mapped
memory which is no longer accessible, causing a CPU_LOCKUP on SoCs
where cache invalidation is immediate.
Add linker entries to place esp_restart_noos,
esp_system_reset_modules_on_exit (and esp_restart_noos_dig for ESP32)
in IRAM text and DRAM rodata sections across all Espressif SoCs.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Since the enum validation for load-capacitance-femtofarad was removed
from the DTS binding, add a BUILD_ASSERT to ensure the provided value
is within the valid range (3000-18000 fF) at compile time.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
Add SoC support for the Bouffalo Lab BL70XL series (BL702L, BL704L).
RISC-V E24 core with CLIC interrupt controller, L1 cache, FPU, and
XIP flash execution.
Includes SoC initialization (CLIC clear, HBN/PDS fastboot flag clear,
SEAM config), system reboot, Kconfig for two SoC variants
(BL702L10Q2I, BL704L22Q2H), soc.yml entries, and e24 common code
inclusion.
Signed-off-by: William Markezana <william.markezana@gmail.com>
In the current implementation the platforms samd20/21 and samr21 can
only use an external crystal or clock to drive RTC. This enable the
possibility to select the internal OSC32K as an alternative for low
cost boards that don't use an external 32.768 kHz source.
Fixes#102352
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
This is necessary for ADC to control GPIO analog multiplexes,
when GPIOs are set as secure (by default).
Signed-off-by: Adam BERLINGER <adam.berlinger@st.com>
Add the new stm32h5e4/5 and stm32h5f4/5 devices of the stm32H5 family
with 4MB of flash and Arm® Cortex®-M33 core.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
Rename SOC_XILINX_XC7Z* Kconfig symbols to SOC_XC7Z* to align
with HWMv2 guidelines. The SOC Kconfig symbol name must match
the uppercase version of the SOC name defined in soc.yml.
Before: config SOC_XILINX_XC7Z010 with default "xc7z010"
After: config SOC_XC7Z010 with default "xc7z010"
This allows CI checks to detect typos and enables future
auto-generation of SOC_* symbols from soc.yml files.
Updated files:
- soc/xlnx/zynq7000/xc7zxxx/Kconfig.soc
- soc/xlnx/zynq7000/xc7zxxxs/Kconfig.soc
- boards/digilent/zybo/Kconfig.zybo
- boards/qemu/cortex_a9/Kconfig.qemu_cortex_a9
Fixes: #69317
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
The nodelabels do not have any relation to the Nordic MDK and can be
named differently between SoCs.
Signed-off-by: Johann Fischer <johann.fischer@nordicsemi.no>
This commit addresses two issues during ISR restoration:
1. Support IRQ_DIRECT_CONNECT: Compare the current RAM vector table
against Zephyr's initial flash vector table (`_vector_start`)
instead of hardcoding `_isr_wrapper`. This correctly identifies
ROM-patched ISRs without falsely overriding Zephyr direct ISRs.
2. Prevent race conditions: Add `irq_lock()` and reorder
`NVIC_EnableIRQ` to safely handle driver interrupts that might
already be active during late initialization.
Note: There is a known limitation with this approach. If a user
registers a direct ISR on an IRQ that the ROM also registers, the
ROM's ISR will take precedence. However, this overlap is practically
rare as users do not typically override ROM-owned interrupts.
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
Add initialization of critical components for the RTL8752H
series.
Key initializations include:
- Realtek OS abstraction layer.
- Clock active mode settings.
- Power Management (PM).
- PHY modules.
- Bluetooth controller ROM initialization.
Note: A mechanism is introduced to synchronize the RAM Vector Table between
Realtek's ROM code (which writes raw ISRs) and Zephyr's interrupt
management subsystem (sw_isr_table).
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
- Add NBU pinmux to configure HDI mode with external radio
- Define nbu_handler to the MU interrupt handler
- Enable TSTMR0 clock at init
- Enable connectivity framework, MCMGR, rpmsg-lite
- Enable MU driver when selecting NXP_RF_IMU
- Disable LPUART1 to avoid pin conflicts with radio interface
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
When using an external radio, we need to configure pins for HDI mode.
Since it's specific to NBU, we can add this control in the nxp_nbu
driver.
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
Define a shared memory section in STCM, this shared memory is used
to transmit data to the NBU core.
This shared STCM section must be used through non-secure address range
because the NBU core can only access non-secure memory regions, and
the main core must reference non-secure addresses in the data shared
with the NBU core.
Since the MCXW70 doesn't have an SMU2, reworked the sections.ld file
to use a macro-based approach to determine the node label.
This allows to differentiate devices that have SMU2 from those that
don't, while reusing the same sections.ld file.
Use "stcm_shared" as node label for MCXW70.
Use node status in sections.ld since all regions are not available
on all SoCs.
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
- Configure FLEXSPI2 root clock using SYS_PLL3_PFD2 with divider 2
when FLEXSPI2 is enabled and not used for XIP flash
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Add counter timer driver support for Realtek Bee series SoCs,
including RTL87x2G and RTL8752H.
This driver is based on the hardware timer and supports:
- Relative alarm configuration
- Top value configuration
Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
BOARD_GrantTRDCFullPermissions() flow:
- Request TRDC ownership via ELE for AON/MEGA/WAKEUP
- Apply SDK-aligned DAC (including TRDC3 MDAC assignments)
- Grant full access control settings for TRDC1/TRDC2
Refactor the implementation out of soc.c into a dedicated trdc_setup.c
file to keep soc.c focused on early init sequencing, and add it to the
SoC CMakeLists.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
- Gate off M7 clock before clearing M7_CFG[WAIT] (CPUWAIT) and gate
it back on after the deassert. (This is the process requirement
in RT118X RM)
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
The default value 0x200 wasn't compatible with IVT alignment which was
set to 0x400 due to large number of ISR.
Signed-off-by: Petr Buchta <petr.buchta@nxp.com>
The RW612 will enter PM_STATE_RUNTIME_IDLE mode when idle but the
average current is higher than expected. The expected current should be
around 15mA but the actual current is nearly 18mA.
By disabling AVPLL and TDDR clock in clock_init, the current of
PM_STATE_RUNTIME_IDLE mode is ok, which is around 15.5mA
Signed-off-by: Hui Bai <hui.bai@nxp.com>
Select HAS_PM for RTS5912, this SoC supports PM and there's some
"default y" entries for it, resulting in a combination where PM is
selected and cannot be unselected.
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
Replaces usage of these deprecated macros with ones that support
fixed and mapped partition compatibles. Also includes an update to
hal_espressif which also (rightly or wrongly) has zephyr specific
code in it
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This change is being reverted as devices should be updated to use
the new zephyr,mapped-partitions binding instead in which the
ranges property should be used
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
SOC_IMX943_PM_MCORE had no dependency on NXP_SCMI_CPU_DOMAIN_HELPERS,
causing pm_mcore.c to be compiled even when the scmi_nxp_cpu_* symbols
were not built, resulting in undefined reference link failures.
Fix by adding depends on NXP_SCMI_CPU_DOMAIN_HELPERS to the Kconfig
entry, ensuring pm_mcore.c is only compiled when the full SCMI CPU
domain stack is present. With this change, enabling CONFIG_PM=y without
the required SCMI stack is caught at Kconfig level rather than failing
at link time.
Fixes#103992
Signed-off-by: Jjateen Gundesha <jjateen97@gmail.com>
Defining `__soc_handle_irq` (part of the code path run on every
interrupt) as a jump to `get_irq` introduces unnecessary latency to
interrupt handling and inflates code size. Since `get_irq` is not
otherwise called, rename it to `__soc_handle_irq` and delete the old
trampoline.
The signature of the function is changed to match the declaration of
`__soc_handle_irq`, which is possible since commit
495a3281d4679c19703810afbac9607d16ac6788 corrected its declaration.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Set zephyr,system-timer = &lptmr0 in the MCX-W7x and MCX-W70 DTSI
/chosen nodes. lptmr1 remains available for use by the counter driver.
Both drivers can be active simultaneously since they use separate
hardware instances.
Update SYS_CLOCK_HW_CYCLES_PER_SEC in the MCX-W7xx SoC defconfig to
resolve the clock frequency from the chosen node path instead of the
lptmr0 nodelabel.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Set zephyr,system-timer = &lptmr1 in the i.MX95 DTSI /chosen node.
lptmr2 remains available for use by the counter driver. Both drivers
can be active simultaneously since they use separate hardware instances.
Default MCUX_LPTMR_TIMER to y in the i.MX95 SoC defconfig and resolve
SYS_CLOCK_HW_CYCLES_PER_SEC from the chosen node path instead of a
hard-coded node address.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Implementing the stm32wba power controller interface to manage
the ram retention in s2ram power state.
According the defined RAM, only the required pages will be retained.
This memory size can be modified by the overlay mechanism matching
the RAM required by the application and highlighted
in the building report.
Signed-off-by: Alessandro Manganaro <alessandro.manganaro@st.com>
Set CONFIG_CODE_DATA_RELOCATION for cm33 core so
that code that needs to be executed from RAM rather
than ext flash gets properly relocated
Additionally, ensure that the SRAM memory allows code
to be executed from it so set the MPU appropriately.
This aligns the strategy with the cm55 core for which all
this is already in place but does it by properly
setting the MPU regions from the start.
Signed-off-by: Laura Carlesso <laura.carlesso@infineon.com>
Add a more generic function `soc_radio_init` to enable additional
operations to be performed as part of radio init.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Disable debug support when powering off through the SoC STANDBY
state to prevent draining current.
When CONFIG_STM32_ENABLE_DEBUG_SLEEP_STOP is enabled, debug remains
powered in standby state which is expected when sleeping but not when
powering off.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Disable debug support when powering off through the SoC STANDBY
state to prevent draining current.
When CONFIG_STM32_ENABLE_DEBUG_SLEEP_STOP is enabled, debug remains
powered in standby state which is expected when sleeping but not when
powering off.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Disable debug support when powering off through the SoC STANDBY
state to prevent draining current.
When CONFIG_STM32_ENABLE_DEBUG_SLEEP_STOP is enabled, debug remains
powered in standby state which is expected when sleeping but not when
powering off.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
When the system clock operates at 96MHz, the core voltage must be
raised to 1.1V to ensure stability.
This fixes spurious resets occuring mainly during clock initialization.
Signed-off-by: Axel Le Bourhis <axel.lebourhis@nxp.com>
This adds the CC1312R SoC by Texas Instruments, this requires virtually
no changes since the cc13x2_c26x2 family of SoCs already implement
everything.
One thing not yet enabled is the IEEE 802.15.4g Sub-GHz
driver for this SoC because I can't download SmartRF Studio
due to access constraints from TI.
Signed-off-by: Jean-Pierre De Jesus DIAZ <me@jeandudey.tech>
