soc: renesas: ra: ra4m1: Migrate to FSP-based configuration

Change to use FSP to integrate with other Renesas RA series.

Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
This commit is contained in:
TOKITA Hiroshi 2024-08-03 21:00:04 +09:00 committed by Fabio Baltieri
commit c968d4eb81
10 changed files with 216 additions and 28 deletions

View file

@ -1,20 +0,0 @@
/*
* Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef ZEPHYR_SOC_ARM_RENESAS_RA_COMMON_RA_COMMON_SOC_H_
#define ZEPHYR_SOC_ARM_RENESAS_RA_COMMON_RA_COMMON_SOC_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <cmsis_core_m_defaults.h>
#ifdef __cplusplus
}
#endif
#endif /* ZEPHYR_SOC_ARM_RENESAS_RA_COMMON_RA_COMMON_SOC_H_ */

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@ -3,13 +3,16 @@
zephyr_include_directories(.)
zephyr_library_sources_ifdef(CONFIG_SOC_OPTION_SETTING_MEMORY
soc.c
)
zephyr_library_sources(soc.c)
zephyr_linker_sources_ifdef(CONFIG_SOC_OPTION_SETTING_MEMORY
ROM_START
${CMAKE_CURRENT_SOURCE_DIR}/opt_set_mem.ld
)
zephyr_linker_sources(SECTIONS sections.ld)
zephyr_linker_sources(DATA_SECTIONS data_sections.ld)
zephyr_linker_sources(RAM_SECTIONS ram_sections.ld)
zephyr_linker_sources(ROM_START rom_start.ld)
set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

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@ -5,10 +5,15 @@ config SOC_SERIES_RA4M1
select ARM
select CPU_CORTEX_M4
select CPU_HAS_ARM_MPU
select CPU_CORTEX_M_HAS_SYSTICK
select DYNAMIC_INTERRUPTS
select TIMER_READS_ITS_FREQUENCY_AT_RUNTIME
select HAS_RENESAS_RA_FSP
select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
select CPU_CORTEX_M_HAS_DWT
select CPU_HAS_FPU
select FPU
select HAS_SWO
select XIP
select SOC_EARLY_INIT_HOOK
select DYNAMIC_INTERRUPTS
if SOC_SERIES_RA4M1

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@ -5,7 +5,7 @@ config SOC_SERIES_RA4M1
bool
select SOC_FAMILY_RENESAS_RA
help
Renesas RA4M1
Renesas RA4M1 series
config SOC_R7FA4M1AB3CFM
bool

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@ -0,0 +1,13 @@
/*
* Copyright (c) 2024 TOKITA Hiroshi
*
* SPDX-License-Identifier: Apache-2.0
*/
.code_in_ram :
{
. = ALIGN(4);
__Code_In_RAM_Start = .;
KEEP(*(.code_in_ram*))
__Code_In_RAM_End = .;
} > RAMABLE_REGION

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@ -0,0 +1,12 @@
/*
* Copyright (c) 2024 TOKITA Hiroshi
*
* SPDX-License-Identifier: Apache-2.0
*/
SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
{
/* If DTC is used, put the DTC vector table at the start of SRAM.
This avoids memory holes due to 1K alignment required by it. */
*(.fsp_dtc_vector_table)
} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)

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@ -0,0 +1,11 @@
/*
* Copyright (c) 2024 TOKITA Hiroshi
*
* SPDX-License-Identifier: Apache-2.0
*/
/* ROM Registers start at address 0x00000400 */
. = 0x400;
KEEP(*(.rom_registers*))
/* Reserving 0x100 bytes of space for ROM registers. */
. = 0x500;

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@ -0,0 +1,116 @@
/*
* Copyright (c) 2024 TOKITA Hiroshi
*
* SPDX-License-Identifier: Apache-2.0
*/
#if DT_NODE_HAS_STATUS(DT_NODELABEL(id_code), okay)
SECTION_PROLOGUE(.id_code,,)
{
KEEP(*(.id_code*))
} GROUP_LINK_IN(ID_CODE)
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_ofs), okay)
SECTION_PROLOGUE(.option_setting_ofs,,)
{
__OPTION_SETTING_OFS_Start = .;
KEEP(*(.option_setting_ofs0))
. = __OPTION_SETTING_OFS_Start + 0x04;
KEEP(*(.option_setting_ofs2))
. = __OPTION_SETTING_OFS_Start + 0x10;
KEEP(*(.option_setting_dualsel))
__OPTION_SETTING_OFS_End = .;
} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_sas), okay)
SECTION_PROLOGUE(.option_setting_sas,,)
{
__OPTION_SETTING_SAS_Start = .;
KEEP(*(.option_setting_sas))
__OPTION_SETTING_SAS_End = .;
} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_ns), okay)
SECTION_PROLOGUE(.option_setting_ns,,)
{
__OPTION_SETTING_NS_Start = .;
KEEP(*(.option_setting_ofs1))
. = __OPTION_SETTING_NS_Start + 0x04;
KEEP(*(.option_setting_ofs3))
. = __OPTION_SETTING_NS_Start + 0x10;
KEEP(*(.option_setting_banksel))
. = __OPTION_SETTING_NS_Start + 0x40;
KEEP(*(.option_setting_bps0))
. = __OPTION_SETTING_NS_Start + 0x44;
KEEP(*(.option_setting_bps1))
. = __OPTION_SETTING_NS_Start + 0x48;
KEEP(*(.option_setting_bps2))
. = __OPTION_SETTING_NS_Start + 0x4C;
KEEP(*(.option_setting_bps3))
. = __OPTION_SETTING_NS_Start + 0x60;
KEEP(*(.option_setting_pbps0))
. = __OPTION_SETTING_NS_Start + 0x64;
KEEP(*(.option_setting_pbps1))
. = __OPTION_SETTING_NS_Start + 0x68;
KEEP(*(.option_setting_pbps2))
. = __OPTION_SETTING_NS_Start + 0x6C;
KEEP(*(.option_setting_pbps3))
__OPTION_SETTING_NS_End = .;
} GROUP_LINK_IN(OPTION_SETTING) = 0xFF
#endif
#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_s), okay)
SECTION_PROLOGUE(.option_setting_s,,)
{
__OPTION_SETTING_S_Start = .;
KEEP(*(.option_setting_ofs1_sec))
. = __OPTION_SETTING_S_Start + 0x04;
KEEP(*(.option_setting_ofs3_sec))
. = __OPTION_SETTING_S_Start + 0x10;
KEEP(*(.option_setting_banksel_sec))
. = __OPTION_SETTING_S_Start + 0x40;
KEEP(*(.option_setting_bps_sec0))
. = __OPTION_SETTING_S_Start + 0x44;
KEEP(*(.option_setting_bps_sec1))
. = __OPTION_SETTING_S_Start + 0x48;
KEEP(*(.option_setting_bps_sec2))
. = __OPTION_SETTING_S_Start + 0x4C;
KEEP(*(.option_setting_bps_sec3))
. = __OPTION_SETTING_S_Start + 0x60;
KEEP(*(.option_setting_pbps_sec0))
. = __OPTION_SETTING_S_Start + 0x64;
KEEP(*(.option_setting_pbps_sec1))
. = __OPTION_SETTING_S_Start + 0x68;
KEEP(*(.option_setting_pbps_sec2))
. = __OPTION_SETTING_S_Start + 0x6C;
KEEP(*(.option_setting_pbps_sec3))
. = __OPTION_SETTING_S_Start + 0x80;
KEEP(*(.option_setting_ofs1_sel))
. = __OPTION_SETTING_S_Start + 0x84;
KEEP(*(.option_setting_ofs3_sel))
. = __OPTION_SETTING_S_Start + 0x90;
KEEP(*(.option_setting_banksel_sel))
. = __OPTION_SETTING_S_Start + 0xC0;
KEEP(*(.option_setting_bps_sel0))
. = __OPTION_SETTING_S_Start + 0xC4;
KEEP(*(.option_setting_bps_sel1))
. = __OPTION_SETTING_S_Start + 0xC8;
KEEP(*(.option_setting_bps_sel2))
. = __OPTION_SETTING_S_Start + 0xCC;
KEEP(*(.option_setting_bps_sel3))
__OPTION_SETTING_S_End = .;
} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF
#endif

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@ -1,9 +1,27 @@
/*
* Copyright (c) 2024 Ian Morris
* Copyright (c) 2024 TOKITA Hiroshi
*
* SPDX-License-Identifier: Apache-2.0
*/
/**
* @file
* @brief System/hardware module for Renesas RA4M1 family processor
*/
#include <zephyr/device.h>
#include <zephyr/init.h>
#include <zephyr/kernel.h>
#include <zephyr/arch/cpu.h>
#include <cmsis_core.h>
#include <zephyr/arch/arm/nmi.h>
#include <zephyr/irq.h>
#include <zephyr/logging/log.h>
LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
#include "bsp_cfg.h"
#include <bsp_api.h>
#define HOCO_FREQ DT_PROP(DT_PATH(clocks, hoco), clock_frequency)
@ -134,3 +152,24 @@ const struct opt_set_mem ops __attribute__((section(".opt_set_mem"))) = {
}
};
#endif
uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
/**
* @brief Perform basic hardware initialization at boot.
*
* This needs to be run from the very beginning.
*/
void soc_early_init_hook(void)
{
uint32_t key;
key = irq_lock();
SystemCoreClock = BSP_MOCO_HZ;
g_protect_pfswe_counter = 0;
irq_unlock(key);
}

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@ -4,4 +4,13 @@
* SPDX-License-Identifier: Apache-2.0
*/
#include "../common/ra_common_soc.h"
/**
* @file SoC configuration macros for the Renesas RA4M1 family MCU
*/
#ifndef ZEPHYR_SOC_RENESAS_RA4M1_SOC_H_
#define ZEPHYR_SOC_RENESAS_RA4M1_SOC_H_
#include <bsp_api.h>
#endif /* ZEPHYR_SOC_RENESAS_RA4M1_SOC_H_ */