soc: renesas: ra: ra4m1: Migrate to FSP-based configuration
Change to use FSP to integrate with other Renesas RA series. Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
This commit is contained in:
TOKITA Hiroshi
Fabio Baltieri
parent
3364a35f05
commit
c968d4eb81
10 changed files with 216 additions and 28 deletions
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@ -1,20 +0,0 @@
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/*
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* Copyright (c) 2023 TOKITA Hiroshi <tokita.hiroshi@fujitsu.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_SOC_ARM_RENESAS_RA_COMMON_RA_COMMON_SOC_H_
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#define ZEPHYR_SOC_ARM_RENESAS_RA_COMMON_RA_COMMON_SOC_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <cmsis_core_m_defaults.h>
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#ifdef __cplusplus
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}
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#endif
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#endif /* ZEPHYR_SOC_ARM_RENESAS_RA_COMMON_RA_COMMON_SOC_H_ */
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@ -3,13 +3,16 @@
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zephyr_include_directories(.)
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zephyr_library_sources_ifdef(CONFIG_SOC_OPTION_SETTING_MEMORY
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soc.c
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)
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zephyr_library_sources(soc.c)
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zephyr_linker_sources_ifdef(CONFIG_SOC_OPTION_SETTING_MEMORY
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ROM_START
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${CMAKE_CURRENT_SOURCE_DIR}/opt_set_mem.ld
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)
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zephyr_linker_sources(SECTIONS sections.ld)
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zephyr_linker_sources(DATA_SECTIONS data_sections.ld)
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zephyr_linker_sources(RAM_SECTIONS ram_sections.ld)
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zephyr_linker_sources(ROM_START rom_start.ld)
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
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@ -5,10 +5,15 @@ config SOC_SERIES_RA4M1
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select ARM
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select CPU_CORTEX_M4
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select CPU_HAS_ARM_MPU
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select CPU_CORTEX_M_HAS_SYSTICK
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select DYNAMIC_INTERRUPTS
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select TIMER_READS_ITS_FREQUENCY_AT_RUNTIME
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select HAS_RENESAS_RA_FSP
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select CLOCK_CONTROL_RENESAS_RA_CGC if CLOCK_CONTROL
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select CPU_CORTEX_M_HAS_DWT
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select CPU_HAS_FPU
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select FPU
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select HAS_SWO
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select XIP
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select SOC_EARLY_INIT_HOOK
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select DYNAMIC_INTERRUPTS
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if SOC_SERIES_RA4M1
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@ -5,7 +5,7 @@ config SOC_SERIES_RA4M1
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bool
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select SOC_FAMILY_RENESAS_RA
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help
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Renesas RA4M1
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Renesas RA4M1 series
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config SOC_R7FA4M1AB3CFM
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bool
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13
soc/renesas/ra/ra4m1/data_sections.ld
Normal file
13
soc/renesas/ra/ra4m1/data_sections.ld
Normal file
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@ -0,0 +1,13 @@
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/*
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* Copyright (c) 2024 TOKITA Hiroshi
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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.code_in_ram :
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{
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. = ALIGN(4);
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__Code_In_RAM_Start = .;
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KEEP(*(.code_in_ram*))
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__Code_In_RAM_End = .;
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} > RAMABLE_REGION
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12
soc/renesas/ra/ra4m1/ram_sections.ld
Normal file
12
soc/renesas/ra/ra4m1/ram_sections.ld
Normal file
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@ -0,0 +1,12 @@
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/*
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* Copyright (c) 2024 TOKITA Hiroshi
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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SECTION_DATA_PROLOGUE(.fsp_dtc_vector_table,(NOLOAD),)
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{
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/* If DTC is used, put the DTC vector table at the start of SRAM.
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This avoids memory holes due to 1K alignment required by it. */
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*(.fsp_dtc_vector_table)
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} GROUP_DATA_LINK_IN(RAMABLE_REGION, RAMABLE_REGION)
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11
soc/renesas/ra/ra4m1/rom_start.ld
Normal file
11
soc/renesas/ra/ra4m1/rom_start.ld
Normal file
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@ -0,0 +1,11 @@
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/*
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* Copyright (c) 2024 TOKITA Hiroshi
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/* ROM Registers start at address 0x00000400 */
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. = 0x400;
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KEEP(*(.rom_registers*))
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/* Reserving 0x100 bytes of space for ROM registers. */
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. = 0x500;
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116
soc/renesas/ra/ra4m1/sections.ld
Normal file
116
soc/renesas/ra/ra4m1/sections.ld
Normal file
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@ -0,0 +1,116 @@
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/*
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* Copyright (c) 2024 TOKITA Hiroshi
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(id_code), okay)
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SECTION_PROLOGUE(.id_code,,)
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{
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KEEP(*(.id_code*))
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} GROUP_LINK_IN(ID_CODE)
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_ofs), okay)
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SECTION_PROLOGUE(.option_setting_ofs,,)
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{
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__OPTION_SETTING_OFS_Start = .;
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KEEP(*(.option_setting_ofs0))
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. = __OPTION_SETTING_OFS_Start + 0x04;
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KEEP(*(.option_setting_ofs2))
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. = __OPTION_SETTING_OFS_Start + 0x10;
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KEEP(*(.option_setting_dualsel))
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__OPTION_SETTING_OFS_End = .;
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} GROUP_LINK_IN(OPTION_SETTING_OFS) = 0xFF
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_sas), okay)
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SECTION_PROLOGUE(.option_setting_sas,,)
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{
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__OPTION_SETTING_SAS_Start = .;
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KEEP(*(.option_setting_sas))
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__OPTION_SETTING_SAS_End = .;
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} GROUP_LINK_IN(OPTION_SETTING_SAS) = 0xFF
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_ns), okay)
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SECTION_PROLOGUE(.option_setting_ns,,)
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{
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__OPTION_SETTING_NS_Start = .;
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KEEP(*(.option_setting_ofs1))
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. = __OPTION_SETTING_NS_Start + 0x04;
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KEEP(*(.option_setting_ofs3))
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. = __OPTION_SETTING_NS_Start + 0x10;
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KEEP(*(.option_setting_banksel))
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. = __OPTION_SETTING_NS_Start + 0x40;
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KEEP(*(.option_setting_bps0))
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. = __OPTION_SETTING_NS_Start + 0x44;
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KEEP(*(.option_setting_bps1))
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. = __OPTION_SETTING_NS_Start + 0x48;
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KEEP(*(.option_setting_bps2))
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. = __OPTION_SETTING_NS_Start + 0x4C;
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KEEP(*(.option_setting_bps3))
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. = __OPTION_SETTING_NS_Start + 0x60;
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KEEP(*(.option_setting_pbps0))
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. = __OPTION_SETTING_NS_Start + 0x64;
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KEEP(*(.option_setting_pbps1))
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. = __OPTION_SETTING_NS_Start + 0x68;
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KEEP(*(.option_setting_pbps2))
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. = __OPTION_SETTING_NS_Start + 0x6C;
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KEEP(*(.option_setting_pbps3))
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__OPTION_SETTING_NS_End = .;
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} GROUP_LINK_IN(OPTION_SETTING) = 0xFF
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(option_setting_s), okay)
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SECTION_PROLOGUE(.option_setting_s,,)
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{
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__OPTION_SETTING_S_Start = .;
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KEEP(*(.option_setting_ofs1_sec))
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. = __OPTION_SETTING_S_Start + 0x04;
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KEEP(*(.option_setting_ofs3_sec))
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. = __OPTION_SETTING_S_Start + 0x10;
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KEEP(*(.option_setting_banksel_sec))
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. = __OPTION_SETTING_S_Start + 0x40;
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KEEP(*(.option_setting_bps_sec0))
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. = __OPTION_SETTING_S_Start + 0x44;
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KEEP(*(.option_setting_bps_sec1))
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. = __OPTION_SETTING_S_Start + 0x48;
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KEEP(*(.option_setting_bps_sec2))
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. = __OPTION_SETTING_S_Start + 0x4C;
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KEEP(*(.option_setting_bps_sec3))
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. = __OPTION_SETTING_S_Start + 0x60;
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KEEP(*(.option_setting_pbps_sec0))
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. = __OPTION_SETTING_S_Start + 0x64;
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KEEP(*(.option_setting_pbps_sec1))
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. = __OPTION_SETTING_S_Start + 0x68;
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KEEP(*(.option_setting_pbps_sec2))
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. = __OPTION_SETTING_S_Start + 0x6C;
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KEEP(*(.option_setting_pbps_sec3))
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. = __OPTION_SETTING_S_Start + 0x80;
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KEEP(*(.option_setting_ofs1_sel))
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. = __OPTION_SETTING_S_Start + 0x84;
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KEEP(*(.option_setting_ofs3_sel))
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. = __OPTION_SETTING_S_Start + 0x90;
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KEEP(*(.option_setting_banksel_sel))
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. = __OPTION_SETTING_S_Start + 0xC0;
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KEEP(*(.option_setting_bps_sel0))
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. = __OPTION_SETTING_S_Start + 0xC4;
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KEEP(*(.option_setting_bps_sel1))
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. = __OPTION_SETTING_S_Start + 0xC8;
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KEEP(*(.option_setting_bps_sel2))
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. = __OPTION_SETTING_S_Start + 0xCC;
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KEEP(*(.option_setting_bps_sel3))
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__OPTION_SETTING_S_End = .;
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} GROUP_LINK_IN(OPTION_SETTING_S) = 0xFF
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#endif
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@ -1,9 +1,27 @@
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/*
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* Copyright (c) 2024 Ian Morris
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* Copyright (c) 2024 TOKITA Hiroshi
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for Renesas RA4M1 family processor
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*/
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <zephyr/kernel.h>
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#include <zephyr/arch/cpu.h>
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#include <cmsis_core.h>
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#include <zephyr/arch/arm/nmi.h>
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#include <zephyr/irq.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(soc, CONFIG_SOC_LOG_LEVEL);
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#include "bsp_cfg.h"
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#include <bsp_api.h>
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#define HOCO_FREQ DT_PROP(DT_PATH(clocks, hoco), clock_frequency)
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@ -134,3 +152,24 @@ const struct opt_set_mem ops __attribute__((section(".opt_set_mem"))) = {
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}
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};
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#endif
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uint32_t SystemCoreClock BSP_SECTION_EARLY_INIT;
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volatile uint32_t g_protect_pfswe_counter BSP_SECTION_EARLY_INIT;
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/**
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* @brief Perform basic hardware initialization at boot.
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*
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* This needs to be run from the very beginning.
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*/
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void soc_early_init_hook(void)
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{
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uint32_t key;
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key = irq_lock();
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SystemCoreClock = BSP_MOCO_HZ;
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g_protect_pfswe_counter = 0;
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irq_unlock(key);
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}
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@ -4,4 +4,13 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "../common/ra_common_soc.h"
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/**
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* @file SoC configuration macros for the Renesas RA4M1 family MCU
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*/
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#ifndef ZEPHYR_SOC_RENESAS_RA4M1_SOC_H_
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#define ZEPHYR_SOC_RENESAS_RA4M1_SOC_H_
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#include <bsp_api.h>
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#endif /* ZEPHYR_SOC_RENESAS_RA4M1_SOC_H_ */
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