arch: riscv: introduce CONFIG_RISCV_GP_PURPOSE choice

Introduce `CONFIG_RISCV_GP_PURPOSE` choice to make sure that only one of `CONFIG_RISCV_GP` or `CONFIG_RISCV_CURRENT_VIA_GP` can be enabled, instead of relying of dependencies. To do that, introduce a new `CONFIG_RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING` that can be selected by SoC when it implemented global pointer (GP) initialization for relative addressing in its linker. `CONFIG_RISCV_GP` will be the default choice when `CONFIG_RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING=y` Signed-off-by: Yong Cong Sin <ycsin@meta.com> Signed-off-by: Yong Cong Sin <yongcong.sin@gmail.com>
2024-11-25 12:54:01 +08:00 · 2024-11-25 12:54:01 +08:00 · e6dd68ec89
commit e6dd68ec89
parent 033804e266
37 changed files with 33 additions and 56 deletions
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@ -16,9 +16,13 @@ config FLOAT_HARD
 	help
 	  This option enables the hard-float calling convention.

+choice RISCV_GP_PURPOSE
+	prompt "Purpose of the global pointer (GP) register"
+	default RISCV_GP if RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
+
 config RISCV_GP
 	bool "RISC-V global pointer relative addressing"
-	default n
+	depends on RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
 	help
 	  Use global pointer relative addressing for small globals declared
 	  anywhere in the executable. It can benefit performance and reduce
@ -30,7 +34,6 @@ config RISCV_GP

 config RISCV_CURRENT_VIA_GP
 	bool "Store current thread into the global pointer (GP) register"
-	depends on !RISCV_GP
 	depends on MP_MAX_NUM_CPUS > 1
 	select ARCH_HAS_CUSTOM_CURRENT_IMPL
 	help
@ -38,6 +41,8 @@ config RISCV_CURRENT_VIA_GP
 	  When is enabled, calls to `arch_current_thread()` & `k_sched_current_thread_query()` will
 	  be reduced to a single register read.

+endchoice # RISCV_GP_PURPOSE
+
 config RISCV_ALWAYS_SWITCH_THROUGH_ECALL
 	bool "Do not use mret outside a trap handler context"
 	depends on MULTITHREADING
@ -148,6 +153,12 @@ config RISCV_SOC_HAS_CUSTOM_SYS_IO
 	  the RISC-V SoC needs to do something different and more than reading and
 	  writing the registers.

+config RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
+	bool
+	help
+	  Selected when SoC has implemented the initialization of global pointer (GP)
+	  at program start, or earlier than any instruction using GP relative addressing.
+
 config RISCV_SOC_CONTEXT_SAVE
 	bool "SOC-based context saving in IRQ handlers"
 	select RISCV_SOC_OFFSETS
--- a/soc/andestech/ae350/Kconfig
+++ b/soc/andestech/ae350/Kconfig
@ -5,6 +5,7 @@ config SOC_SERIES_ANDES_AE350
 	select RISCV
 	select RISCV_PRIVILEGED
 	select RISCV_HAS_PLIC
+	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
 	imply XIP

 config SOC_ANDES_AE350
--- a/soc/andestech/ae350/Kconfig.defconfig
+++ b/soc/andestech/ae350/Kconfig.defconfig
@ -21,9 +21,6 @@ config RISCV_GENERIC_TOOLCHAIN
 config RISCV_SOC_INTERRUPT_INIT
 	default y

-config RISCV_GP
-	default y
-
 config 2ND_LVL_ISR_TBL_OFFSET
 	default 12

--- a/soc/espressif/esp32c2/Kconfig
+++ b/soc/espressif/esp32c2/Kconfig
@ -3,7 +3,7 @@

 config SOC_SERIES_ESP32C2
 	select RISCV
-	select RISCV_GP
+	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
 	select DYNAMIC_INTERRUPTS
 	select CLOCK_CONTROL
 	select PINCTRL
--- a/soc/espressif/esp32c3/Kconfig
+++ b/soc/espressif/esp32c3/Kconfig
@ -3,7 +3,7 @@

 config SOC_SERIES_ESP32C3
 	select RISCV
-	select RISCV_GP
+	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
 	select DYNAMIC_INTERRUPTS
 	select CLOCK_CONTROL
 	select PINCTRL
--- a/soc/espressif/esp32c6/Kconfig
+++ b/soc/espressif/esp32c6/Kconfig
@ -3,7 +3,7 @@

 config SOC_SERIES_ESP32C6
 	select RISCV
-	select RISCV_GP
+	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
 	select DYNAMIC_INTERRUPTS
 	select CLOCK_CONTROL
 	select PINCTRL
--- a/soc/gd/gd32/gd32vf103/Kconfig
+++ b/soc/gd/gd32/gd32vf103/Kconfig
@ -13,6 +13,7 @@ config SOC_SERIES_GD32VF103
 	select RISCV_ISA_EXT_ZICSR
 	select RISCV_ISA_EXT_ZIFENCEI
 	select RISCV_HAS_CLIC
+	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
 	select ATOMIC_OPERATIONS_C
 	select INCLUDE_RESET_VECTOR
 	select GD32_HAS_AFIO_PINMUX
--- a/soc/gd/gd32/gd32vf103/Kconfig.defconfig.gd32vf103
+++ b/soc/gd/gd32/gd32vf103/Kconfig.defconfig.gd32vf103
@ -17,9 +17,6 @@ config RISCV_MCAUSE_EXCEPTION_MASK
 config RISCV_SOC_INTERRUPT_INIT
 	default y

-config RISCV_GP
-	default y
-
 config NUM_IRQS
 	default 87 if  NUCLEI_ECLIC
 	default 16 if !NUCLEI_ECLIC
--- a/soc/intel/intel_niosv/niosv/Kconfig
+++ b/soc/intel/intel_niosv/niosv/Kconfig
@ -11,6 +11,7 @@ config SOC_SERIES_NIOSV
 	select RISCV_ISA_EXT_A
 	select RISCV_ISA_EXT_ZICSR
 	select RISCV_ISA_EXT_ZIFENCEI
+	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
 	imply XIP

 config SOC_NIOSV_M
--- a/soc/intel/intel_niosv/niosv/Kconfig.defconfig.series
+++ b/soc/intel/intel_niosv/niosv/Kconfig.defconfig.series
@ -10,9 +10,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 config NUM_IRQS # Platform interrupts IRQs index start from index 16
 	default 32

-config RISCV_GP
-	default y
-
 config RISCV_SOC_INTERRUPT_INIT
 	default y

--- a/soc/ite/ec/it8xxx2/Kconfig
+++ b/soc/ite/ec/it8xxx2/Kconfig
@ -6,6 +6,7 @@ config SOC_SERIES_IT8XXX2
 	select HAS_PM
 	select ARCH_HAS_CUSTOM_CPU_IDLE
 	select ARCH_HAS_CUSTOM_CPU_ATOMIC_IDLE
+	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING

 if SOC_SERIES_IT8XXX2

--- a/soc/ite/ec/it8xxx2/Kconfig.defconfig.series
+++ b/soc/ite/ec/it8xxx2/Kconfig.defconfig.series
@ -3,9 +3,6 @@

 if SOC_SERIES_IT8XXX2

-config RISCV_GP
-	default y
-
 config ARCH_HAS_CUSTOM_BUSY_WAIT
 	default y

--- a/soc/lowrisc/opentitan/Kconfig
+++ b/soc/lowrisc/opentitan/Kconfig
@ -16,6 +16,7 @@ config SOC_OPENTITAN
 	select RISCV
 	select RISCV_PRIVILEGED
 	select RISCV_HAS_PLIC
+	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
 	# OpenTitan Ibex core mtvec mode is read-only / forced to vectored mode.
 	select RISCV_VECTORED_MODE
 	select GEN_IRQ_VECTOR_TABLE
--- a/soc/lowrisc/opentitan/Kconfig.defconfig
+++ b/soc/lowrisc/opentitan/Kconfig.defconfig
@ -9,9 +9,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 config RISCV_SOC_INTERRUPT_INIT
 	default y

-config RISCV_GP
-	default y
-
 config 2ND_LVL_ISR_TBL_OFFSET
 	default 32

--- a/soc/microchip/miv/miv/Kconfig
+++ b/soc/microchip/miv/miv/Kconfig
@ -7,6 +7,7 @@ config SOC_SERIES_MIV
 	select RISCV
 	select RISCV_PRIVILEGED
 	select RISCV_HAS_PLIC
+	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
 	imply XIP

 config SOC_MIV
--- a/soc/microchip/miv/miv/Kconfig.defconfig
+++ b/soc/microchip/miv/miv/Kconfig.defconfig
@ -9,9 +9,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 config RISCV_SOC_INTERRUPT_INIT
 	default y

-config RISCV_GP
-	default y
-
 config 2ND_LVL_ISR_TBL_OFFSET
 	default 12

--- a/soc/microchip/miv/polarfire/Kconfig
+++ b/soc/microchip/miv/polarfire/Kconfig
@ -7,13 +7,14 @@ config SOC_SERIES_POLARFIRE
 	select RISCV
 	select RISCV_PRIVILEGED
 	select RISCV_HAS_PLIC
+	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
 	imply XIP

 config SOC_POLARFIRE
 	select 64BIT
 	select SCHED_IPI_SUPPORTED
 	select ATOMIC_OPERATIONS_BUILTIN
-	select RISCV_GP
+	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
 	select USE_SWITCH_SUPPORTED
 	select USE_SWITCH

--- a/soc/microchip/miv/polarfire/Kconfig.defconfig
+++ b/soc/microchip/miv/polarfire/Kconfig.defconfig
@ -13,9 +13,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 config RISCV_SOC_INTERRUPT_INIT
 	default y

-config RISCV_GP
-	default y
-
 config 2ND_LVL_ISR_TBL_OFFSET
 	default 13

--- a/soc/neorv32/Kconfig
+++ b/soc/neorv32/Kconfig
@ -9,6 +9,7 @@ config SOC_NEORV32
 	select RISCV_ISA_EXT_ZICSR
 	select RISCV_ISA_EXT_ZIFENCEI
 	select RISCV_PRIVILEGED
+	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
 	imply XIP

 if SOC_NEORV32
--- a/soc/neorv32/Kconfig.defconfig
+++ b/soc/neorv32/Kconfig.defconfig
@ -9,9 +9,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 config NUM_IRQS
 	default 32

-config RISCV_GP
-	default y
-
 config SYSCON
 	default y

--- a/soc/qemu/virt_riscv/Kconfig
+++ b/soc/qemu/virt_riscv/Kconfig
@ -10,6 +10,7 @@ config SOC_FAMILY_QEMU_VIRT_RISCV
 	select RISCV
 	select RISCV_PRIVILEGED
 	select RISCV_HAS_PLIC
+	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
 	imply XIP

 if SOC_FAMILY_QEMU_VIRT_RISCV
--- a/soc/qemu/virt_riscv/Kconfig.defconfig
+++ b/soc/qemu/virt_riscv/Kconfig.defconfig
@ -10,9 +10,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 config RISCV_SOC_INTERRUPT_INIT
 	default y

-config RISCV_GP
-	default y
-
 config 2ND_LVL_ISR_TBL_OFFSET
 	default 12

--- a/soc/renode/riscv_virtual/Kconfig
+++ b/soc/renode/riscv_virtual/Kconfig
@ -13,4 +13,5 @@ config SOC_RISCV_VIRTUAL_RENODE
 	select RISCV_ISA_EXT_ZICSR
 	select RISCV_ISA_EXT_ZIFENCEI
 	select RISCV_HAS_PLIC
+	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
 	imply XIP
--- a/soc/renode/riscv_virtual/Kconfig.defconfig
+++ b/soc/renode/riscv_virtual/Kconfig.defconfig
@ -9,9 +9,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 config RISCV_SOC_INTERRUPT_INIT
 	default y

-config RISCV_GP
-	default y
-
 config 1ST_LEVEL_INTERRUPT_BITS
 	default 4

--- a/soc/sifive/sifive_freedom/fe300/Kconfig
+++ b/soc/sifive/sifive_freedom/fe300/Kconfig
@ -10,6 +10,7 @@ config SOC_SERIES_SIFIVE_FREEDOM_FE300
 	select RISCV_PRIVILEGED
 	select RISCV_HAS_PLIC
 	select RISCV_PMP
+	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING

 	select RISCV_ISA_RV32I
 	select RISCV_ISA_EXT_M
--- a/soc/sifive/sifive_freedom/fe300/Kconfig.defconfig
+++ b/soc/sifive/sifive_freedom/fe300/Kconfig.defconfig
@ -10,9 +10,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 config RISCV_SOC_INTERRUPT_INIT
 	default y

-config RISCV_GP
-	default y
-
 config 2ND_LVL_ISR_TBL_OFFSET
 	default 12

--- a/soc/sifive/sifive_freedom/fu500/Kconfig
+++ b/soc/sifive/sifive_freedom/fu500/Kconfig
@ -12,6 +12,7 @@ config SOC_SERIES_SIFIVE_FREEDOM_FU500
 	select RISCV_PRIVILEGED
 	select RISCV_HAS_PLIC
 	select RISCV_PMP
+	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING

 	select RISCV_ISA_RV64I
 	select RISCV_ISA_EXT_M
--- a/soc/sifive/sifive_freedom/fu500/Kconfig.defconfig
+++ b/soc/sifive/sifive_freedom/fu500/Kconfig.defconfig
@ -10,9 +10,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 config RISCV_SOC_INTERRUPT_INIT
 	default y

-config RISCV_GP
-	default y
-
 config 2ND_LVL_ISR_TBL_OFFSET
 	default 12

--- a/soc/sifive/sifive_freedom/fu700/Kconfig
+++ b/soc/sifive/sifive_freedom/fu700/Kconfig
@ -11,6 +11,7 @@ config SOC_SERIES_SIFIVE_FREEDOM_FU700
 	select RISCV_PRIVILEGED
 	select RISCV_HAS_PLIC
 	select RISCV_PMP
+	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING

 	select RISCV_ISA_RV64I
 	select RISCV_ISA_EXT_M
--- a/soc/sifive/sifive_freedom/fu700/Kconfig.defconfig
+++ b/soc/sifive/sifive_freedom/fu700/Kconfig.defconfig
@ -10,9 +10,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 config RISCV_SOC_INTERRUPT_INIT
 	default y

-config RISCV_GP
-	default y
-
 config 2ND_LVL_ISR_TBL_OFFSET
 	default 12

--- a/soc/snps/nsim/arc_v/rmx/Kconfig
+++ b/soc/snps/nsim/arc_v/rmx/Kconfig
@ -12,6 +12,7 @@ config SOC_SERIES_RMX
 	select RISCV_ISA_EXT_C
 	select RISCV_ISA_EXT_ZICSR
 	select RISCV_ISA_EXT_ZIFENCEI
+	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
 	select INCLUDE_RESET_VECTOR
 	select ATOMIC_OPERATIONS_BUILTIN
 	imply XIP
--- a/soc/snps/nsim/arc_v/rmx/Kconfig.defconfig
+++ b/soc/snps/nsim/arc_v/rmx/Kconfig.defconfig
@ -6,9 +6,6 @@ if SOC_SERIES_RMX
 config RISCV_SOC_INTERRUPT_INIT
 	default y

-config RISCV_GP
-	default y
-
 config MULTI_LEVEL_INTERRUPTS
 	default n

--- a/soc/starfive/jh71xx/Kconfig
+++ b/soc/starfive/jh71xx/Kconfig
@ -5,6 +5,7 @@ config SOC_SERIES_STARFIVE_JH71XX
 	select RISCV
 	select RISCV_PRIVILEGED
 	select RISCV_HAS_PLIC
+	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
 	imply XIP

 config SOC_JH7100
--- a/soc/starfive/jh71xx/Kconfig.defconfig
+++ b/soc/starfive/jh71xx/Kconfig.defconfig
@ -9,9 +9,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 config RISCV_SOC_INTERRUPT_INIT
 	default y

-config RISCV_GP
-	default y
-
 config 2ND_LVL_ISR_TBL_OFFSET
 	default 12

--- a/soc/telink/tlsr/tlsr951x/Kconfig
+++ b/soc/telink/tlsr/tlsr951x/Kconfig
@ -12,6 +12,7 @@ config SOC_SERIES_TLSR951X
 	select RISCV_ISA_EXT_ZIFENCEI
 	select RISCV_PRIVILEGED
 	select RISCV_HAS_PLIC
+	select RISCV_SOC_HAS_GP_RELATIVE_ADDRESSING
 	select HAS_TELINK_DRIVERS
 	select ATOMIC_OPERATIONS_BUILTIN
 	select CPU_HAS_FPU
--- a/soc/telink/tlsr/tlsr951x/Kconfig.defconfig
+++ b/soc/telink/tlsr/tlsr951x/Kconfig.defconfig
@ -9,9 +9,6 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 config RISCV_SOC_INTERRUPT_INIT
 	default y

-config RISCV_GP
-	default y
-
 config NUM_IRQS
 	default 64

--- a/tests/arch/riscv/userspace/riscv_gp/testcase.yaml
+++ b/tests/arch/riscv/userspace/riscv_gp/testcase.yaml
@ -8,8 +8,6 @@ tests:
  arch.riscv64.riscv_gp.relative_addressing:
    extra_configs:
      - CONFIG_RISCV_GP=y
-      - CONFIG_RISCV_CURRENT_VIA_GP=n
  arch.riscv64.riscv_gp.thread_pointer:
    extra_configs:
      - CONFIG_RISCV_CURRENT_VIA_GP=y
-      - CONFIG_RISCV_GP=n