drivers: add ch32v00x pinctrl support
This commit adds the pinctrl driver for WCH CH32V003. Signed-off-by: Michael Hope <michaelh@juju.nz> Signed-off-by: Dhiru Kholia <dhiru.kholia@gmail.com>
This commit is contained in:
Fabio Baltieri
parent
936c78e8ba
commit
6d3348bd83
7 changed files with 316 additions and 0 deletions
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@ -40,5 +40,6 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_IMX_SCU pinctrl_imx_scu.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_MAX32 pinctrl_max32.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_IMX_SCMI pinctrl_imx_scmi.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_MCHP_MEC5 pinctrl_mchp_mec5.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_WCH_AFIO pinctrl_wch_afio.c)
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add_subdirectory(renesas)
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@ -67,6 +67,7 @@ source "drivers/pinctrl/Kconfig.ene"
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source "drivers/pinctrl/Kconfig.zynqmp"
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source "drivers/pinctrl/Kconfig.max32"
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source "drivers/pinctrl/Kconfig.mec5"
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source "drivers/pinctrl/Kconfig.wch_afio"
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rsource "renesas/Kconfig"
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9
drivers/pinctrl/Kconfig.wch_afio
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9
drivers/pinctrl/Kconfig.wch_afio
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@ -0,0 +1,9 @@
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# Copyright (c) 2024 Michael Hope
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# SPDX-License-Identifier: Apache-2.0
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config PINCTRL_WCH_AFIO
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bool "WCH AFIO pin controller driver"
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default y
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depends on DT_HAS_WCH_AFIO_ENABLED
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help
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WCH AFIO pin controller driver.
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75
drivers/pinctrl/pinctrl_wch_afio.c
Normal file
75
drivers/pinctrl/pinctrl_wch_afio.c
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@ -0,0 +1,75 @@
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/*
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* Copyright (c) 2024 Michael Hope
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/dt-bindings/pinctrl/ch32v003-pinctrl.h>
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#include <ch32fun.h>
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static GPIO_TypeDef *const wch_afio_pinctrl_regs[] = {
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(GPIO_TypeDef *)DT_REG_ADDR(DT_NODELABEL(gpioa)),
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(GPIO_TypeDef *)DT_REG_ADDR(DT_NODELABEL(gpioc)),
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(GPIO_TypeDef *)DT_REG_ADDR(DT_NODELABEL(gpiod)),
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};
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
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{
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int i;
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for (i = 0; i < pin_cnt; i++, pins++) {
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uint8_t port = (pins->config >> CH32V003_PINCTRL_PORT_SHIFT) & 0x03;
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uint8_t pin = (pins->config >> CH32V003_PINCTRL_PIN_SHIFT) & 0x0F;
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uint8_t bit0 = (pins->config >> CH32V003_PINCTRL_RM_BASE_SHIFT) & 0x1F;
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uint8_t remap = (pins->config >> CH32V003_PINCTRL_RM_SHIFT) & 0x3;
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GPIO_TypeDef *regs = wch_afio_pinctrl_regs[port];
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uint32_t pcfr1 = AFIO->PCFR1;
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uint8_t cfg = 0;
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if (pins->output_high || pins->output_low) {
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cfg |= (pins->slew_rate + 1);
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if (pins->drive_open_drain) {
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cfg |= BIT(2);
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}
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/* Select the alternate function */
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cfg |= BIT(3);
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} else {
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if (pins->bias_pull_up || pins->bias_pull_down) {
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cfg |= BIT(3);
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}
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}
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regs->CFGLR = (regs->CFGLR & ~(0x0F << (pin * 4))) | (cfg << (pin * 4));
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if (pins->output_high) {
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regs->OUTDR |= BIT(pin);
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regs->BSHR |= BIT(pin);
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} else if (pins->output_low) {
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regs->OUTDR |= BIT(pin);
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/* Reset the pin. */
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regs->BSHR |= BIT(pin + 16);
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} else {
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regs->OUTDR &= ~(1 << pin);
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if (pins->bias_pull_up) {
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regs->BSHR = BIT(pin);
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}
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if (pins->bias_pull_down) {
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regs->BCR = BIT(pin);
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}
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}
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if (bit0 == CH32V003_PINMUX_I2C1_RM) {
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pcfr1 |= ((remap & 1) << CH32V003_PINMUX_I2C1_RM) |
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(((remap >> 1) & 1) << CH32V003_PINMUX_I2C1_RM1);
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} else if (bit0 == CH32V003_PINMUX_USART1_RM) {
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pcfr1 |= ((remap & 1) << CH32V003_PINMUX_USART1_RM) |
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(((remap >> 1) & 1) << CH32V003_PINMUX_USART1_RM1);
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} else {
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pcfr1 |= remap << bit0;
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}
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AFIO->PCFR1 = pcfr1;
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}
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return 0;
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}
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52
dts/bindings/pinctrl/wch,afio.yaml
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52
dts/bindings/pinctrl/wch,afio.yaml
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@ -0,0 +1,52 @@
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# Copyright (c) 2024 Michael Hope
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# SPDX-License-Identifier: Apache-2.0
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description: WCH CH32V00x AFIO
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compatible: "wch,afio"
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include: base.yaml
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properties:
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reg:
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required: true
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"#address-cells":
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required: true
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const: 1
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"#size-cells":
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required: true
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const: 1
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child-binding:
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description: |
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Each child node defines the configuration for a particular state.
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child-binding:
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description: |
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The grandchild nodes group pins that share the same pin configuration.
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include:
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- name: pincfg-node.yaml
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property-allowlist:
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- bias-high-impedance
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- bias-pull-up
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- bias-pull-down
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- drive-open-drain
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- drive-push-pull
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- output-high
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- output-low
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properties:
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slew-rate:
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type: string
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default: "max-speed-2mhz"
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enum:
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- "max-speed-10mhz"
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- "max-speed-2mhz"
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- "max-speed-30mhz"
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pinmux:
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required: true
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type: array
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description: |
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An array of pins sharing the same group properties. The pins should
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be defined using pre-defined macros.
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136
include/zephyr/dt-bindings/pinctrl/ch32v003-pinctrl.h
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136
include/zephyr/dt-bindings/pinctrl/ch32v003-pinctrl.h
Normal file
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@ -0,0 +1,136 @@
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/*
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* Copyright (c) 2024 Michael Hope
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __CH32V003_PINCTRL_H__
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#define __CH32V003_PINCTRL_H__
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#define CH32V003_PINMUX_PORT_PA 0
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#define CH32V003_PINMUX_PORT_PC 1
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#define CH32V003_PINMUX_PORT_PD 2
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/*
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* Defines the starting bit for the remap field. Note that the I2C1 and USART1 fields are not
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* contigious.
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*/
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#define CH32V003_PINMUX_SPI1_RM 0
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#define CH32V003_PINMUX_I2C1_RM 1
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#define CH32V003_PINMUX_I2C1_RM1 23
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#define CH32V003_PINMUX_USART1_RM 2
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#define CH32V003_PINMUX_USART1_RM1 21
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#define CH32V003_PINMUX_TIM1_RM 6
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#define CH32V003_PINMUX_TIM2_RM 8
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/* Port number with 0-2 */
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#define CH32V003_PINCTRL_PORT_SHIFT 0
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/* Pin number 0-15 */
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#define CH32V003_PINCTRL_PIN_SHIFT 2
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/* Base remap bit 0-31 */
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#define CH32V003_PINCTRL_RM_BASE_SHIFT 6
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/* Function remapping ID 0-3 */
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#define CH32V003_PINCTRL_RM_SHIFT 11
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#define CH32V003_PINMUX_DEFINE(port, pin, rm, remapping) \
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((CH32V003_PINMUX_PORT_##port << CH32V003_PINCTRL_PORT_SHIFT) | \
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(pin << CH32V003_PINCTRL_PIN_SHIFT) | \
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(CH32V003_PINMUX_##rm##_RM << CH32V003_PINCTRL_RM_BASE_SHIFT) | \
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(remapping << CH32V003_PINCTRL_RM_SHIFT))
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#define TIM1_ETR_PC5_0 CH32V003_PINMUX_DEFINE(PC, 5, TIM1, 0)
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#define TIM1_ETR_PC5_1 CH32V003_PINMUX_DEFINE(PC, 5, TIM1, 1)
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#define TIM1_ETR_PD4_2 CH32V003_PINMUX_DEFINE(PD, 4, TIM1, 2)
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#define TIM1_ETR_PC2_3 CH32V003_PINMUX_DEFINE(PC, 2, TIM1, 3)
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#define TIM1_CH1_PD2_0 CH32V003_PINMUX_DEFINE(PD, 2, TIM1, 0)
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#define TIM1_CH1_PC6_1 CH32V003_PINMUX_DEFINE(PC, 6, TIM1, 1)
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#define TIM1_CH1_PD2_2 CH32V003_PINMUX_DEFINE(PD, 2, TIM1, 2)
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#define TIM1_CH1_PC4_3 CH32V003_PINMUX_DEFINE(PC, 4, TIM1, 3)
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#define TIM1_CH2_PA1_0 CH32V003_PINMUX_DEFINE(PA, 1, TIM1, 0)
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#define TIM1_CH2_PC7_1 CH32V003_PINMUX_DEFINE(PC, 7, TIM1, 1)
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#define TIM1_CH2_PA1_2 CH32V003_PINMUX_DEFINE(PA, 1, TIM1, 2)
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#define TIM1_CH2_PC7_3 CH32V003_PINMUX_DEFINE(PC, 7, TIM1, 3)
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#define TIM1_CH3_PC3_0 CH32V003_PINMUX_DEFINE(PC, 3, TIM1, 0)
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#define TIM1_CH3_PC0_1 CH32V003_PINMUX_DEFINE(PC, 0, TIM1, 1)
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#define TIM1_CH3_PC3_2 CH32V003_PINMUX_DEFINE(PC, 3, TIM1, 2)
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#define TIM1_CH3_PC5_3 CH32V003_PINMUX_DEFINE(PC, 5, TIM1, 3)
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#define TIM1_CH4_PC4_0 CH32V003_PINMUX_DEFINE(PC, 4, TIM1, 0)
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#define TIM1_CH4_PD3_1 CH32V003_PINMUX_DEFINE(PD, 3, TIM1, 1)
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#define TIM1_CH4_PC4_2 CH32V003_PINMUX_DEFINE(PC, 4, TIM1, 2)
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#define TIM1_CH4_PD4_3 CH32V003_PINMUX_DEFINE(PD, 4, TIM1, 3)
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#define TIM1_BKIN_PC2_0 CH32V003_PINMUX_DEFINE(PC, 2, TIM1, 0)
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#define TIM1_BKIN_PC1_1 CH32V003_PINMUX_DEFINE(PC, 1, TIM1, 1)
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#define TIM1_BKIN_PC2_2 CH32V003_PINMUX_DEFINE(PC, 2, TIM1, 2)
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#define TIM1_BKIN_PC1_3 CH32V003_PINMUX_DEFINE(PC, 1, TIM1, 3)
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#define TIM1_CH1N_PD0_0 CH32V003_PINMUX_DEFINE(PD, 0, TIM1, 0)
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#define TIM1_CH1N_PC3_1 CH32V003_PINMUX_DEFINE(PC, 3, TIM1, 1)
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#define TIM1_CH1N_PD0_2 CH32V003_PINMUX_DEFINE(PD, 0, TIM1, 2)
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#define TIM1_CH1N_PC3_3 CH32V003_PINMUX_DEFINE(PC, 3, TIM1, 3)
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#define TIM1_CH2N_PA2_0 CH32V003_PINMUX_DEFINE(PA, 2, TIM1, 0)
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#define TIM1_CH2N_PC4_1 CH32V003_PINMUX_DEFINE(PC, 4, TIM1, 1)
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#define TIM1_CH2N_PA2_2 CH32V003_PINMUX_DEFINE(PA, 2, TIM1, 2)
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#define TIM1_CH2N_PD2_3 CH32V003_PINMUX_DEFINE(PD, 2, TIM1, 3)
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#define TIM1_CH3N_PD1_0 CH32V003_PINMUX_DEFINE(PD, 1, TIM1, 0)
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#define TIM1_CH3N_PD1_1 CH32V003_PINMUX_DEFINE(PD, 1, TIM1, 1)
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#define TIM1_CH3N_PD1_2 CH32V003_PINMUX_DEFINE(PD, 1, TIM1, 2)
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#define TIM1_CH3N_PC6_3 CH32V003_PINMUX_DEFINE(PC, 6, TIM1, 3)
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#define TIM2_ETR_PD4_0 CH32V003_PINMUX_DEFINE(PD, 4, TIM2, 0)
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#define TIM2_ETR_PC5_1 CH32V003_PINMUX_DEFINE(PC, 5, TIM2, 1)
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#define TIM2_ETR_PC1_2 CH32V003_PINMUX_DEFINE(PC, 1, TIM2, 2)
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#define TIM2_ETR_PC1_3 CH32V003_PINMUX_DEFINE(PC, 1, TIM2, 3)
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#define TIM2_CH1_PD4_0 CH32V003_PINMUX_DEFINE(PD, 4, TIM2, 0)
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#define TIM2_CH1_PC5_1 CH32V003_PINMUX_DEFINE(PC, 5, TIM2, 1)
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#define TIM2_CH1_PC1_2 CH32V003_PINMUX_DEFINE(PC, 1, TIM2, 2)
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#define TIM2_CH1_PC1_3 CH32V003_PINMUX_DEFINE(PC, 1, TIM2, 3)
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#define TIM2_CH2_PD3_0 CH32V003_PINMUX_DEFINE(PD, 3, TIM2, 0)
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#define TIM2_CH2_PC2_1 CH32V003_PINMUX_DEFINE(PC, 2, TIM2, 1)
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#define TIM2_CH2_PD3_2 CH32V003_PINMUX_DEFINE(PD, 3, TIM2, 2)
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#define TIM2_CH2_PC7_3 CH32V003_PINMUX_DEFINE(PC, 7, TIM2, 3)
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#define TIM2_CH3_PC0_0 CH32V003_PINMUX_DEFINE(PC, 0, TIM2, 0)
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#define TIM2_CH3_PD2_1 CH32V003_PINMUX_DEFINE(PD, 2, TIM2, 1)
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#define TIM2_CH3_PC0_2 CH32V003_PINMUX_DEFINE(PC, 0, TIM2, 2)
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#define TIM2_CH3_PD6_3 CH32V003_PINMUX_DEFINE(PD, 6, TIM2, 3)
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#define TIM2_CH4_PD7_0 CH32V003_PINMUX_DEFINE(PD, 7, TIM2, 0)
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#define TIM2_CH4_PC1_1 CH32V003_PINMUX_DEFINE(PC, 1, TIM2, 1)
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#define TIM2_CH4_PD7_2 CH32V003_PINMUX_DEFINE(PD, 7, TIM2, 2)
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#define TIM2_CH4_PD5_3 CH32V003_PINMUX_DEFINE(PD, 5, TIM2, 3)
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#define USART1_CK_PD4_0 CH32V003_PINMUX_DEFINE(PD, 4, USART1, 0)
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#define USART1_CK_PD7_1 CH32V003_PINMUX_DEFINE(PD, 7, USART1, 1)
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#define USART1_CK_PD7_2 CH32V003_PINMUX_DEFINE(PD, 7, USART1, 2)
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#define USART1_CK_PC5_3 CH32V003_PINMUX_DEFINE(PC, 5, USART1, 3)
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#define USART1_TX_PD5_0 CH32V003_PINMUX_DEFINE(PD, 5, USART1, 0)
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#define USART1_TX_PD0_1 CH32V003_PINMUX_DEFINE(PD, 0, USART1, 1)
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#define USART1_TX_PD6_2 CH32V003_PINMUX_DEFINE(PD, 6, USART1, 2)
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#define USART1_TX_PC0_3 CH32V003_PINMUX_DEFINE(PC, 0, USART1, 3)
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#define USART1_RX_PD6_0 CH32V003_PINMUX_DEFINE(PD, 6, USART1, 0)
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#define USART1_RX_PD1_1 CH32V003_PINMUX_DEFINE(PD, 1, USART1, 1)
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#define USART1_RX_PD5_2 CH32V003_PINMUX_DEFINE(PD, 5, USART1, 2)
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#define USART1_RX_PC1_3 CH32V003_PINMUX_DEFINE(PC, 1, USART1, 3)
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#define USART1_CTS_PD3_0 CH32V003_PINMUX_DEFINE(PD, 3, USART1, 0)
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#define USART1_CTS_PC3_1 CH32V003_PINMUX_DEFINE(PC, 3, USART1, 1)
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#define USART1_CTS_PC6_2 CH32V003_PINMUX_DEFINE(PC, 6, USART1, 2)
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#define USART1_CTS_PC6_3 CH32V003_PINMUX_DEFINE(PC, 6, USART1, 3)
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#define USART1_RTS_PC2_0 CH32V003_PINMUX_DEFINE(PC, 2, USART1, 0)
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#define USART1_RTS_PC2_1 CH32V003_PINMUX_DEFINE(PC, 2, USART1, 1)
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#define USART1_RTS_PC7_2 CH32V003_PINMUX_DEFINE(PC, 7, USART1, 2)
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#define USART1_RTS_PC7_3 CH32V003_PINMUX_DEFINE(PC, 7, USART1, 3)
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#define SPI1_NSS_PC1_0 CH32V003_PINMUX_DEFINE(PC, 1, SPI1, 0)
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#define SPI1_NSS_PC0_1 CH32V003_PINMUX_DEFINE(PC, 0, SPI1, 1)
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#define SPI1_SCK_PC5_0 CH32V003_PINMUX_DEFINE(PC, 5, SPI1, 0)
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#define SPI1_SCK_PC5_1 CH32V003_PINMUX_DEFINE(PC, 5, SPI1, 1)
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#define SPI1_MISO_PC7_0 CH32V003_PINMUX_DEFINE(PC, 7, SPI1, 0)
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#define SPI1_MISO_PC7_1 CH32V003_PINMUX_DEFINE(PC, 7, SPI1, 1)
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#define SPI1_MOSI_PC6_0 CH32V003_PINMUX_DEFINE(PC, 6, SPI1, 0)
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#define SPI1_MOSI_PC6_1 CH32V003_PINMUX_DEFINE(PC, 6, SPI1, 1)
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#define I2C1_SCL_PC2_0 CH32V003_PINMUX_DEFINE(PC, 2, I2C1, 0)
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#define I2C1_SCL_PD1_1 CH32V003_PINMUX_DEFINE(PD, 1, I2C1, 1)
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#define I2C1_SCL_PC5_2 CH32V003_PINMUX_DEFINE(PC, 5, I2C1, 2)
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#define I2C1_SDA_PC1_0 CH32V003_PINMUX_DEFINE(PC, 1, I2C1, 0)
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#define I2C1_SDA_PD0_1 CH32V003_PINMUX_DEFINE(PD, 0, I2C1, 1)
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#define I2C1_SDA_PC6_2 CH32V003_PINMUX_DEFINE(PC, 6, I2C1, 2)
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#endif /* __CH32V003_PINCTRL_H__ */
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42
soc/wch/ch32v00x/pinctrl_soc.h
Normal file
42
soc/wch/ch32v00x/pinctrl_soc.h
Normal file
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@ -0,0 +1,42 @@
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/*
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* Copyright (c) 2024 Michael Hope
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __PINCTRL_SOC_H__
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#define __PINCTRL_SOC_H__
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/**
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* @brief Type to hold a pin's pinctrl configuration.
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*/
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struct ch32v003_pinctrl_soc_pin {
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uint32_t config: 22;
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bool bias_pull_up: 1;
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bool bias_pull_down: 1;
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bool drive_open_drain: 1;
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bool drive_push_pull: 1;
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bool output_high: 1;
|
||||
bool output_low: 1;
|
||||
uint8_t slew_rate: 2;
|
||||
};
|
||||
|
||||
typedef struct ch32v003_pinctrl_soc_pin pinctrl_soc_pin_t;
|
||||
|
||||
#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \
|
||||
{ \
|
||||
.config = DT_PROP_BY_IDX(node_id, prop, idx), \
|
||||
.bias_pull_up = DT_PROP(node_id, bias_pull_up), \
|
||||
.bias_pull_down = DT_PROP(node_id, bias_pull_down), \
|
||||
.drive_open_drain = DT_PROP(node_id, drive_open_drain), \
|
||||
.drive_push_pull = DT_PROP(node_id, drive_push_pull), \
|
||||
.output_high = DT_PROP(node_id, output_high), \
|
||||
.output_low = DT_PROP(node_id, output_low), \
|
||||
.slew_rate = DT_ENUM_IDX(node_id, slew_rate), \
|
||||
},
|
||||
|
||||
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
|
||||
{DT_FOREACH_CHILD_VARGS(DT_PHANDLE(node_id, prop), DT_FOREACH_PROP_ELEM, pinmux, \
|
||||
Z_PINCTRL_STATE_PIN_INIT)}
|
||||
|
||||
#endif
|
||||
Loading…
Add table
Add a link
Reference in a new issue