board: s32z2xxdc2: allow the code to be executed from code RAM
- Trace32 runner: no need to configure TE bit in CFG_CORE register in the cmm start-up script, it can be configured at Zephyr start-up code when required (via SCTRL register) - MPU static regions also needs to be updated for XIP and non-XIP Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
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5 changed files with 32 additions and 20 deletions
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@ -30,4 +30,20 @@ config NET_L2_ETHERNET
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endif # NETWORKING
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if XIP
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# Offset between CRAM AXIM and CRAM AXIF, code will be downloaded
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# over AXIM interface
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config BUILD_OUTPUT_ADJUST_LMA
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default "-0x47800000"
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config CPU_CORTEX_R52_CACHE_SEGREGATION
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default y
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config CPU_CORTEX_R52_ICACHE_FLASH_WAY
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default 4
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config CPU_CORTEX_R52_DCACHE_FLASH_WAY
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default 1
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endif # XIP
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endif # BOARD_S32Z2XXDC2_S32Z270_RTU0 || BOARD_S32Z2XXDC2_S32Z270_RTU1
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@ -1,7 +1,7 @@
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# Copyright 2022,2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_XIP=n
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CONFIG_XIP=y
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CONFIG_ISR_STACK_SIZE=512
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CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=8000000
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@ -1,7 +1,7 @@
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# Copyright 2022,2024 NXP
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_XIP=n
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CONFIG_XIP=y
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CONFIG_ISR_STACK_SIZE=512
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CONFIG_SYS_CLOCK_TICKS_PER_SEC=1000
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CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC=8000000
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@ -20,20 +20,17 @@
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; - Core0 and Core2 (redundancy) operate as a lockstep pair *
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; - Core1 and Core3 (redundancy) operate as a lockstep pair *
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; default: yes *
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; - thumb set to "yes" to select the T32 instruction set at reset *
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; default: no *
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; *
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;*******************************************************************************
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ENTRY %LINE &args
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LOCAL &rtuStartAddr &cfgCoreAddr &coreId &rtuId &thumbBit &spltLckBit
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LOCAL &rtuStartAddr &cfgCoreAddr &coreId &rtuId &spltLckBit
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&command=STRing.SCANAndExtract("&args","command=","debug")
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&elfFile=STRing.SCANAndExtract("&args","elfFile=","")
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&rtu=STRing.SCANAndExtract("&args","rtu=","0")
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&core=STRing.SCANAndExtract("&args","core=","0")
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&lockstep=STRing.SCANAndExtract("&args","lockstep=","yes")
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&thumb=STRing.SCANAndExtract("&args","thumb=","no")
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IF ("&elfFile"=="")
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(
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@ -59,12 +56,6 @@ IF (&core<0||&core>3)
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ENDDO
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)
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; select ARMv8 instruction set at reset for all Cortex-R52 cores (CFG_CORE.THUMB bit)
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IF ("&thumb"=="yes")
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&thumbBit="1"
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ELSE
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&thumbBit="0"
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; select lock-step or split-lock mode (CFG_CORE.SPLT_LCK bit)
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IF ("&lockstep"=="yes")
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&spltLckBit="0"
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@ -126,8 +117,8 @@ GOSUB EnableRTU1
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; Init RTU SRAM
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DO ~~/demo/arm/hardware/s32z27/misc/s32z27_init_rtu&(rtu)_sram.cmm
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; Set reset value for TE bit and split-lock mode
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Data.Set EZAXI:&cfgCoreAddr %Long 0yXXXXxxxxXXXXxxxxXXXXxxxxXXXXx&(thumbBit)x&(spltLckBit) ; CFG_CORE
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; Set reset value for split-lock mode
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Data.Set EZAXI:&cfgCoreAddr %Long 0yXXXXxxxxXXXXxxxxXXXXxxxxXXXXxxx&(spltLckBit) ; CFG_CORE
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; Write loop to self instruction
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Data.Set EAXI:&rtuStartAddr %Long 0xFFFEF7FF
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@ -11,20 +11,25 @@
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#define DEVICE_REGION_END 0x76FFFFFFUL
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static const struct arm_mpu_region mpu_regions[] = {
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MPU_REGION_ENTRY("vector",
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(uintptr_t)_vector_start,
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REGION_RAM_TEXT_ATTR((uintptr_t)_vector_end)),
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MPU_REGION_ENTRY("SRAM_TEXT",
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(uintptr_t)__text_region_start,
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(uintptr_t)__rom_region_start,
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REGION_RAM_TEXT_ATTR((uintptr_t)__rodata_region_start)),
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MPU_REGION_ENTRY("SRAM_RODATA",
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(uintptr_t)__rodata_region_start,
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REGION_RAM_RO_ATTR((uintptr_t)__rodata_region_end)),
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#ifdef CONFIG_XIP
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REGION_RAM_RO_ATTR(CONFIG_FLASH_BASE_ADDRESS + KB(CONFIG_FLASH_SIZE))
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#else
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REGION_RAM_RO_ATTR((uintptr_t)__rodata_region_end)
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#endif
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),
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MPU_REGION_ENTRY("SRAM_DATA",
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#ifdef CONFIG_XIP
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(uintptr_t)_image_ram_start,
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#else
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(uintptr_t)__rom_region_end,
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#endif
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REGION_RAM_ATTR((uintptr_t)__kernel_ram_end)),
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MPU_REGION_ENTRY("DEVICE",
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