This change splits eth sram region name definition
and configuration.
In the end the configuration is stored only once
er declared name.
This name shall increase readability and maintainability
Signed-off-by: Alexander Kozhinov <ak.alexander.kozhinov@gmail.com>
The current implementation requires SoCs/Boards to manualy instantiate
the preripherals and initilize them.
The change lets Zephyr rely on the device tree setup to instantiate &
initialize the relevant gpio peripheral.
Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
When TRDC permission fails to be obtained, it does not recycle to
access ELE core to prevent blocking problems. The current practice
only generates a log warning alarm.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Currently the resource table is added to the memory-region labeled DDR.
This region can also be extra space for code/data, although this is
not yet implemented. This will mean that the linker is free to put
the resource table *after* the code/data sections in DDR. The resource
table must be at the start of the assigned DRAM area for the remote
core to support early-boot/late-attach usecases.
To solve this, we carveout the first 4KB of our DRAM area specifically
for the resource table. This matches how this issue was solved for the
K3 R5F cores.
To make this clear we label this memory-region "RSC_TABLE". This is
done at the linker file level, which is common for all K3 M4 boards
and so we update all 3 such boards in this one patch instead of
patch-per-board.
Signed-off-by: Andrew Davis <afd@ti.com>
I think my original idea with this default MPU setup was that the top
bits of the (fast) SRAM region might be useful for host DMA that
needed better latencies than the (extremely slow) system DRAM
mappings. So it should be left uncached for safety.
But unfortunately the author[1] of the SOF heap integration for this
platform decided to size the heap dynamically to use most of the SRAM
block (the vectors and a few other bits live at the bottom, but most
of .text is in DRAM).
Needless to say, an uncached heap is sort of a performance disaster.
It worked OK for default copy-only topologies but fell over the moment
we turned on nontrivial processing.
[1] Um... Hi. Yeah, that's me too.
Signed-off-by: Andy Ross <andyross@google.com>
Recent Python interpreters have started tossing bus errors from this
12-byte string search (the loader is looking for the winstream
descriptor in the live firmware image). My guess is that there's a
SIMD optimization that's been added that's trying to do e.g. a 16 byte
load, and something in the fabric is kicking that out. Note that this
is 100% a software change: the same hardware with one version of the
host environment works, and an update breaks it.
But really I have no idea what's happening here, the memory region in
question is documented as system DRAM, the same bus regular process
memory is on (it's just not kernel-utilized memory). All I know is
that the bus error is introduced with a Python upgrade from 3.8.20 to
3.11.10.
Regardless, it's no great hardship to do the search on 64 bit chunks.
Signed-off-by: Andy Ross <andyross@google.com>
When TRDC permission fails to be obtained, it does not recycle to
access ELE core to prevent blocking problems. The current practice
only generates a log warning alarm.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
silabs_s2 uses simplicity_sdk hal library, which already have by default
a zero latency IRQs mechanism with a hardcoded value. In order to be
aligned with simplicity_sdk, we need to activate Zero Latency IRQ in
Zephyr by default. The level (2) depends on the hardcoded
value in simplicity_sdk (CORE_ATOMIC_BASE_PRIORITY_LEVEL). Without this
fix, if you use an IRQ with a priority of 0 or 1, irq_lock() and
irq_unlock() have no effect for this IRQ.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
This SoC has an external XCACHE controller for CPU0
instruction and data bus.
Add code to enable the data cache. Instruction cache
is already enabled by SystemInit.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Update to support APP_CPU flash access.
- fix the map_rom_segment so it can be used in other context
- add IROM and DROM region size in Kconfig
- update the memory.h by using dts records
- fix the appcpu ld file to support flash
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Update and enable Wi-Fi/Bluetooth software coexistence management.
This improves package handling and is recommended to be used
in high traffic scenarios.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Decouple dependency of CONFIG_NXP_WIFI_SOFTAP_SUPPORT.
Add wifi defconfig to set default kconfig options when soft AP
enabled.
Signed-off-by: Fengming Ye <frank.ye@nxp.com>
The i.MX 91 SoC’s integrated EdgeLock® Secure Enclave provides
security features including lifecycle management, tamper detection,
secure boot and a simplified path to certifications. The i.MX 91
family features an Arm® Cortex®-A55 running at up to 1.4GHz,
support for modern LPDDR4 memory to enable platform longevity,
dual Gigabit Ethernet and dual USB ports, along with a rich set
of peripherals targeting medical, industrial and consumer IoT
market segments.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
This driver allow to use Zephyr native IP stack or the IP stack provided
by HAL / WiseConnect.
The WiseConnect implementation may take advantage of the specific
features provided by the 917 (power consumption, speed,
validation...).
Some notable features are not available with this interface:
- It seems Zephyr does not provide API to offload multicast membership
management. User should be to directly call WiseConnect APIs
- Support for ICMP frames is difficult. Note that WiseConnect
automatically answer to ping request. It is just not possible to
send ping requests and receive ping responses.
- Zephyr and WiseConnect both support TLS offloading. However this
patch does not implement it.
- Reentrancy in the WiseConnect side is uncertain.
This implementation has been tested with samples/net/wifi/ (which relies
on subsys/net/lib/shell).
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Driver was tested with a custom application which enabled the BT_SHELL.
Basic functionalities were verified:
- Scanning
- Advertising
- Connecting
Configuration needed for the test:
- CONFIG_BT=y
- CONFIG_BT_PERIPHERAL=y
- CONFIG_BT_CENTRAL=y
- CONFIG_BT_SHELL=y
- CONFIG_SHELL=y
Co-authored-by: Tibor Laczko <tibor.laczko@silabs.com>
Signed-off-by: Tibor Laczko <tibor.laczko@silabs.com>
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Network Processor (NWP) is used to run WiFi, Bluetooth and Flash
drivers.
Co-authored-by: Tibor Laczko <tibor.laczko@silabs.com>
Signed-off-by: Tibor Laczko <tibor.laczko@silabs.com>
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Report DMA configuration in the board definitions.
Note the addresses of the DMA buffers are hardcoded in the HAL. So,
these areas have to be declared in the linker file.
Co-authored-by: Sai Santhosh Malae <santhosh.malae@silabs.com>
Signed-off-by: Sai Santhosh Malae <santhosh.malae@silabs.com>
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
This device is included on Silabs SiWx91x series. The current driver is
able to manage "High Power" and "Ultra Low Power" pins.
Co-authored-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Introduce minimal support for Silicon Labs SiWx91x family. SiWx91x
provide many device and especially Bluetooth and Wifi connectivity. This
patch prepare Zephyr to receive further drivers.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Enable sam4l internal factory calibrated RC32K clock source. The RC32K
was used as source for Generic Clock 5 using 32 as divider. The output
is a 1024 Hz clock that can be used by GLOC and TC0 peripherals.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
- mpu code in soc.c for 20829 platform was accidentally removed
in a recent PR. This is its reapplication
Signed-off-by: McAtee Maxwell <maxwell.mcatee@infineon.com>
Configure the Generic Clock Generator to be used as source to RTC.
The index 4 is now reserved to RTC.
Signed-off-by: Gerson Fernando Budke <nandojve@gmail.com>
Instead of forwarding pins to the network core during the
initialization, do it just before reseting the network core. With
this approach pins can be used by the application core as long as
network core is not started.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
CONFIG_ADSP_POWER_DOWN_HPSRAM may not be defined (when it's "n") so
update the code accordingly so that power_down() is called with
correct parameters.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Remove ESP heap from the sources. System heap is default heap.
Use heap adapter layer to configure used heap.
Use MEM_POOL memory request config to Wi-Fi and Bluetooth drivers.
Update the Wi-Fi and BLE memory needs.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
For Nuclei ECLIC, the interrupt level (mintstatus.MIL) is restored from
the previous interrupt level (mcause.MPIL) only if mcause.interrupt is set.
This behavior is not defined in the RISC-V CLIC spec.
If an ISR causes a context switch and mcause.interrupt is not set in the
next context (e.g. the next context is yielded from ecall), interrupts will
be masked after MRET because the interrupt level is not restored.
Use SOC-specific context to set mcause.interrupt to ensure the interrupt
level is restored correctly.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
The main thread, if configured with coop priority (don't do that :D)
breaks gpd since it has a non yielding while loop (also don't do that)
Add an explicit yield() to allow other threads to run if main or other
threads use gpd with coop prio.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Make clock init functions in SOC level weak and global so they can be
overriden by board/app level.
Ideally these should have been put at board level but for now just make
them weak so they can be overriden without breaking anything.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add support for pinctrl to cc23x0 SoC. Like for other TI SoCs,
a node approach is implemented (no grouping approach).
Signed-off-by: Lars Thalian Morstad <l-morstad@ti.com>
Signed-off-by: Vebjorn Myklebust <v.myklebust@ti.com>
Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com>
Signed-off-by: Julien Panis <jpanis@baylibre.com>
When the SiSDK HAL was introduced, a corresponding Kconfig option
was not. Update Series 2 SoCs to use the new option.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Generate a proper Cmake warning when signing tool isn't available.
This also allows not to fail in Github CI.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
