Fixes the Kconfig name of this so that it matches the value from
soc.yml, this has not been deprecated because this SoC is a virtual
SoC used only with the boards in zephyr meaning it should not cause
any breakage of out-of-tree boards
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Fixes the Kconfig name of this so that it matches the value from
soc.yml, this has not been deprecated because this SoC is a virtual
SoC used only with the 2 boards in zephyr meaning it should not
cause any breakage of out-of-tree boards
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
This commit adds cache handling for Hifi4 core on RT600.
Enable CACHE_MANAGEMENT and HAS_DCACHE.
This is required for proper data coherency when the DSP shares memory
with other cores (e.g., Cortex-M33) or DMA peripherals.
With this change, applications can now use sys_cache_data_flush_range()
and sys_cache_data_invd_range() to ensure cache coherency in shared
memory scenarios.
Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com>
Fixes using a dt function which suffered from firstly trying to
take the value from a variable that isn't defined, and which if is
ignored, was entirely invalid due to supplying a chosen node, not
a path as the dt function explicitly requires
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Fixes Kconfig naming to be properly set as required by HWMv2, to
allow for future build system features to work
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Fixes a wrongly added SoC feature which should not have been
accepted in the original way it was added, by correctly adding a
Kconfig to select an optional build configuration for this SoC
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
The Versal RPU uses Arm Cortex-R5F cores, which implement VFPv3-D16
(single and double precision with 16 double-word registers):.
Select VFP_DP_D16 to describe the available VFP configuration for this SoC.
Signed-off-by: Yasushi SHOJI <yashi@spacecubics.com>
Adding support for running Zephyr OS as a guest virtual machine
in the QNX Hypervisor environment.
This change introduces a new board configuration for ARM64-based
QNX Hypervisor VM.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
STM32H5, STM32L5, STM32U5, and STM32WBAX series MCUs have external
ICACHE/DCACHE with a cache line size of 16 bytes. The previous
configuration incorrectly set the cache line size to 32 bytes (the
default cache line size for Cortex-M cores).
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
Introduce the NRF_DT_IRQ_DIRECT_DEFINE and NRF_DT_IRQ_CONNECT macros
which reduce provide a common way for nordic drivers to adapt to the
presence of the SW ISR table which is commonly excluded as it is not
required for nordic socs. Also adds device driver inst variants of
the macros.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
1. This commit converts the 'XIP_BOOT_HEADER_DCD_ENABLE' preprocessor
define to Kconfig options across NXP i.MX RTxxxx evaluation boards.
The changes enable flexible boot header configuration through the
Kconfig build system instead of compile-time defines, improving
configurability and maintainability.
2. Now 'XIP_BOOT_HEADER_DCD_ENABLE' flag is only used in
hal_nxp/rtxxxx/fsl_flexspi_nor_boot.h which is included by soc.c,
therefore, this flag should be passed in the rtxxxx/SoC layer CMake
using zephyr_library_compile_definitions(). and can be removed from
each board CMakeLists.txt.
Note: if out-of-tree files still need to use this flag, please add
it in your own CMakeLists.txt.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
1. This commit converts the 'XIP_BOOT_HEADER_ENABLE' preprocessor
define to Kconfig options across NXP i.MX RTxxxx evaluation boards.
The changes enable flexible boot header configuration through the
Kconfig build system instead of compile-time defines, improving
configurability and maintainability.
2. Now 'XIP_BOOT_HEADER_ENABLE' flag is only used in
hal_nxp/rt11xx/fsl_flexspi_nor_boot.h which is included by soc.c,
therefore, this flag should be passed in the rt11xx/SoC layer CMake
using zephyr_library_compile_definitions(). and can be removed from
each board CMakeLists.txt.
Note: if out-of-tree files still need to use this flag, please add
it in your own CMakeLists.txt.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
For RT10xx and RT11xx, flag 'BOARD_FLASH_SIZE' is only used
in hal_nxp fsl_flexspi_nor_boot.h which is included by soc.c,
therefore, this flag should be passed in the SoC layer CMake
using zephyr_library_compile_definitions() to limit its scope.
Normally, 'BOARD_FLASH_SIZE' should not be used elsewhere.
If an out-of-tree user uses this flag elsewhere, please define
the flag yourself.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Create a dedicated Zephyr library for the imxrt11xx and
imxrt10xx SoC in CMakeLists.txt and move soc.c into it
(zephyr_library() + zephyr_library_sources(soc.c)).
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
We modified the Microchip MEC UART driver to be HAL
independent and be usuable on all MEC SoCs. The only
hardware difference is an extra register in the MEC174x/5x
family providing TX FIFO full and current byte count.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
The TI AM62L is a low-power ARM Cortex-A53 based SoC with display for
IOT, HMI and general purpose applications. More information here:
https://www.ti.com/product/AM62L
Add initial SoC and DTS support here.
Signed-off-by: Andrew Davis <afd@ti.com>
Add DT properties to select CK48M source for GD32 RCU.
Apply CK48M source selection during early SoC init.
Signed-off-by: Aleksandr Senin <al@meshium.net>
The ARC IoT SoC (used on iotdk board) has a hardware limitation where
entering CPU sleep mode causes some peripherals (e.g., UART) to lose
power, preventing the board from waking up via peripheral interrupts.
Add a configurable custom CPU idle option (CONFIG_ARC_IOT_CUSTOM_CPU_IDLE)
that enables interrupts without executing the sleep instruction. This
allows the system to remain responsive while keeping peripherals powered.
The option defaults to disabled (n) to preserve normal CPU sleep behavior
for most use cases. Tests that require continuous UART operation during
idle (pytest/shell harnesses) can enable it via platform-specific
extra_configs.
This approach allows timer-based idle to work correctly by default while
providing a workaround for tests that need UART retention.
Signed-off-by: Mohamed Moawad <moawad@synopsys.com>
Add linker script support for CONFIG_USERSPACE:
- MPU alignment macros for PMP granularity
- User stacks section in noinit area
- Application shared memory partitions
- Kernel object sections (text, rom, data, priv-stacks)
- ROM region size symbol for PMP configuration
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Replace some manually-defined DT_COMPAT_<> Kconfig macro variables with
their automatically generated counterparts. In most cases, this is
straightforward as the manually defined macro is named identically to the
one generated by the build system.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
xt-clang seems to generate some memory access patterns which
result in the simulator accessing incorrect memory and/or
messing with cached TLB entries when spinlock validation
is enabled. Not exactly sure what's going on here due to
the core of the simulator is built on top of pre-built
binaries provided by the toolchain without any sources so
debugging would be nearly impossible. But at least we have
an easy workaround by disabling spin lock validation.
Fixes#100885
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Set default values for BLE HCI buffer configuration that match
the ESP32 controller requirements:
- BT_BUF_ACL_RX_COUNT=24: Match controller's ACL buffer count
- BT_BUF_EVT_RX_COUNT=30: Match controller's event buffer count
Enable BT HCI node in device tree for all ESP32 SoCs that
support BLE.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The data is updated by both local domains (cpuapp/cpuapp) and
IronSide SE (cpusec), so disable caching to avoid coherency issues.
Signed-off-by: Håkon Amundsen <haakon.amundsen@nordicsemi.no>
This configure MPU region over OTP area like ID region.
OTP can be directly read and need to use flash HAL API for writing.
Signed-off-by: Gaétan Froissard <gaetan.froissard@marshmallow.kids>
Rework the Intel Audio DSP host IPC service backend to use the generic
ipc_service data/len conventions and the new critical send and buffer
management APIs.
Replace the backend-specific intel_adsp_ipc_msg and related enums with a
simple two-word payload passed through the standard ipc_service_send()
and ipc_service_send_critical() interfaces, and adapt the ISR and
receive callback to operate on this representation.
Use ipc_service_get_tx_buffer_size() as a readiness check for the host
channel and provide hold_rx_buffer() / release_rx_buffer()
implementations so ipc_service_release_rx_buffer() can be used to signal
when the channel becomes available again.
Wire the emergency send path through send_critical() to route urgent
messages via the backend's emergency fast path while keeping the normal
IPC flow unchanged.
Move the synchronous IPC wait logic out of the Intel Audio DSP host IPC
backend and into the common intel_adsp_ipc helper used by tests.
Update intel_adsp_ipc_send_message_sync() to both send the IPC message
through ipc_service_send() and wait on the backend semaphore, and remove
the now redundant ipc_send_message_sync() helper from the host IPC
backend.
Document that intel_adsp_ipc_send_message_sync() is a test-only helper,
not used by SOF firmware, and that it is a candidate for future removal
or for replacement by an explicit synchronous send primitive in the
generic IPC service API or in application code.
Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
5 years ago LiteX switched to 32 bit csr data width,
while the option is still available in litex, it doesn't really
work there, even if it can be build, the bios f.e. won't boot.
already described in https://github.com/enjoy-digital/litex/issues/1062
So it is currently only here for designs, that are older than
5 years and for fpgas, where also the fpga bitstream can be updated
it is time to remove the support and require the users, when they wan't
to update zephyr, that they also have to update their fpga bitstream.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
RTT need to use RAM which is not cacheable as RTT does not support
data cache. Using cpuapp TCM RAM memory section for RTT.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add MCUX_OS_TIMER configuration with CPU_FREQ-based default selection.
Update CORTEX_M_SYSTICK to be disabled when either LPTMR or OSTIMER
is selected as the system timer, ensuring only one timer is active.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Add initial support for the Allwinner H3 SoC, commonly
found in development boards like the Orange Pi series.
This commit introduces the intial SoC support files:
- Basic Kconfig configuration and SoC definition
- MMU region setup for memory management
- SoC-specific headers and device tree source include
Signed-off-by: Muhammad Waleed Badar <walid.badar@gmail.com>
This disables the kconfigs to build the reset vector and crt1
startup code from the architecture layer as ACE has its own
rom_entry() as entry point.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The idle enter was being traced but idle exit was not.
This change adds the missing call to sys_trace_idle_exit()
to the idle exit path for the it51xxx and it8xxx2 SoCs.
Signed-off-by: Rob Barnes <robbarnes@google.com>
Add the memory-regions property to mac in stm32h7rs.dtsi,
same as in stm32h7.dtsi, and set sram2 as default. Also add
the #memory-region-cells to sram2 and sram1 nodes.
Override the sram2 as default with sram1 in stm32h7s3.dtsi and
stm32h7s3.dtsi since sram2 is disabled per default.
Add the same checks as for h7 series to mpu_regions.c and sections.c.
Signed-off-by: Benjamin Klaric <benjamin.klaric01@gmail.com>
Use the memory-regions property in stm32h7.dtsi to explicitly locate
ethernet buffer and descriptor to an sram region. Set sram2 as default
and override with sram3 when available, in soc level .dtsi files.
Add #memory-region-cells to sram2 and sram3 nodes in specific .dtsi
files in dts/arm/st/h7, since it is needed by the memory-regions
property.
Add a check for memory-regions before the check and definition of the
sram_eth_node in mpu_regions.c and sections.ld.
Signed-off-by: Benjamin Klaric <benjamin.klaric01@gmail.com>
The binary-info feature that introduced in #54290 causing trouble
with some rp2xxx variant boards.
Turning off this feature defaultly to solve these problems.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
The LCD_CAM peripheral is a parallel I/O controller integrated in the ESP32
series. It consists of an LCD output module and a DVP camera input module.
The camera side is already supported in Zephyr as a video driver.
This commit adds support for the LCD module by implementing it as a
MIPI-DBI backend. The LCD_CAM supports multiple output formats, and the
initial implementation provides I8080 mode.
Signed-off-by: Chen Xingyu <hi@xingrz.me>
Move the shared pinctrl and clock initialization for the LCD_CAM peripheral
from the ESP32 DVP driver into a new SoC-level implementation.
Update the ESP32-S3 DTS to reflect the new structure by introducing an
`lcd_cam_dvp` child node under the common `lcd_cam` parent node.
Signed-off-by: Chen Xingyu <hi@xingrz.me>
The goal is to slowly convert all Microchip MEC to in-tree drivers
and support code (no HAL). We had partial HAL support for MEC172x
as the mech172x folder. We are removing HAL based mech172x since HAL
will be deprecated in the future and it has no board support.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
GPIO hardware in Microchip MEC parts is the same except for the MUX
field (number of alternate functions). We modify the old XEC PINCTRL
driver to work on all MEC parts and also be independent of HAL and
CMSIS register structures. During development we found a DT issue
with DT_ENUM_IDX_OR always inserting the default value. Worked around
by converting slew rate and drive strength to YAML integer type and
created defines for the values in the dt-bindings header.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
