Some platforms (nrf53 and nrf54h) are using hook for entering
idle to execute SoC specific code. There can only be one hook
in the application so it was impossible for the user to add own
code that is executed in the hook.
Add CONFIG_NRF_CUSTOM_ON_ENTER_CPU_IDLE_HOOK option. If enabled,
the Nordic hook is not implemented. The user implements own hook.
It is the user's responsibility to include SoC specific part in
that hook.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add BLE controller port layer (IRQ, clock, RF callbacks) and linker
scripts for the vendor binary blob.
ble_rwdata.ld: places .pds_code, .tcm_data, .retention and ROM data
with GP-relative addressing into the .data section (RWDATA).
ble_hbn.ld: places .hbn_code (RF functions) and .retention_noinit
into the RETRAM region (HBN RAM at 0x40010000). Provides linker
symbols __LD_CONFIG_EM_SEL and __LD_BLE_CORE_REG_SIZE consumed by
the controller blob.
soc.c: configure GLB_EM_SEL for 8KB (or 16KB for m8s1p) exchange
memory when BLE is enabled, and copy .hbn_code from flash to RETRAM
at boot.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Add a LONG(0) at a 16-byte aligned start of .flash.rodata_end so
the merged flash.rodata segment size never lands on a boundary
that trips esptool's --ram-only-header alignment assertion during
elf2image.
Applied to all espressif socs since the issue is not chip-specific.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
SRF needs to be initialized on the cm33ns soc to be used to
send requests to the SPE. Added configuration file and code
to properly initialize srf requests pool.
Signed-off-by: Laura Carlesso <laura.carlesso@infineon.com>
VPR after boot has default sleep mode set to WAIT which is the most
power hungry sleep mode. Typically, user expects to see low current
when system enters system-on-idle state. Set sleep mode that is
more suitable: DEEPSLEEP by default for nRF54H20 PPR which allows to
reach <5 uA idle current and has almost the same wake up time as WAIT,
HIBERNATE for other VPRs on non-NRF54H20. It allows to get <5 uA
currents in system-on-idle.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Update the help text for CONFIG_SECOND_CORE_MCUX to be more generic
and applicable to all supported multi-core RT series (RT11xx, RT118x,
and RT7xx), rather than being specific to RT11xx and Cortex-M7/M4.
The updated documentation now refers to "primary core" and "secondary
core" instead of specific core types, making it more accurate for all
supported SoC series.
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Rework GPPI configuration for SD^2PPI global domain. There can
be an SoC which does not have dppic135, dppic136, ppib136 and
ppib137 nodes. Add build time conditions to configuration files.
Additionally, remove references to APBxx (bus) names which
could be confusing as they are not references anywhere else.
Use DPPIxxx identification instead.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Move files which are specific to nrf54h20 global domain from nrf54h
folder to common. Rename those files to use sd2ppi name instead of
nrf54h. SD2PPI (or SD^2PPI) is an abbrevation for Secure Distributed
(multi-Domain) DPPI - PPI system where DPPI resources requires
Ironside service.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add SOC_RTS5912_ULPM_POWEROFF_BRAM for user to decide
if the BRAM need keep power or not during ULPM.
SOC_RTS5912_ULPM_POWEROFF_BRAM default as n, means NOT to poweroff.
Signed-off-by: Elmo Lan <elmo_lan@realtek.com>
Place mspi_timing_by_mspi_delay text and rodata in IRAM/DRAM.
This file contains PSRAM and flash timing tuning functions
that must not run from flash during MSPI clock reconfiguration.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add missing Kconfig.sysbuild to enable VPR launcher image when
building for the FLPR core.
Signed-off-by: Dhanoo Surasarang <dhanoo.surasarang@nordicsemi.no>
1. Remove the NRF_PLATFORM_HALTIUM and NRF_PLATFORM_LUMOS Kconfig
symbols and eliminate all "haltium"/"lumos" naming from the zephyr
directory.
2. The shared haltium_power.c/h and haltium_pm_s2ram.c/h files from
soc/nordic/common/ are duplicated into the per-SoC-series directories
(nrf54h/ and nrf92/) as soc_power.c/h and soc_pm_s2ram.c/h. The
corresponding build rules are moved from common/CMakeLists.txt to the
per-series CMakeLists.txt files.
3. Kconfig guards that relied on the platform symbols are replaced with
individual hardware feature checks derived from nrfx/MDK:
- select NRFX_POWER if !NRF_PLATFORM_HALTIUM -> if HAS_HW_NRF_POWER
- CLOCK_CONTROL default ... !NRF_PLATFORM_HALTIUM -> HAS_HW_NRF_CLOCK
- depends on NRF_PLATFORM_LUMOS -> SOC_SERIES_NRF54L||SOC_SERIES_NRF71
4. C preprocessor guards using CONFIG_NRF_PLATFORM_HALTIUM are replaced
with explicit SoC series checks (CONFIG_SOC_SERIES_NRF54H ||
CONFIG_SOC_SERIES_NRF92).
5. The sysbuild option NRF_HALTIUM_GENERATE_UICR is renamed to
NRF_GENERATE_UICR.
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
Add kconfig options for the signature flag and mirror comparison range
address, allowing projects to customize these settings.
Additionally, this change introduces custom signature extension section.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Enclose default LLEXT heap section placements with
!CONFIG_LLEXT_CUSTOM_HEAP_PLACEMENT. Users who want to
write a custom linker script can include files like
snippets-noinit.ld, common-noinit.ld or the SOC linker
scripts without including the default LLEXT heap
section placements.
Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
SoC series such as AM62x and AM62Lx use the GIC500 module. This module
supports up to 16 SGIs, 16 PPIs and 960 SPIs. This comes to a total of 992
interrupts. Hence, update the NUM_IRQ to match this number.
Signed-off-by: Amneesh Singh <amneesh@ti.com>
- Added autanalog MFD support in PSE84 DTS files
- Refactored autanalog ADC in PSE84 to use a common
MFD for handling the global AC configuration
- Constructed AC to use phandle in the overlay
for a better the user experience.
- Added support for a basic and advanced mode
with custom AC
Assisted-by: Claude:claude-opus-4.6
Signed-off-by: Richard Mc Sweeney <Richard.McSweeney@infineon.com>
Convert three NXP drivers from raw DT_REG_ADDR() register access
to the Zephyr device MMIO API (DEVICE_MMIO_ROM / DEVICE_MMIO_RAM /
DEVICE_MMIO_MAP):
With the MMIO API, the drivers create their own mapping at init time via
DEVICE_MMIO_MAP() thus the corresponding mmu_regions entries are removed
from the five NXP SoC files that carried them.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
This commit introduces the CONFIG_ESP_SPIRAM_BSS_RELOC_LIBS_AND_OBJS
parameter that when filled in with a list of library and/or object file
names and having the parameter CONFIG_ESP_SPIRAM enabled will allow that
.bss segments of such files be placed in .ext_ram.data section
Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
Now that CPU_CORTEX_A selects KERNEL_DIRECT_MAP when MMU is enabled,
there is no need for individual ARM64 board defconfigs or SoC Kconfig
files to enable it explicitly.
Signed-off-by: Carlo Caione <ccaione@baylibre.com>
The STM32F777 is a variant of the STM32F767 that adds a hardware
crypto accelerator (CRYP). Add SoC support by including the
stm32f767.dtsi and extending with the CRYP peripheral node.
Fixes: #105976
Signed-off-by: Anand Kumar <anandvtu16158@gmail.com>
Add targets to the UICR generator image that validates and/or prints
the register configurations in the generated PERIPHCONF blob:
* periphconf_validate (only check for errors)
* periphconf_dump (print entire blob, also prints errors)
* periphconf_dump_raw (same as periphconf_dump but with hex values)
Equivalent targets exist for SECONDARY PERIPHCONF:
* secondary_periphconf_validate
* secondary_periphconf_dump
* secondary_periphconf_dump_raw
The new validation replaces the old conflict detection
("PERIPHCONF has conflicting registers") and adds more checks.
PERIPHCONF registers are now also by default printed out in a human
readable format instead of by raw hex address and value.
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
The cm33 defaults to a secure state and we don't enable the MPC,
PPC, SAU, etc which all stay in their default states. To support
the HWINFO driver, we need the SAU enabled so the cm33_s can access
the device UID which is stored in non-secure memory.
Signed-off-by: Zayne Stites <Zayne.Stites@infineon.com>
Used Zephyr inline register access functions (sys_read/write)
instead of CMSIS register structure.
Used soc helper api to access/configure girq registers.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Add an RT118x ARM PLL binding wrapper that reuses the shared
loop-div/post-div schema and derive CLOCK_InitArmPll() directly
from devicetree.
RT118x keeps the new loop-div/post-div properties only and removes
the hard-coded loop and post divider values from the SoC init path
while retaining the HAL loop divider range check.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Replace the fixed-factor-clock compatible with an RT11xx ARM PLL
binding that shares the loop-div/post-div schema through a common
include.
The RT11xx wrapper keeps the deprecated clock-mult/clock-div
properties and the SoC code falls back per property so existing
definitions keep working while new overlays can switch to
loop-div/post-div.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Replace WAIT_FOR macro with a simple do-while loop in is_memory_ready()
used by the SMIF PM callback.
WAIT_FOR uses kernel timing functions which reside in flash.
During CY_SYSPM_AFTER_DS_WFI_TRANSITION callback
execution, the flash (SMIF) is being re-enabled and the external memory
may not be ready yet. Calling flash-resident kernel functions at this
point causes a hardfault.
The do-while loop uses only:
- Cy_SMIF_Memslot_IsBusy() - relocated to RAM
- Cy_SysLib_DelayUs() - located in RAM
This avoids any flash access during the early wake-up phase when flash
is not yet accessible.
Signed-off-by: Merin George <merin.george@infineon.com>
This is a direct copy from arch/xtensa/core/mem_manage.c.
It is moved here as the checks are really SoC specific and
should not be in the architecture code at all.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
When AES is activated in the DT, configure it's register region with
strong ordered, read and write access.
Signed-off-by: Tony Han <tony.han@microchip.com>
Add shared interrupt support for STM32 UART on SoC families where
multiple USART/LPUART peripherals share a single IRQ line (F0, G0,
L0, U0, C0).
Add a compile-time BUILD_ASSERT in the STM32 UART driver that detects
when two or more enabled UART instances share an IRQ and
CONFIG_SHARED_INTERRUPTS is not set.
Add configdefault SHARED_INTERRUPTS and SHARED_IRQ_MAX_NUM_CLIENTS
to the SoC Kconfig for STM32F0x, STM32L0x, STM32U0x, and STM32C0x.
Update DTS comments in the F0 family that previously stated shared
UART IRQs are unsupported.
The SHARED_IRQ_MAX_NUM_CLIENTS combinations in the F0x Kconfig were
generated with:
from itertools import combinations
usarts = ['usart3','usart4','usart5','usart6','usart7','usart8']
for n in range(6, 2, -1):
for combo in combinations(usarts, n):
conds = ' && '.join(
f'$(dt_nodelabel_enabled,{u})'
for u in combo)
print(f'\tdefault {n} if {conds}')
Fixes zephyrproject-rtos#39565
Signed-off-by: Anand Kumar <anandvtu16158@gmail.com>
Check for secondary RV32 support by way of devicetree checks, not enabling
explicitly for each SoC in Kconfig.
Signed-off-by: Pete Johanson <pete.johanson@analog.com>
Add Kconfig options to allocate OpenThread dynamic memory and message
pool buffer from external memory on ESP platforms:
- OPENTHREAD_EXTERNAL_HEAP_SHARED_MULTI_HEAPOPENTHREAD_HEAP_EXTERNAL:
routes otPlatCAlloc/otPlatFree through shared multi-heap to allocate
from external memory.
- OPENTHREAD_MESSAGE_POOL_CUSTOM_SECTION: places the message pool
buffer in a custom .ot_msg_pool linker section.
- Add .ot_msg_pool section to external RAM in the linker
script for ESP32, ESP32-C5, ESP32-S3, ESP32-S3
This allows offloading large OpenThread buffers to PSRAM, freeing
internal SRAM for other uses.
Signed-off-by: Marcio Ribeiro <marcio.ribeiro@espressif.com>
In 7579ccc68e (modules: hal_nordic: nrfs: Fix initialization priority)
used wrong priority as it assumed that NRFS is using IPC service init
priority. Priorities are fixed now and static assert is added to ensure
that NRFS init priority is higher than IPC service.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
sys_clock_set_timeout() and sys_clock_elapsed() are now documented
as requiring the system clock lock to be held by the caller. Wrap
the calls in subsys/pm/pm.c, soc/nxp/rw/power.c and the kernel
shell thread list command with sys_clock_lock()/sys_clock_unlock().
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
runtime_idle, also called standby in SiWx91x HAL power manager
did not need to check if it can go to sleep, reconfigure wireless
control after standby, or generate a synchronization event with
the NWP (network coprocessor) when the SoC exits runtime_idle.
This fixes a bug where the shell application is not responsive
with PM enabled. Since the system stays in runtime_idle due to
UART activity for the shell, interrupt information from the NWP
can be lost due to reconfiguration when exiting standby.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Previously, the purpose of disabling AVPLL and TDDR is to save power
consumption in low power. But all examples of RW612 use clock_init()
and disable AVPLL and TDDR without condition check is not proper.
Move disable AVPLL and TDDR to condition when they are not in use.
The ethernet uses TDDR clock and enet is enabled by default for RW612.
Add CONFIG_ETH_DRIVER along with enet and CONFIG_NET_L2_ETHERNET in
clock_init(). If any of the condition is not match, the TDDR clock
will be disabled.
Signed-off-by: Hui Bai <hui.bai@nxp.com>
