Adds initial SoC-level support for the Microchip SAM D5x
and E5x series, including SoC definition files.
Signed-off-by: Arunprasath P <arunprasath.p@microchip.com>
Map definition of NRF_GPIOTE0 to NRF_RADIOCORE_GPIOTE when MDK
defines NRF_RADIOCORE_GPIOTE instead of NRF_GPIOTE0
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
To prevent FSPI pins from floating, which may cause internal leakage
and increase SoC power consumption, tri-state is enabled by default.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
This commit raises the sspi clock from 24MHz to 48MHz and
corrects the clock divisor setting for it82xx2 chips.
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
There are some drivers like NXP SDMA that need a NonCacheable
data region to put data like channel control or buffer descriptors.
So far, we haven't added such a section because the linker created
one default orphan section at the end of the data section.
But this generates a warning in the build system:
xtensa-nxp_imx8m_adsp_zephyr-elf/bin/ld.bfd: warning: orphan section
NonCacheable' from modules/hal_nxp/libmodules__hal_nxp.a(fsl_sdma.c.obj)'
being placed in section `NonCacheable'
So fix this by explicitly define a NonCacheable area at the end of data
section.
This works because imx8mp cache attributes are
_memmap_cacheattr_imx8_wt_allvalid = 0x22212222
and the area where the NonCacheable section is allocated is
write-through.
So all the configuration for the SDMA core is not-cached at write.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
CONFIG_FLASH_MCUX_FLEXSPI_XIP should also be disabled when using MCUBoot
ramload mode with revert support.
Signed-off-by: Daniel DeGrasse <ddegrasse@tenstorrent.com>
MCUBoot RAMLOAD mode relies on CONFIG_XIP=n, but FLASH_MCUX_FLEXSPI_XIP
y-selects this symbol. Disable CONFIG_FLASH_MCUX_FLEXSPI_XIP for the
case where we are using MCUBoot ramload mode.
Signed-off-by: Daniel DeGrasse <ddegrasse@tenstorrent.com>
Update the bit offset of bit VCC_STS in the BKUP_STS register.
Signed-off-by: Alvis Sun <yfsun@nuvoton.com>
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
Only RTC DRAM area is currently being loaded during segment loader.
It means that RTC_IRAM and RTC_DATA is missing, causing
issues when sleep-modes are needed.
This also re-format the segments logging output
to meet with MCUBoot/Simple boot cases.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Updated twister.yaml workflow to fetch esptool for the CI.
Fix format of the arguments used in the esptool-5.0.2.
Check that esptool is available on build time.
Update runners for esp32.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Rename symbols so that they reflect purpose of defined memory regions.
Point region symbols to nodes in the DT. Move bogus IDT section before
DSP's ITCM. Move common ROM and RAM sections before the heap.
The move had to be done as these sections and the heap did overlap.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
Add dummy interrupt controller, clock control, pin control, Flexcomm 0,
Flexcomm 2, SAI0, SAI1, SAI2 into SoC's DT. Enable relevant nodes in
board's DT and include pinctrl definitions. Add default LED and button
nodes. Set /hifi4's real frequency. Add memory nodes for device's main
SRAM.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
Add desired Kconfig implications for the mimxrt798s/hifi4 domain. Add
pinctrl_soc.h and set up an include path for it.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
A recent commit inadvertently broke GDB stub on ACE. Revert that
part of the faulty commit.
Fixes: commit cfd6a0673c ("SoC: Intel: ACE: remove unused litelals
parts in interrupt vectors")
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
MCUBoot currently always builds the image as confirmed,
but image confirmation should be explicitly handled by the application
or subsystems.
This change disables the default behavior to avoid premature confirmation
during build time.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The sy1xx SoC enabled CONFIG_RISCV_SOC_EXCEPTION_FROM_IRQ and provided
its own __soc_is_irq implementation. However, the behavior matches the
default implementation, making the override unnecessary.
This commit removes the custom implementation and disables the config
option to remove unnecessary code.
Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
The __soc_is_irq function is only used when
CONFIG_RISCV_SOC_EXCEPTION_FROM_IRQ is enabled, which is not the case
for any WCH SoC. The implementation is therefore dead code.
Additionally, the implementation matches the default fallback behavior,
so no functional change would occur even if the config were enabled.
Signed-off-by: Miguel Gazquez <miguel.gazquez@bootlin.com>
Reorganize and update soc folder files for SDK-independance
Reorganize and update hal_bouffalolab files for SDK-independance
Reorganize and update soc dts files for SDK-independance
Update serial and pinctrl driver files for SDK-independance
Update ai_wb2_12f, bl604e_iot_dvk, and dt_bl10_dvk
to new bl60x support
and fixup openocd config of ai_wb2_12f
Signed-off-by: Camille BAUD <mail@massdriver.space>
litex supports little CSR ordering, also support
it in zephyr. historical the default is big ordering.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
This commit added support for Apollo510 SDIO host driver and
ambiq board configuration in fs_sample and disk_performance
Signed-off-by: Fan Wang <fan.wang@ambiq.com>
Create Kconfig variable NXP_INPUTMUX, which selects the fsl_inputmux
driver. Imply the MCUX component symbol from it. Imply that variable
from the NXP PINT, SmartDMA and LPC DMA drivers and from the mimxrt685s
SoC.
This needed to be done for the mimxrt700_evk/mimxrt798s/hifi4 domain, as
the INPUTMUX peripheral handles IRQ assginments and its driver
(fsl_inputmux) is used directly by the domain's soc.c. Instantiating the
currently dependent drivers (for PINT and SmartDMA) isn's possible nor
reasonable on the said target.
Signed-off-by: Vit Stanicek <vit.stanicek@nxp.com>
Configure the CTRLSEL value and the clock pin so that the TRACE pins
work when the TDD gets used.
Signed-off-by: Karsten Koenig <karsten.koenig@nordicsemi.no>
Added support for the IronSide TDD service which allows configuring and
powering the trace and debug domain of the nrf54h20.
Also provide option to start the trace and debug domain in the soc start
sequence.
Signed-off-by: Karsten Koenig <karsten.koenig@nordicsemi.no>
Use this approach for a simpler flow and to make relocation of images
into RAM easier.
Also do not force-select CONFIG_XIP (which is a default anyway), since
RP2350 can boot from SRAM.
Signed-off-by: Dmitrii Sharshakov <d3dx12.xx@gmail.com>
Add needed backtrace helpders routines and enable
backtrace for the Xtensa Fusion F1 DSP in the
IMXRT595S.
Signed-off-by: Mike J. Chen <mjchen@google.com>
