Correct the value written to the PMC_PCR register when configuring the
MCAN peripheral clock. Previously, incorrect GCLKDIV or GCLKCSS values
might be written if the MCAN clocks had already been configured before
Zephyr started.
Fixes: e79081f444 ("soc: microchip: sama7d6: update MMU and config
generic clocks for MCAN")
Signed-off-by: Tony Han <tony.han@microchip.com>
Add SoC layer support for the i.MX RT118x derivative parts that were
missing in Zephyr:
- MIMXRT1187 (CM33 + CM7)
- MIMXRT1185 (CM33 + CM7)
- MIMXRT118C (CM33 + CM7)
- MIMXRT1182 (single-core CM33)
- MIMXRT1181 (single-core CM33)
All CM33 cores in the family share the XCACHE controller and all CM7
cores share the ARM L1 I/D cache, so the existing cache select pattern
is reused.
The single-core RT1182/RT1181 parts are excluded from
SECOND_CORE_MCUX, and from the "_cm33" MCUX_CORE_SUFFIX since their
HAL device files carry no core suffix (MIMXRT1182.h, not
MIMXRT1182_cm33.h).
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Describe the STM32N6 8 KiB backup SRAM and enable the driver with
STM32_BACKUP_PROTECTION selected. Extract the retention logic into a
dedicated helper, use the correct device-tree SRAM address, and wait
for standby retention acknowledgement on STM32N6.
Assisted-by: opencode:openai/gpt-5.6
Signed-off-by: Tobias Meyer <tobias.meyer@hula.earth>
Select XTENSA_CPU_HAS_HIFI3 for the CAVS 2.5 (TGL) SOC series so that
the XTENSA_HIFI_SHARING infrastructure knows the coprocessor is present.
Without this the HiFi AE register file is never saved/restored across
context switches, corrupting the state of any thread that uses HiFi
instructions.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
All board and SoC Kconfig.defconfig overrides setting
CONFIG_RTC_INIT_PRIORITY=70 were workarounds to ensure the RTC counter
wrapper initialized after the underlying counter driver.
Signed-off-by: Soumya Tripathy <s-tripathy@ti.com>
Add the CH32H41X SoC series under the ch32v family. The CH32H417 is
an asymmetric dual-core (AMP) RISC-V part with a QingKe V3F boot
core and a QingKe V5F application core.
Model the two cores as cpuclusters with separate CPU descriptions,
runtime-idle power states, interrupt entry, vector handling, and
non-overlapping memory. Keep the external HSE frequency
board-specific.
The optional SOC_CH32H417_BOOT_V5F setting lets the V3F early-init
hook wake the V5F image at its real flash address, 0x08010000, while
allowing standalone V3F applications to disable that behavior.
Signed-off-by: Liu Changjie <liucj1228@outlook.com>
Include "dfp_override.h" for overriding the definitions of GMAC
registers for reusing "drivers/ethernet/eth_sam_gmac.c" with
minimum changes.
Signed-off-by: Tony Han <tony.han@microchip.com>
Instead of every new xtensa core having to modify xtensa_backtrace.c
and provide a header file with custom functions needed by the common
xtensa backtrace functions to validate stack and code addresses, now
xtensa_backtrace.c uses default weak functions that the soc can replace
with their own implementations.
Modify the current in-tree instances that used to have custom helper
functions to provide the standardize weak replacements.
Signed-off-by: Mike J. Chen <mjchen@google.com>
Co-authored-by: Filip Kokosinski <fkokosinski@antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
DRAM_STACK_START resolves to a devicetree-derived expression when
CONFIG_NOCACHE_MEMORY is enabled. Without devicetree.h the DT_REG_SIZE
and DT_NODELABEL macros reach the assembler unexpanded and fail. Add
the include so the early stack pointer resolves in all configurations.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The entry point set the stack pointer from inline asm inside a C
function, so the compiler was free to emit a prologue that spilled
through the stack inherited from ROM before the switch happened.
Where that stack overlaps .bss it corrupts statics arch_bss_zero()
has already cleared.
Do the gp, stack and vector table setup in assembly instead, then
hand off to C. Gate it on RISCV rather than RISCV_GP, as only the
gp setup depends on gp being used for addressing.
On esp32p4 v1.3 the early stack address came from devicetree macros,
which the assembler cannot evaluate. Derive it from plain literals
instead.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add clock control driver
Implement bootup clock initialization, on, off, configure and get_rate API
Signed-off-by: Sunil Abraham <Sunil.Abraham@microchip.com>
- Enable code execution from SRAM for mcxl platforms, as
most platforms treat SRAM as executable by default.
- The MCXL SoC does not grant execute permission to its SRAM banks by
default, so code placed in RAM (e.g. RAM-resident functions or tests
that execute from RAM) faults on fetch.
- Unlock the SRAM_XEN_DP register through the GLIKEY write-enable state
machine and set the execute-enable for SRAM.
- Tested on frdm-mcxl255
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
The esp32 runner implements the erase option as a full chip
erase. Flashing a sysbuild build with west flash --erase wiped
the previously programmed image before each new one, leaving
the device unbootable. Mark the erase option as a run-once
command so only the first image erases the chip.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This is almost a copy of the STM32L152xE support.
The STM32L152xE is already supported and is nearly identical.
The STM32L151xE differs only by lacking the LCD interface.
Signed-off-by: Florian Moesch <florian.moesch@draeger.com>
STM32H5 has a hardware data cache (DCACHE1, and DCACHE2 on some
part numbers) but unlike other STM32 series its soc_early_init_hook()
did not enable it, so the data cache was left disabled by default.
Enable it in soc_early_init_hook(), matching the behavior of the
stm32h7/h7rsx/f7/n6 SoCs.
sys_cache_data_enable() is a no-op when the part has no data cache
(e.g. STM32H503, where CPU_HAS_DCACHE is not selected), so this is
safe across the whole H5 series.
Signed-off-by: Liang Jiaxiang <moonbite233@gmail.com>
The RTL87x2G ROM initialization (via phy_init and related routines)
calls RamVectorTableUpdate() internally, which overwrites the NMI
vector in the RAM vector table with an RTK-specific handler. This
clobbers Zephyr's z_arm_nmi, causing the arm_runtime_nmi test to fail
on rtl87x2g_evb_a/rtl8762gku.
Fix this by calling RamVectorTableUpdate(NMI_VECTORn, z_arm_nmi) at
the end of rtl87x2g_isr_register(), which already runs in
soc_late_init_hook() after all SoC initialization is complete. This
restores the NMI vector to Zephyr's handler, consistent with how
peripheral IRQ vectors are already reconciled in the same function.
Fixes: tests/arch/arm/arm_runtime_nmi on rtl87x2g_evb_a/rtl8762gku
Co-Authored-By: Claude <noreply@anthropic.com>
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
Move SoC init steps that use kernel timers to the late init hook.
The system timer is not ready when the early init hook runs, so these
steps must run later after Zephyr has initialized timer support.
Co-Authored-By: Claude <noreply@anthropic.com>
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
The rtl8752h CM0+ SysTick does not have the COUNTFLAG early-assertion
hardware bug present on the KM4 core (rtl87x2g), so the default
k_busy_wait() implementation based on k_uptime_get_32() works correctly
on this platform.
Remove ARCH_HAS_CUSTOM_BUSY_WAIT and its arch_busy_wait() implementation
to fall back to the default k_busy_wait() which gives reliable results.
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
The nRF52 and nRF91 SoC bring-up (instruction cache and DC/DC
regulator enable) ran as a SYS_INIT at PRE_KERNEL_1 priority 0, i.e.
before any device initialization. Convert these to the SoC early init
hook, which runs at the same point, and select SOC_EARLY_INIT_HOOK for
the respective series. No functional change; this aligns the nRF52 and
nRF91 series with the SoC hook convention already used across the tree.
Assisted-by: Claude:claude-opus-4-8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
- Add SOC support under ti/am13 folder structure
- Kconfig integration for AM13E series and AM13E230X SOC
- MPU regions definition for AM13E
Signed-off-by: Sameer Srivastava <s-srivastava4@ti.com>
The idle argument of sys_clock_set_timeout() carries a distinct signal:
the CPU is entering low-power idle, here is its wakeup. Only the PM and
SoC power paths produce it (the timeout core always passes false), and
only a few drivers act on it to hand off to a low-power wakeup timer.
Introduce a dedicated sys_clock_idle_enter() hook for that, so the two
idle==true callers (subsys/pm and soc/nxp/rw) call it instead of
sys_clock_set_timeout(). Its weak default just programs the wakeup via
sys_clock_set_timeout(), so a driver with no low-power handling needs
nothing.
The five drivers that acted on idle (cortex_m_systick, esp32, xtensa,
mcux_os, stm32_lptim) move that handling into their own
sys_clock_idle_enter(), keeping their exact behaviour. Where the idle
path was self-contained it moves wholesale (cortex_m_systick, mcux_os,
stm32_lptim); where it shares the timeout programming, idle_enter()
calls set_timeout() first and then does its idle work (esp32), or shares
a small private helper (xtensa). set_timeout() keeps its now-unused idle
argument for the moment; nobody passes idle==true to it any more, which
lets the next change drop the argument entirely.
Signed-off-by: Nicolas Pitre <npitre@baylibre.com>
Move Cortex-M7 initialization to the POST_KERNEL to ensure that common
peripherals are already initialized by the Cortex-M33 main core.
Signed-off-by: Aziz Sellami <aziz.sellami@nxp.com>
XIP builds provide a separate ROM region for code and vectors, so a high
SRAM base address does not imply that the low-address TCM/vector mapping
is missing.
Keep the warning for non-XIP builds, but suppress it when CONFIG_XIP is
enabled.
Signed-off-by: Takumi Ando <takumi@spacecubics.com>
Use the address and size of the OCM devicetree node for the OCM MPU
region instead of hard-coded values.
This allows boards to map the full OCM region or reserve part of it for
firmware such as BL31.
Signed-off-by: Takumi Ando <takumi@spacecubics.com>
When `zephyr,sram` points to OCM, `DT_CHOSEN_SRAM_ADDR` is a
high address. The current MPU setup therefore treats OCM as a
separate DDR region, which produces a misleading DDR warning and
adds a redundant MPU region covering OCM.
Detect when OCM is selected as `zephyr,sram`, suppress the
DDR-specific warning, and avoid creating the separate DDR MPU
region. OCM is already covered by its dedicated MPU region.
Signed-off-by: Takumi Ando <takumi@spacecubics.com>
Use #include <> instead of #include "" to include a header file which path
is not relative to the directory path of the file emitting the #include
directive.
This change was made running scripts/check_quoted_includes.py script
proposed in https://github.com/zephyrproject-rtos/zephyr/pull/112135
with the Linux shell command below and manually selecting the applicable
changes:
$ find soc/nxp/ -type f -exec \
./scripts/check_quoted_includes.py -w {} \;
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
This commit adds support for MRAMC in the nrf_sys_event driver for
NRF_SYS_EVENT_IRQ_LATENCY. Note that MRAMC does not support DPPI, so the
driver will only use NRF_SYS_EVENT_IRQ_LATENCY_MANUAL mode when MRAMC
is present.
Signed-off-by: Robert Robinson <robert.robinson@nordicsemi.no>
The Wi-Fi core (LMAC/UMAC) is kickstarted from soc_early_init_hook()
when SOC_NRF71_WIFI_BOOT is set. Until now this symbol defaulted to y
on non-TF-M builds, so the core was booted unconditionally even when no
Wi-Fi driver was present. A booted Wi-Fi core is useless without the
driver that owns it, and no such driver exists in upstream Zephyr.
Invert the control: leave SOC_NRF71_WIFI_BOOT disabled by default and
turn it into a passive capability that the driver owning the core is
expected to select. This way the core is booted if and only if a driver
that can use it is present.
A pure-Zephyr build has no nRF71 Wi-Fi driver, so defaulting the boot
off is the correct behaviour and loses nothing.
Signed-off-by: Chaitanya Tata <Chaitanya.Tata@nordicsemi.no>
Assisted-by: Claude:claude-opus-4.8
The architecture idle paths call sys_trace_idle() and
sys_trace_idle_exit() to notify subscribers when the CPU enters and
leaves the idle state. These calls were guarded by CONFIG_TRACING,
which tied idle-time accounting to the tracing subsystem even though
no tracing backend is required to service the hooks.
Introduce a hidden Kconfig symbol, SYS_IDLE_HOOKS, that any subsystem
needing these notifications can select, and have TRACING select it.
Switch the idle-path guards in every architecture and SoC that emits
the hooks from CONFIG_TRACING to CONFIG_SYS_IDLE_HOOKS. Because
TRACING selects the new symbol, existing tracing behaviour is
unchanged; the change only lets non-tracing consumers receive the
hooks.
This is a prerequisite for building the CPU load module without the
tracing subsystem.
Assisted-by: Claude:claude-opus-4-8
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
Update the STM32 common Kconfig defaults to obtain the prescaler of the
chosen LPTIM-as-sysclk using the standard chosen zephyr,system-timer
instead of the vendor-specific stm32_lp_tick_source nodelabel.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Add initial SoC series support for the TI MSPM33C321A.
The MSPM33C series has no dependency on the TI MSPM0 SDK/HAL.
Guard common/soc.c and HAL includes in common/soc.h with
CONFIG_HAS_MSPM0_SDK so they compile only for MSPM0G/MSPM0L series.
Signed-off-by: Aman Lachhiramka <a-lachhiramka@ti.com>
Rename the TI MSP SoC family symbol from SOC_FAMILY_TI_MSPM0 to
SOC_FAMILY_TI_MSPM and directory from soc/ti/mspm0 to soc/ti/mspm
to accommodate upcoming MSP series beyond MSPM0 (MSPM0G, MSPM0L,
MSPM33) without ambiguity with other MSP product lines (MSP430,
MSP432).
Gate MSPM0-specific configs (MSPM0_PERIPH_STARTUP_DELAY, mclk
clock default) on MSPM0 series symbols to prevent unintended
enablement on future series.
No functional change for existing MSPM0G and MSPM0L builds.
Signed-off-by: Aman Lachhiramka <a-lachhiramka@ti.com>
- Adds zephyr,code-partition pointing to slot0_partition in the chosen
node to enable MCUboot-based booting.
- Increase ROM_START_OFFSET to 0x400 for imxrt7xx when
BOOTLOADER_MCUBOOT is enabled, as the default 0x200 offset is
insufficient for the higher ISR count on this SoC family.
- Adds a flash runner configuration used for sysbuild
multi-image projects, mainly for MCU-boot, to avoid unwanted
multiple erases and resets.
- Uses unified flash node naming used by other RTs.
- Fixed ext. flash comment to MX25UM51345G (was MX25UM51245G) in dts.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
Add SoC support for the Arm MPS3 AN536 Cortex-R52x2 FPGA image.
The AN536 platform uses a Cortex-R52 CPU, GICv3 and the Arm
architectural timer. Add the SoC Kconfig entries, SoC metadata,
Cortex-R linker script selection and MPU region configuration needed
by the platform.
Provide the CMSIS Core_R device definitions required by the Cortex-R
CMSIS headers, including the AN536 IRQn_Type interrupt map and GIC base
address definitions.
Signed-off-by: Andrei-Edward Popa <andrei.popa105@yahoo.com>
Upon waking from heavy sleep, the CPU resumes on a slow 25MHz RC clock
while the main PLL stabilizes (~40us). Returning immediately from
rts5912_heavy_sleep() causes early resume code to run at 25MHz, leading
to timing corruption and driver timeouts on high-speed buses like eSPI.
Fix this by adding a busy-wait loop after WFI to poll the PLL ready flag
(RTS5912_PLLCTRL_RDY), ensuring the CPU runs at full speed before
proceeding.
Signed-off-by: Elmo Lan <elmo_lan@realtek.com>
The timer task stack was sized at 4096 bytes, far above what the
registered callbacks use. Measured peak usage on Wi-Fi plus BLE and
Wi-Fi mesh workloads is around 350 bytes. Lower the default to 1536,
which keeps a wide margin above the observed peak while reclaiming
memory from every build that enables Wi-Fi or BLE.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The zephyr,mapped-partition binding translates partition reg addresses
through the parent ranges properties. gen_ftab.py was treating the
translated addresses as offsets relative to the NOR flash base and
added the base address a second time.
Use the partition addresses directly when populating the ftab and
writing the generated Intel HEX image.
Fixes: 7989a094f8
Signed-off-by: Zhengyu Yan <zhengyuyan@sifli.com>
On RV64, "1 << irq" uses a 32-bit int operand. When irq >= 32 this is
undefined behavior, and the resulting mask is zero-extended from int
so high CSR bits are never set. Use "1UL << irq" so the shift uses
an unsigned long (64-bit on RV64) and correctly covers all bits of
the mie/sie CSR.
Applies to arch_irq_enable(), arch_irq_disable() and
arch_irq_is_enabled() in soc_common_irq.c.
Signed-off-by: Liu Qian <liuqian.andy@picoheart.com>
Add ability to disable the second core boot through a Kconfig option, so
that the user can define and run the start function on application side.
Signed-off-by: Aziz Sellami <aziz.sellami@nxp.com>
Waking from PM_STATE_SUSPEND_TO_IDLE reset the SoC with a brownout
(hwinfo RESET_BROWNOUT) because SPC_SetLowPowerWakeUpDelay() ran only
on the STANDBY path. Call it on the SUSPEND_TO_IDLE path as well.
Fixes: 3114d7751b
Signed-off-by: Jacob Wienecke <jacob.wienecke@nxp.com>
The MCXE31B mask set errata sheet (Rev 1.2) lists ERR050456: resetting
the LPSPI FIFOs with CR[RTF]/CR[RRF] does not clear the FIFO pointers
completely, the documented workaround is to reset the entire module
with CR[RST]. Select the existing driver workaround like S32K3 does.
Without this, spi_loopback on frdm_mcxe31b receives stale bytes from
the previous transfer in the test cases which reuse the same spi
config (test_spi_null_tx_buf, test_spi_rx_half_start,
test_spi_same_buf_cmd). With the workaround selected these pass.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Use #include <> instead of #include "" to include a header file which path
is not relative to the directory path of the file emitting the #include
directive.
This change was made running scripts/check_quoted_includes.py script
proposed in https://github.com/zephyrproject-rtos/zephyr/pull/112135
with the Linux shell command below and manually selecting the applicable
changes:
$ find soc/intel/ -type f -exec \
./scripts/check_quoted_includes.py -w {} \;
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
This change removes underscore charaters from the PSE84 memory region
names. The zephyr_code_relocate CMake function uses underscore
characters as a delimiter for different properties in the target
region, so it is problematic to have underscores in the base name of
the memory region.
Signed-off-by: Brett Peterson <brett.peterson@infineon.com>
This API was never intended to be "public" in the sense now documented
in the Glossary, as said in 559c72d7a6:
"Introduce public functions for GPIO pins configuration [...] in
stm32 drivers & routines such gpio_stm32 & poweroff."
Remove the header from the public API directory and move the definitions
to a private header in SoC-specific includes. Update all previous users
of the header (which are as expected only those documented in the commit
message quoted above: gpio_stm32 and SoC poweroff.c).
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
