soc: adi: Add MAX32660 SoC

This commit adds MAX32660 SoC
and dts files.

Signed-off-by: Yasin Ustuner <Yasin.Ustuner@analog.com>
This commit is contained in:
Yasin Ustuner 2025-02-12 11:39:35 +03:00 committed by Benjamin Cabé
commit de9f48ee33
5 changed files with 259 additions and 0 deletions

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@ -0,0 +1,149 @@
/*
* Copyright (c) 2025 Analog Devices, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <zephyr/dt-bindings/pinctrl/max32-pinctrl.h>
/ {
soc {
pinctrl: pin-controller@40008000 {
/omit-if-no-ref/ swdio_p0_0: swdio_p0_0 {
pinmux = <MAX32_PINMUX(0, 0, AF1)>;
};
/omit-if-no-ref/ spi1_miso_p0_0: spi1_miso_p0_0 {
pinmux = <MAX32_PINMUX(0, 0, AF2)>;
};
/omit-if-no-ref/ uart1_tx_p0_0: uart1_tx_p0_0 {
pinmux = <MAX32_PINMUX(0, 0, AF3)>;
};
/omit-if-no-ref/ swdclk_p0_1: swdclk_p0_1 {
pinmux = <MAX32_PINMUX(0, 1, AF1)>;
};
/omit-if-no-ref/ spi1_mosi_p0_1: spi1_mosi_p0_1 {
pinmux = <MAX32_PINMUX(0, 1, AF2)>;
};
/omit-if-no-ref/ uart1_rx_p0_1: uart1_rx_p0_1 {
pinmux = <MAX32_PINMUX(0, 1, AF3)>;
};
/omit-if-no-ref/ i2c1_scl_p0_2: i2c1_scl_p0_2 {
pinmux = <MAX32_PINMUX(0, 2, AF1)>;
};
/omit-if-no-ref/ spi1_sck_p0_2: spi1_sck_p0_2 {
pinmux = <MAX32_PINMUX(0, 2, AF2)>;
};
/omit-if-no-ref/ cal32k_p0_2: cal32k_p0_2 {
pinmux = <MAX32_PINMUX(0, 2, AF3)>;
};
/omit-if-no-ref/ i2c1_sda_p0_3: i2c1_sda_p0_3 {
pinmux = <MAX32_PINMUX(0, 3, AF1)>;
};
/omit-if-no-ref/ spi1_ss0_p0_3: spi1_ss0_p0_3 {
pinmux = <MAX32_PINMUX(0, 3, AF2)>;
};
/omit-if-no-ref/ tmr0_p0_3: tmr0_p0_3 {
pinmux = <MAX32_PINMUX(0, 3, AF3)>;
};
/omit-if-no-ref/ spi0_miso_p0_4: spi0_miso_p0_4 {
pinmux = <MAX32_PINMUX(0, 4, AF1)>;
};
/omit-if-no-ref/ uart0_tx_p0_4: uart0_tx_p0_4 {
pinmux = <MAX32_PINMUX(0, 4, AF2)>;
};
/omit-if-no-ref/ spi0_mosi_p0_5: spi0_mosi_p0_5 {
pinmux = <MAX32_PINMUX(0, 5, AF1)>;
};
/omit-if-no-ref/ uart0_rx_p0_5: uart0_rx_p0_5 {
pinmux = <MAX32_PINMUX(0, 5, AF2)>;
};
/omit-if-no-ref/ spi0_sck_p0_6: spi0_sck_p0_6 {
pinmux = <MAX32_PINMUX(0, 6, AF1)>;
};
/omit-if-no-ref/ uart0_cts_p0_6: uart0_cts_p0_6 {
pinmux = <MAX32_PINMUX(0, 6, AF2)>;
};
/omit-if-no-ref/ uart1_tx_p0_6: uart1_tx_p0_6 {
pinmux = <MAX32_PINMUX(0, 6, AF3)>;
};
/omit-if-no-ref/ spi0_ss0_p0_7: spi0_ss0_p0_7 {
pinmux = <MAX32_PINMUX(0, 7, AF1)>;
};
/omit-if-no-ref/ uart0_rts_p0_7: uart0_rts_p0_7 {
pinmux = <MAX32_PINMUX(0, 7, AF2)>;
};
/omit-if-no-ref/ uart1_rx_p0_7: uart1_rx_p0_7 {
pinmux = <MAX32_PINMUX(0, 7, AF3)>;
};
/omit-if-no-ref/ i2c0_scl_p0_8: i2c0_scl_p0_8 {
pinmux = <MAX32_PINMUX(0, 8, AF1)>;
};
/omit-if-no-ref/ swdio_p0_8: swdio_p0_8 {
pinmux = <MAX32_PINMUX(0, 8, AF2)>;
};
/omit-if-no-ref/ i2c0_sda_p0_9: i2c0_sda_p0_9 {
pinmux = <MAX32_PINMUX(0, 9, AF1)>;
};
/omit-if-no-ref/ swdclk_p0_9: swdclk_p0_9 {
pinmux = <MAX32_PINMUX(0, 9, AF2)>;
};
/omit-if-no-ref/ spi1_miso_p0_10: spi1_miso_p0_10 {
pinmux = <MAX32_PINMUX(0, 10, AF1)>;
};
/omit-if-no-ref/ uart1_tx_p0_10: uart1_tx_p0_10 {
pinmux = <MAX32_PINMUX(0, 10, AF2)>;
};
/omit-if-no-ref/ spi1_mosi_p0_11: spi1_mosi_p0_11 {
pinmux = <MAX32_PINMUX(0, 11, AF1)>;
};
/omit-if-no-ref/ uart1_rx_p0_11: uart1_rx_p0_11 {
pinmux = <MAX32_PINMUX(0, 11, AF2)>;
};
/omit-if-no-ref/ spi1_sck_p0_12: spi1_sck_p0_12 {
pinmux = <MAX32_PINMUX(0, 12, AF1)>;
};
/omit-if-no-ref/ uart1_cts_p0_12: uart1_cts_p0_12 {
pinmux = <MAX32_PINMUX(0, 12, AF2)>;
};
/omit-if-no-ref/ spi1_ss0_p0_13: spi1_ss0_p0_13 {
pinmux = <MAX32_PINMUX(0, 13, AF1)>;
};
/omit-if-no-ref/ uart1_rts_p0_13: uart1_rts_p0_13 {
pinmux = <MAX32_PINMUX(0, 13, AF2)>;
};
};
};
};

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@ -0,0 +1,90 @@
/*
* Copyright (c) 2025 Analog Devices, Inc.
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <arm/armv7-m.dtsi>
#include <adi/max32/max32xxx.dtsi>
&clk_ipo {
clock-frequency = <DT_FREQ_M(96)>;
};
&sram0 {
reg = <0x20000000 DT_SIZE_K(16)>;
};
/delete-node/ &clk_iso;
/delete-node/ &clk_ibro;
/delete-node/ &clk_erfo;
/delete-node/ &adc;
/delete-node/ &gpio1;
/delete-node/ &i2c2;
/delete-node/ &uart2;
/delete-node/ &timer3;
/delete-node/ &trng;
/delete-node/ &flash0;
&flc0 {
flash0: flash@0{
compatible = "soc-nv-flash";
reg = <0x00000000 DT_SIZE_K(256)>;
write-block-size = <16>;
erase-block-size = <8192>;
};
};
/* MAX32660 extra peripherals. */
/ {
chosen {
/delete-property/ zephyr,entropy;
};
soc {
sram1: memory@20004000 {
compatible = "mmio-sram";
reg = <0x20004000 DT_SIZE_K(16)>;
};
sram2: memory@20008000 {
compatible = "mmio-sram";
reg = <0x20008000 DT_SIZE_K(32)>;
};
sram3: memory@20010000 {
compatible = "mmio-sram";
reg = <0x20010000 DT_SIZE_K(32)>;
};
dma0: dma@40028000 {
compatible = "adi,max32-dma";
reg = <0x40028000 0x1000>;
clocks = <&gcr ADI_MAX32_CLOCK_BUS0 5>;
interrupts = <28 0>, <29 0>, <30 0>, <31 0>;
dma-channels = <4>;
status = "disabled";
#dma-cells = <2>;
};
spi0: spi@40046000 {
compatible = "adi,max32-spi";
reg = <0x40046000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&gcr ADI_MAX32_CLOCK_BUS0 6>;
interrupts = <16 0>;
status = "disabled";
};
spi1: spi@40019000 {
compatible = "adi,max32-spi";
reg = <0x40019000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
clocks = <&gcr ADI_MAX32_CLOCK_BUS0 7>;
interrupts = <17 0>;
status = "disabled";
};
};
};

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@ -0,0 +1,14 @@
# Analog Devices MAX32660 MCU
# Copyright (c) 2025 Analog Devices, Inc.
# SPDX-License-Identifier: Apache-2.0
if SOC_MAX32660
config SYS_CLOCK_HW_CYCLES_PER_SEC
default $(dt_node_int_prop_int,/clocks/clk_ipo,clock-frequency)
config NUM_IRQS
default 55
endif # SOC_MAX32660

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@ -25,6 +25,10 @@ config SOC_MAX32655_M4
select SOC_MAX32655
select SOC_FAMILY_MAX32_M4
config SOC_MAX32660
bool
select SOC_FAMILY_MAX32_M4
config SOC_MAX32662
bool
select SOC_FAMILY_MAX32_M4
@ -84,6 +88,7 @@ config SOC_MAX78002_M4
config SOC
default "max32650" if SOC_MAX32650
default "max32655" if SOC_MAX32655
default "max32660" if SOC_MAX32660
default "max32662" if SOC_MAX32662
default "max32666" if SOC_MAX32666
default "max32670" if SOC_MAX32670

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@ -8,6 +8,7 @@ family:
- name: max32655
cpuclusters:
- name: m4
- name: max32660
- name: max32662
- name: max32666
cpuclusters: