soc: nxp: imxrt118x: add M7 MPU configuration
Added M7 MPU configuration. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
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3aafce99b3
commit
26a59796ed
4 changed files with 41 additions and 6 deletions
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@ -39,9 +39,6 @@ if(CONFIG_SOC_SERIES_IMXRT10XX OR CONFIG_SOC_SERIES_IMXRT11XX)
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endif()
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if(CONFIG_SOC_SERIES_IMXRT118X)
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if(CONFIG_SOC_MIMXRT1189_CM7)
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zephyr_sources(mpu_regions.c)
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endif()
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if(CONFIG_EXTERNAL_MEM_CONFIG_DATA)
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set(boot_hdr_xmcd_data_section ".boot_hdr.xmcd_data")
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endif()
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@ -11,6 +11,10 @@ if(CONFIG_SOC_MIMXRT1189_CM33)
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zephyr_linker_sources(DTCM_SECTION m33/dtcm.ld)
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endif()
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if(CONFIG_SOC_MIMXRT1189_CM7)
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zephyr_sources(m7/mpu_regions.c)
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endif()
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zephyr_include_directories(.)
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if(CONFIG_MEMC_MCUX_FLEXSPI)
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@ -2,7 +2,6 @@
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_IMXRT118X
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select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS if SOC_MIMXRT1189_CM7
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select CPU_CORTEX_M_HAS_DWT
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select SOC_RESET_HOOK
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select INIT_ARCH_HW_AT_BOOT if SOC_MIMXRT1189_CM33
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@ -13,8 +12,8 @@ config SOC_SERIES_IMXRT118X
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select CPU_HAS_ARM_SAU if SOC_MIMXRT1189_CM33
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select HAS_MCUX
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select CPU_HAS_ARM_MPU
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select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS if SOC_MIMXRT1189_CM33
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select ARM_MPU if SOC_MIMXRT1189_CM33
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select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
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select ARM_MPU
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select INIT_ARM_PLL
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select ARM_TRUSTZONE_M if SOC_MIMXRT1189_CM33
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select CPU_HAS_ICACHE
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35
soc/nxp/imxrt/imxrt118x/m7/mpu_regions.c
Normal file
35
soc/nxp/imxrt/imxrt118x/m7/mpu_regions.c
Normal file
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@ -0,0 +1,35 @@
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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/devicetree.h>
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#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
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#define REGION_ITCM_BASE_ADDRESS 0x00000000
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#define REGION_ITCM_SIZE REGION_256K
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#define REGION_FLEXSPI2_BASE_ADDRESS 0x04000000
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#define REGION_FLEXSPI2_SIZE REGION_64M
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#define REGION_DTCM_BASE_ADDRESS 0x20000000
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#define REGION_DTCM_SIZE REGION_256K
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#define REGION_FLEXSPI_BASE_ADDRESS 0x28000000
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#define REGION_FLEXSPI_SIZE REGION_128M
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#define REGION_PERIPHERAL_BASE_ADDRESS 0x40000000
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#define REGION_PERIPHERAL_SIZE REGION_1G
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static const struct arm_mpu_region mpu_regions[] = {
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MPU_REGION_ENTRY("ITCM", REGION_ITCM_BASE_ADDRESS, REGION_FLASH_ATTR(REGION_ITCM_SIZE)),
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MPU_REGION_ENTRY("FLEXSPI2", REGION_FLEXSPI2_BASE_ADDRESS,
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REGION_RAM_ATTR(REGION_FLEXSPI2_SIZE)),
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MPU_REGION_ENTRY("FLEXSPI", REGION_FLEXSPI_BASE_ADDRESS,
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REGION_FLASH_ATTR(REGION_FLEXSPI_SIZE)),
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MPU_REGION_ENTRY("DTCM", REGION_DTCM_BASE_ADDRESS, REGION_RAM_ATTR(REGION_DTCM_SIZE)),
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MPU_REGION_ENTRY("PERIPHERAL", REGION_PERIPHERAL_BASE_ADDRESS,
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REGION_PPB_ATTR(REGION_PERIPHERAL_SIZE)),
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};
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const struct arm_mpu_config mpu_config = {
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.num_regions = ARRAY_SIZE(mpu_regions),
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.mpu_regions = mpu_regions,
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};
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