The SoC-level default of 10 ms is too short when UART tracing is
enabled at 115200 baud: three trace hooks (isr_exit, switched_out,
switched_in) fire back-to-back after each sys-timer ISR and together
emit ~9-12 ms of synchronous UART output, leaving no CPU time for
application threads (sample.tracing.user, sample.tracing.gpio stall).
Remove the override and let the kernel default (20 ms) apply, which
provides sufficient headroom for application code to run between
scheduling events.
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
Now that all series (with wake-up pins) have been migrated to the new
binding, drop the old driver.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Add a new STM32 SoC-specific driver for management of wake-up pins at
Power Controller level. The more generic terminology "wake-up lines" is
used for consistency across all series, but the driver currently focuses
only on wake-up lines connected to GPIO pins. This driver is designed to
handle nodes with the new `st,stm32-pwr-wkupctrl` compatible as well as
derivatives (`st,stm32f1-pwr-wkupctrl` and `st,stm32f7-pwr-wkupctrl`).
The old driver is retained for backward compatibility; selection is done
automatically based on whether a node with the new compatible is present
and active in the Devicetree or not.
While at it, also update the STM32 GPIO driver to use the new driver
when appropriate by introducing a new (private) API. The old driver is
considered as deprecated and will be removed in a future commit.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The macro to check whether a node is a valid and active STM32 GPIOport
node will be useful for upcoming drivers, so move it to the common GPIO
header to enable reuse by other components.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
stm32_pwr_wkup_pin_cfg_pupd() is a trivial function. Inlining it inside
each SoC's `poweroff.c` makes it easier to follow the logic and should
also have a slightly smaller footprint.
Note that nothing remains in `stm32wbax/poweroff.c` because the function
was a no-op: STM32WBA series does not have the `wkup-pins-pupd` property
on its power controller.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Instead of encoding the WKUP line selection as a one-hot value, use a
plain integer value instead and update the associated driver to support
this new encoding. This change should have no impact on existing users
as long as they used the named constants instead of raw values in their
Devicetree.
While at it, also introduce a new macro for the bitmask of all supported
line sources, which is useful for extraction purposes.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Add helpers to arm the combined comparator interrupt and add a critical
section around it. Reduce callback register critical section from
irq_lock to irq_disable of the comparator interrupt.
Assisted-by: Github Copilot:claude-opus-4.8
Signed-off-by: John Batch <john.batch@infineon.com>
the clang linker does not like quotation marks
in the name, if the memory region has been
defined before without them. The build will
fail if they are not the same. This fixes it.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Track the time spent in deep doze / sleep states on ITE EC SoCs
(IT8xxx2, IT51xxx) by capturing the 32.768 kHz free-run timer timestamp
before entering deep sleep and accumulating elapsed cycles upon waking.
Add ite_ec_clock_get_sleep_ticks() to convert total deep-sleep cycles
to kernel ticks.
Signed-off-by: Keith Short <keithshort@google.com>
Assisted-by: Antigravity:gemini-1.5-pro
Rename ite_ec_timer_block_idle() to ite_it8xxx2_timer_block_idle() to
reflect that this DMA clock synchronization idle check is specific to
the IT8XXX2 SoC family. Remove the unnecessary header guard around its
prototype in soc_timer.h.
Signed-off-by: Keith Short <keithshort@google.com>
Assisted-by: Antigravity:gemini-1.5-pro
Mapped partitions already resolve to CPU-visible flash addresses. Stop
adding the FlexSPI mapping base a second time when adjusting remote
image load and boot addresses.
Signed-off-by: Tomas Galbicka <tomas.galbicka@nxp.com>
The MCUX LPTMR system-timer driver previously defaulted to enabled
whenever the /chosen/zephyr,system-timer node was compatible with
nxp,lptmr. On SoCs whose devicetree points zephyr,system-timer at an
LPTMR instance (e.g. frdm_mcxw71/mcxw716c), this forced every build,
including non-power-management builds, to select the 32.768 kHz LPTMR
and disable the Cortex-M SysTick. Tests that rely on the high-resolution
SysTick clock (tests/kernel/timer/timer_api) then failed because the
1024 tick/s LPTMR does not provide the required timing resolution.
Restore the explicit per-SoC policy: the generic driver no longer
defaults MCUX_LPTMR_TIMER on, and each SoC opts in on its own terms.
MCXW7xx, KE1xF and MCXC enable the LPTMR only when power management is
enabled (default y if PM); i.MX95 and i.MX952 M7 enable it only when the
LPTMR is not claimed by the counter driver (default y if
!COUNTER_MCUX_LPTMR). This keeps SysTick as the system timer for plain
builds while preserving the low-power LPTMR configuration for PM builds.
Update the 4.5 migration guide accordingly.
Fixes#115491
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Define labeled Cortex-A55 and Cortex-A76 CPU nodes for RK3588 and select
the combined Cortex-A76/A55 CPU configuration. Keep the existing
ROC-RK3588-PC SMP variant on its supported Cortex-A55 CPUs.
Signed-off-by: Chao Liu <chao.liu@processmission.com>
PSRAM timing tuning reprograms the MSPI core clock, which is
shared between flash and PSRAM. The esp_flash driver had already
cached the flash timing in its HAL context during
esp_flash_config(), so the stale values made SPI1 erase and write
operations fail once tuning ran.
Re-read the timing settled on by the tuning code after PSRAM chip
init. This restores flash access on ESP32-S3 with octal PSRAM at
80 MHz. Add a Zephyr-side capability symbol for the SoCs that
support MSPI timing tuning instead of relying on the HAL one.
Assisted-by: Claude:opus-4-8
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This commit migrates the existing pinmux driver for the musca-b1
board to the newer pinctrl API. The new implementation also fixes
a bug in the original pinmux driver which would have selected
alternative function 2 instead of ALTF1 as desired.
The musca-s1 pinmux driver has been left as this board is
deprecated.
Signed-off-by: Laurie Fay <Laurie.Fay@arm.com>
The Renesas RZ and Smartbond DA1469x Kconfig.defconfig files derive
FLASH_SIZE, FLASH_BASE_ADDRESS and BUILD_OUTPUT_ADJUST_LMA from
$(DT_CHOSEN_Z_FLASH), but never assign that preprocessor variable.
Kconfig.zephyr does assign it, at a point after the SoC Kconfig.defconfig
files have already been sourced, so these trees were picking up the
assignment from an unrelated vendor's tree that happened to be parsed
first, the way the ST, NXP and Realtek trees each assign it for
themselves.
Assign the variable in the files that use it, as the other SoC trees do.
Assisted-by: Claude:claude-opus-5
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
The npcx4 series did not provide a custom fixed SoC MPU region
definition, so it fell back to the default single-region flash
configuration in arch/arm/core/mpu/arm_mpu_regions.c.
On this SoC the flash is 384 KB based at 0x10060000, which the
default logic rounds up to a single 512 KB (REGION_512K) region.
The ARMv7-M MPU requires a region base aligned to the region size,
but 0x10060000 is not 512 KB aligned. The hardware masks the base
down to 0x10000000, so the region only covers 0x10000000-0x10080000
and leaves flash above 0x10080000 unprotected.
This is latent until the image grows past 0x10080000. With
CONFIG_NO_OPTIMIZATIONS=y the arm_thread_swap test image exceeds
that boundary and takes an MPU fault (Data Access Violation) when
code runs in the upper Code RAM.
Add a custom mpu_regions.c mirroring the npcx7 approach: split the
flash into two properly aligned 256 KB regions covering
0x10060000-0x100c0000
Fixes#114538
Assisted-by: Claude:claude-opus-4.8
Signed-off-by: Jun Lin <CHLin56@nuvoton.com>
The ztest benchmark framework places its iterable sections via
zephyr_linker_sources(DATA_SECTIONS ...), which end up in the generated
snippets-data-sections.ld. This linker script did not include that file,
so the _ztest_benchmark_*_list_start/end symbols were undefined and
benchmark tests failed to link.
Include snippets-data-sections.ld to fix it.
Signed-off-by: Iuliana Prodan <iuliana.prodan@nxp.com>
SLEEP_HOLD_EN is enabled by default, which gates SysTick and causes
the system to hang in tests like test_gpio_pin_configure_single_ended.
Set CPU sleep mode to RUN via SCMI CPU domain protocol during
soc_init() to clear SLEEP_HOLD_EN and allow SysTick to run.
Signed-off-by: Qiang Zhao <qiang.zhao@nxp.com>
All STM32 SoC and platforms embedding Zephyr MCUboot application or$
embedding TF-M (with or without its BL2 bootloader) do expect
a 1024 bytes header blob in the Zephyr application layout. Factorize
this default value instead of adding the same information in each
SoC series or at board level.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Add pinctrl support for Renesas RZ/A3M
Remove the default from the binding and use DT_PROP_OR(..., 0) when
extracting FILNUM/FILCLKSEL, so DT_NODE_HAS_PROP() distinguishes an
explicitly requested filter from an absent property.
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Support Zephyr RTOS on Cortex A720 for R-Car X5H.
For more information and documentation, please visit the product page:
https://www.renesas.com/secure/gen5-r-car-x5h
Signed-off-by: Nam Nguyen <nam.nguyen.xn@renesas.com>
Allow host-side remoteproc to locate a Versal RPU resource table in a
remoteproc-visible RPROC memory region. Publish its location using the
metadata format required when attaching to an RPU started before the APU.
Optionally use RPROC as the load region for initialized runtime data.
This supports layouts whose code and data use different memories without
making that layout a requirement for other Versal boards.
Signed-off-by: Takumi Ando <takumi@spacecubics.com>
Add the fixed NXP System MPU region table for the MCXE24X SoC series and
wire it into the build:
- Select CPU_HAS_NXP_SYSMPU for SOC_SERIES_MCXE24X.
- Compile the SoC MPU region table (nxp_mpu_regions.c) when
CONFIG_ARM_MPU is enabled.
The region table enforces execute-never for data/heap/stack and
read-only for rodata/text. Because the NXP MPU uses OR semantics (a
region granting access cannot be revoked by another), the background
region is split around SRAM when MPU_STACK_GUARD is enabled so the stack
guard can deny supervisor writes; a single background region is used
otherwise to save one boot region.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Inside an output section, assigning __rom_region_size without
ABSOLUTE() yields a section-relative ELF symbol. Zephyr's PMP
init casts that symbol's address to a size, so the ROM TOR entry
becomes section_base + size instead of the actual region length
and can cover the peripheral window (0x60000000+), causing
Store/AMO faults on protected accesses.
Force an absolute symbol on ESP32-C5/C6/P4.
Signed-off-by: Tiago Medicci <tiago.medicci@espressif.com>
Add support for the i.MX RT1150 family (MIMXRT1151/MIMXRT1152),
single Cortex-M7 core SoCs of the i.MX RT11xx series running at up
to 800MHz, to the shared imxrt11xx SoC layer. Clock init configures
the M7 root from the ARM PLL at 798MHz, keeps the bus roots at
240MHz and enables Forward Body Biasing in OverDrive mode. All
orderable part numbers are defined.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
Clear RET and RET2 during secure early initialization. Skip the
redundant nRF71 System OFF clear and use the nrfx all-sections helper
for other Nordic SoCs.
Signed-off-by: Erdem Simsek <erdem.simsek@nordicsemi.no>
When CONFIG_SOC_SERIES_NRF71_TFM_RAM_CTRL_SERVICE is set, route
z_nrf_retained_mem_retention_apply() to the secure RAM-control service
(tfm_platform_ram_ctrl_retention_set) instead of nrfx_ram_ctrl; the secure
build keeps the direct nrfx path. Apply regions best-effort and return
-EIO if the secure service rejects one.
Signed-off-by: Erdem Simsek <erdem.simsek@nordicsemi.no>
Add SOC_SERIES_NRF71_TFM_RAM_CTRL_SERVICE for nRF71 TF-M builds
and pass it to the TF-M build as -DNRF_RAM_CTRL_SERVICE, so the secure
RAM-control service is compiled into the secure image for non-secure
builds.
Signed-off-by: Erdem Simsek <erdem.simsek@nordicsemi.no>
Enable hardware-backed System OFF RAM retention (MEMCONF RET) for
nRF7120 via the nrfx_ram_ctrl / retained_mem path.
Signed-off-by: Erdem Simsek <erdem.simsek@nordicsemi.no>
When TRNG is activated in the DT, configure it's register region with
strong ordered, read and write access.
Signed-off-by: Tony Han <tony.han@microchip.com>
Rename the source file for sama7d6 and simplify the sources file by
using "${CONFIG_SOC_SERIES}.c" in "CMakeLists.txt".
Signed-off-by: Tony Han <tony.han@microchip.com>
Configure the Cortex-R52 GIC so Group 1 interrupts, including
the virtual timer PPI, are delivered correctly.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Calling timer_5ms_one_shot() from chip_run_pll_sequence() can result
in a R_RISCV_RVC_JUMP linker relocation truncaction error because
timer_5ms_one_shot() links into flash, and chip_run_pll_sequence()
links into RAM.
Move the timer_5ms_one_shot() call out of chip_run_pll_sequence()
and into chip_configure_pll() right before chip_run_pll_sequence()
is invoked.
Tested on IT8xxx2 EC board.
Signed-off-by: Keith Short <keithshort@google.com>
Assisted-by: Antigravity:gemini-1.5-pro
Xtensa architecture does not have native inter-processor
interrupts and must rely on mechanism on SoC or board to do
that. Because of this, the architecture should not select
CONFIG_ARCH_HAS_DIRECTED_IPIS and should let SoC or board
layer to do that, where CONFIG_SCHED_IPI_SUPPORTED is also
being selected.
Note that CONFIG_XTENSA_LAZY_HIFI_SHARING is now dependent
on CONFIG_ARCH_HAS_DIRECTED_IPIS as it uses directed IPI.
Due to that it keeps sending IPI under the other has saved
HIFI state, it is not really appopriate to broadcast IPIs.
That's why it can only be enabled when directed IPI is
supported.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The SiWx91x reference manual describes a dedicated JTAG_TDO/SWO pin
that outputs Serial Wire Viewer (SWV) trace data over SWO, same as
the ARM CoreSight infrastructure used on other Silabs SoCs that
already select HAS_SWO. Select HAS_SWO so LOG_BACKEND_SWO becomes
available for this family.
While there, sort the select statements, as done in the rest of the Silabs
SoC Kconfig files.
Assisted-by: Claude:claude-sonnet-5
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
The xg22 and xg27 Series 2 SoCs (Cortex-M33) and the siwx91x family
(Cortex-M4) did not select CPU_CORTEX_M_HAS_DWT, unlike their sibling
SoCs based on the same core.
The Silicon Labs reference manuals for EFR32xG22 and EFR32xG27
("DBG - Debug Interface" section) and for SiWx917 ("Trace and Debug"
chapter) explicitly list the Data Watchpoint and Trace (DWT) unit as
an implemented feature, same as on xg21/xg23/xg24/xg26/xg28/xg29.
Select CPU_CORTEX_M_HAS_DWT for these SoCs to match the hardware and
be consistent with the rest of the series.
Assisted-by: Claude:claude-sonnet-5
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Powering down the peripheral domain in light sleep allocates the CPU
retention frames from the system heap at each sleep entry. Declare the
requirement so builds enabling it get the heap they need instead of
relying on each application to size it.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Add SoC and devicetree support for the R-Car Gen4 R8A779G0 A76.
Co-authored-by: Yuya Hamamachi <yuya.hamamachi.sx@renesas.com>
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
When the STM32 GPIO driver is not enabled, drop the gpio_driver_config
common field from the instance configuration and don't create instance
data blocks as they become unnecessary. This reduces the footprint in
this configuration.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Stop instantiation of the GPIO port nodes as proper devices when the
STM32 GPIO driver is disabled. This allows application to build but
then fail miserably at runtime because they try to using the GPIO API
without CONFIG_GPIO=y.
Instead, when CONFIG_GPIO_STM32=n, use the DEVICE_DEFINE() macro
to still create `struct device`s (which are needed by our API and to
use PM services), but with a name that doesn't match the one expected
by DEVICE_DT_GET(). This ensures any naive consumer trying to use the
GPIO ports will get a "__device_dts_ord_N not found" linker error at
build, as it would if the GPIO driver (which isn't built in this case)
did handle instantiation, without loosing access to device servicis
since we still creating an actual `struct device`. The only downside
of this approach is that the GPIO ports become "software devices" so
they don't have any dependencies and their initialization priority
is not checked. This should be fine because in this configuration,
the devices are private and very little code will interact with them.
(Really, only the STM32-specific pinctrl driver will...)
An alternative option would be to call Z_DEVICE_DEFINE() directly
to create frankenstein-esque devices which would be recognized as
coming from a Devicetree node but forced to have the "wrong" name.
However, this requires usage of an internal macro so it has been
avoided here.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Use GPIO_COMMON_CONFIG_FROM_DT_NODE() to initialize the GPIO subsystem
`common` field of the instance's configuration instead of manually
initializing each field.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
