This adds STM32U5F7/STM32U5G7 which are basically U5F9/U5G9
respectively with LQFP100 packages without DSI.
Also adds missing STM32U5F9xJ DTS and updates Kconfig file.
Signed-off-by: Adam BERLINGER <adam.berlinger@st.com>
Add initial support for the Rockchip RV1106 SoC. This SoC features
a single Cortex-A7 core and is commonly found in multimedia and IP
camera applications like the Luckfox Pico series.
Signed-off-by: Patryk Koscik <koscikpatryk@gmail.com>
Add the MIMX8ML8CVNKZ SoC part number (i.MX8MP, Cortex-M7,
LFBGA272 package) to the Kconfig selection list.
This variant is used on a custom board: Goldilocks Mama Bear
made by Future Electronics.
Signed-off-by: Paolo Wattebled <paolo.wattebled@savoirfairelinux.com>
Add a retained memory driver for GD32 backup SRAM.
The driver exposes the memory region defined by devicetree reg, enables
the BKPSRAM clock gate, and optionally enables a vin-supply regulator
for retention power.
Signed-off-by: Aleksandr Senin <al@meshium.net>
Platform shim for the BL602 BLE controller binary blob: IRQ
dispatch via bflb_irq_* functions, MSOFT handler for deferred context
switching, delay functions, GLB register access, and MAC address
reading via hwinfo.
Configure 8 KB exchange memory (SEAM) when BLE is enabled, reducing
usable SRAM from 176 KB to 168 KB.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Use DPPIC nodes to detect if certain SPU associated with that DPPIC
is present. NRF_SPUxxx defines are created even if SPU instances are
not present.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Use feature Kconfig instead of SoC Kconfig to determine initialization
priority as SD2PPI is not unique to only a single SoC.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add System Clock Controller for the M480 nuvoton MCU.
This only adds the base driver to setup HIRC, HXT, LIRC, LXT and
PLL. Configuring the PLL driver from a target frequency with
calculating values to best match this frequency.
Signed-off-by: Fiona Behrens <me@kloenk.dev>
With the introduction of mapped partitions, the condition for detecting
the second-stage bootloader needs to be updated.
When mapped partitions are enabled, if code-partition starts at offset
0x100 in flash0, which is mapped at 0x10000000, this means the region from
0x0 to 0x100 is occupied by the second-stage bootloader.
Since code-partition is defined as alias, this is the most stable detection
method.
The existing condition applies when mapped partitions are not used.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
After #106943, atomic C symbols moved from libkernel.a to libzephyr.a.
On chips using ATOMIC_OPERATIONS_C (no hardware atomics), this caused
functions to land in flash instead of IRAM.
Update the linker scripts for ESP32-C2/ESP8684, ESP32-C3 and ESP32-S2
to explicitly pull libzephyr.a:atomic_c.* back into IRAM.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Next-generation it51xxx SoCs support more than 256 irqs.
This change extends irq range up to 16 bit depend on
CONFIG_NUM_IRQS.
And the it8xxx2 SoC series only supports 8-bit irq
number size. Add irq type check assertion for this
series.
Tested with:
- it82xx2_evb/it8xxx2_evb/it51xxx_evb_it51526aw:
tests/drivers/gpio/gpio_basic_api
- native_sim/native:
tests/drivers/gpio/gpio_ite_it8xxx2_v2
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Move MAC address and TSEN initialization from the HCI driver into
per-SoC bflb_rf_init() implementations, matching the BL61x pattern.
This lets the HCI driver call bflb_rf_init() unconditionally.
Signed-off-by: William Markezana <william.markezana@gmail.com>
Hardware port that bridges the precompiled BLE controller blob to
Zephyr on BL61x: IRQ registration, clock gating, eFuse MAC read,
RC32M trimming, and debug output stubs.
PHY/RF initialization is in a separate bflb_rf.c so it can be shared
with the WiFi driver later.
Signed-off-by: William Markezana <william.markezana@gmail.com>
SoCs using the NXP MPU (ke1xf, k2x, k6x, k8x, s32k1) currently
program 5 boot MPU regions:
0 DEBUGGER (hardwired, covers full address space)
1 BACKGROUND_0 (0 -> SRAM_BASE-1)
2 BACKGROUND_1 (SRAM_END -> 0xFFFFFFFF)
3 FLASH_0
4 RAM_U_0
The two-region background split exists because the NXP MPU uses OR
semantics rather than priority-based precedence. When MPU_STACK_GUARD
is enabled, a single full-address-space background region would prevent
the stack guard from ever denying supervisor writes to the guard area,
so the split is necessary.
When MPU_STACK_GUARD is disabled, no such restriction applies. A single
background region covering the full address space is sufficient, reducing
boot region consumption from 5 to 4. This frees one hardware slot on
SoCs with only 8 MPU regions (e.g. MKE18F16, S32K146), which previously
left only 3 dynamic regions - insufficient to support both stack guard
and userspace simultaneously.
Remove the twr_ke18f platform_exclude from tests that were blacklisted
solely due to the region shortage:
- tests/kernel/mem_protect/mem_protect
- tests/kernel/mem_protect/protection
- tests/lib/mem_alloc
Fixes#18885
Signed-off-by: Jjateen Gundesha <jjateen97@gmail.com>
Balletto is a family of BLE 5.3 microcontrollers from Alif
Semiconductor, integrating an Arm Ethos-U55 NPU and a dedicated
network co-processor. The application core is a single Cortex-M55
running in the RTSS-HE (Real Time Subsystem - High Efficiency)
subsystem, targeting power-efficient edge AI/ML and wireless IoT
applications.
Add SoC framework support for the Balletto family, the B1 series
within the family and the AB1C1F4M51820PH0 SoC within the series.
Link: https://alifsemi.com/products/balletto/
Link: https://alifsemi.com/balletto-b1-series/
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Move the pinctrl_soc.h header from the Ensemble family directory to
a new vendor-level common directory (soc/alif/common/) to enable
sharing across all Alif Semiconductor SoC families. The pinctrl
hardware implementation is identical across Alif SoC families
(Ensemble and Balletto) and has the same pad configuration and
alternate function register layout.
No functional changes.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Currently only LPSPI1 has a clock set. This clock seems to be way
larger than the max. allowable frequency of the LPSPI clock root
input. This change sets all the LPSPI instances to a valid clock.
The LPSPI clock root is set to PLL3 PFD2, which leads to a
fPERIPH clock of 135MHz, which is allowed on the RT11xx series.
Signed-off-by: Bas van Loon <bas@arch-embedded.com>
Add new inline function entropy_get_default_device which returns
the "zephyr,entropy" device or the architectural entropy device,
if the former is not set, and use that in all places to query the
entropy device.
This allows using architectural drivers which do not have a DT
node.
Signed-off-by: Christoph Busold <cbusold@qti.qualcomm.com>
Added support for hardening decision on resume from
S2RAM by MCUboot bootloader.
Application sets additional variable to MCUBOOT_S2RAM_RESUME_MAGIC
which allows the bootloader to doublecheck.
Extended mcuboot_resume_s suture by slot_info field intended to
be used by MCUboot for recognize proper boot slot in direct-xp
mode.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Signed-off-by: Tomasz Moń <tomasz.mon@nordicsemi.no>
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
Selecting MCUX_LPTMR_TIMER directly from
/chosen/zephyr,system-timer broadens the default behavior for
any SoC DTSI that now sets the chosen node. KE1xF only
intends to use LPTMR under PM, while MCX-W7xx and i.MX95 M7
still require their SoC-specific selection rules.
Keep the generic Kconfig selection policy implicit and retain
the SoC-specific enablement rules in the MCX-W7xx and i.MX95
M7 defconfigs.
This keeps the chosen-based instance selection while avoiding
unintended system timer changes outside the narrow fix scope.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
KE1xF now provides its LPTMR system timer through the
/chosen/zephyr,system-timer property, but the SoC defconfig
still reads SYS_CLOCK_HW_CYCLES_PER_SEC from a hard-coded
lptmr0 path.
Switch the clock-frequency lookup to the chosen system timer
node so the Kconfig side stays aligned with the timer
driver chosen-based instance selection.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
For cases where there is IPC such as
openamp_rsc_table and rpmsg_service there is a need for a
shared memory region.
As part of this, validate the IPC carveout with some checks
Add validation for flash handling
Finally, add ipc_shm carveout handling for such a MPU region,
similar to how is done for other SOCs
Signed-off-by: Ben Levinsky <ben.levinsky@amd.com>
The EFM32HG (Series 0) WDOG has no IRQ support, no window mode
and no reset-disable bit.
Guard the logic with HAL feature macros and use `IF_ENABLED` with
`DT_INST_IRQ_HAS_IDX` for conditional IRQ setup.
Add the `wdog0` node to the EFM32HG device tree.
Signed-off-by: Patryk Koscik <pkoscik@antmicro.com>
CONFIG_SMP is by default already not enabled,
so there is no need to set the default to n in the
soc or board specific Kconfig.defconfig
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Add support for defining the PROTECTEMEM and SECONDARY.PROTECTEMEM
sizes in DTS. The sizes are taken from the nodes with label
'protectedmem_partition' and 'secondary_protectedmem_partition',
respectively. The existing interface for setting them via Kconfig
directly has been kept as is for backward compatibility.
Also add a dependency on secondary_partition to enabling secondary
firmware, as it is used unconditionally by the cmake to get the
start address of the secondary firmware.
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
Introduce CONFIG_RISCV_S_MODE to select Supervisor-mode execution.
Add depends on !RISCV_S_MODE to RISCV_PMP since PMP CSRs are
inaccessible from S-mode.
Add an M-mode SBI shim (reset.S + sbi.S) that configures exception
delegation, PMP, and counter access before dropping to S-mode via mret.
The shim handles SBI_SET_TIMER ecalls from S-mode and forwards MTIP to
STIP so the supervisor timer driver works without a full SBI firmware.
Introduce privilege-level abstractions in isr.S (RV_CAUSE, RV_EPC,
RV_STATUS, RV_TVAL, etc.) and update all runtime code that previously
accessed M-mode-only CSRs (mcause, mtval, mstatus, mie, mip) to use the
S-mode equivalents when CONFIG_RISCV_S_MODE is set.
ARCH_EXCEPT in kernel context uses ebreak (cause=3, Breakpoint) instead
of a direct z_riscv_fatal_error() call. In S-mode, ecall (cause=9) is
kept in M-mode for SBI and never reaches the S-mode exception handler;
a direct call with NULL esf caused the stack unwinder to crash into an
infinite fault loop. ebreak is delegated to S-mode by our medeleg
configuration; isr.S treats ebreak with t0=RV_ECALL_RUNTIME_EXCEPT the
same way M-mode treats ecall-based ARCH_EXCEPT.
Signed-off-by: Alexios Lyrakis <alexios.lyrakis@gmail.com>
Enable CONFIG_NXP_COMPRESSED_WIFI_NB_FW by default for the
nxp_m2_wifi_bt shield and RW series SoCs.
This selects compressed Wi-Fi and NBU firmware images to reduce
flash usage on supported NXP platforms.
Signed-off-by: Maochen Wang <maochen.wang@nxp.com>
