It was detected by test_sw_isr_irq_parent_table_idx in arch.interrupt:
ASSERTION FAIL [table_idx < (186 - 0)]
@ WEST_TOPDIR/zephyr/arch/common/multilevel_irq.c:91
table_idx(186) < IRQ_TABLE_SIZE(186)
NUM_IRQS was previously set to the same value as MAX_IRQ_PER_AGGREGATOR
and it didn't take into account the number of 1st level interrupts
specified by 2ND_LVL_ISR_TBL_OFFSET. In the generated __sw_isr_table,
Level 2 interrupts start at the offset specified by 2ND_LVL_ISR_TBL_OFFSET.
For PolarFire SoC, upper interrupt sources for PLIC correspond to
Bus Error Unit and Fabric Interface. They are currently not used by
platforms in Zephyr, so the previous value of NUM_IRQS hasn't caused
issues for regular applications.
As it doesn't look like an explicit memory optimization, increase NUM_IRQS
to allow kernel interrupt tests to pass.
Note:
2ND_LVL_ISR_TBL_OFFSET=13 and NUM_IRQS=199 don't include additional
48 Local Interrupts supported by cores. In total, there are
64 bits in Machine Interrupt Pending Register (mip)
which can be used to configure 1st level interrupts.
As a further extension to the platform, values could be extended to
2ND_LVL_ISR_TBL_OFFSET=64 and NUM_IRQS=250. This commit increases
NUM_IRQS by a minimal value required to pass kernel interrupt tests.
Link: https://ww1.microchip.com/downloads/aemDocuments/documents/FPGA/ProductDocuments/ReferenceManuals/PolarFire_SoC_FPGA_MSS_Technical_Reference_Manual_VC.pdf
Signed-off-by: Marek Slowinski <mslowinski@antmicro.com>
Added configuration for new audio PLL service.
Pull in new service implementation in new hal nordic.
Signed-off-by: Łukasz Stępnicki <lukasz.stepnicki@nordicsemi.no>
Enabled west flash and west erase for nRF54L20 PDK FLPR core.
Added missing reset qualifier for nRF54L20 and nRF54L09.
Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
This is the initial commit to support pinctrl driver for Renesas RZ/A3UL
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Phuc Pham <phuc.pham.xr@bp.renesas.com>
The first two partitions in padconfig mmr regions need to be unlocked for
the pinctrl driver to be able to write. However, the base addresses for the
the registers can be different across SoCs and domains. Besides, currently
this is only done for M4 and that too not in the local (M4's) view.
This patch introduces a file specifying all ctrl partition base addresses
using ifdef directives for different SoCs and variants, and unlocking them
before the kernel and drivers initialize.
Signed-off-by: Amneesh Singh <a-singh7@ti.com>
There is a configuration of the DCDC in the clock_init for the RT10xx.
The RT11xx has a kconfig flag ADJUST_DCDC to enable or disable DCDC
adjust code. This flag is now also used for the RT10xx to be able to
enable or disable the DCDC adjust code.
Signed-off-by: Adrian Bieri <adrian.bieri@loepfe.com>
In the case where more than a full tick was unannounced when
sys_clock_set_timeout() was called, the timer driver would
subtract it from the next timeout. However, this is already
done by the caller through the elapsed() function in timeout.c,
leading to the timer interrupt firing too early.
With this fix, SYS_CLOCK_TICKS_PER_SEC can be increased to the
full speed of the low frequency timer. The underlying sleeptimer
API must be called with a timeout of at least 1, and will if needed
increase the value to the minimum value required by the hardware.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Added Kconfig options to allow use of TWIM frequency
workaround in NRFX for nRF52 and nRF53.
Signed-off-by: Michał Stasiak <michal.stasiak@nordicsemi.no>
In spi loopback test, high bandrate is 16Mbps while some source of lpspi
are too low to support this bandrate. According the reference mannual,
to support 16Mbps, Input frequency at least should be 2*16MHz.
Update LPSPI input freq to maximum to get more accurate band rate
because band rate must be divisible by input freq.
Signed-off-by: Raymond Lei <raymond.lei@nxp.com>
List NEORV32 v1.11.2 as the currently supported version. No changes to the
in-tree drivers needed for the changes between v1.11.1 and v1.11.2.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
We disable power management by removing select HAS_PM. At this time
these new SoC do not have any power management code. With HAS_PM
selected the zephyr test runner will choose PM tests which fail to
build. PM support will be enabled in the future once we decide
which of the many Zephyr PM implementations we will support.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
CONFIG_TIMER_READS_ITS_FREQUENCY_AT_RUNTIME depends on
CONFIG_SYS_CLOCK_EXISTS, so CONFIG_SOC_NEORV32_READ_FREQUENCY_AT_RUNTIME
needs to depend on CONFIG_SYS_CLOCK_EXISTS for selecting it.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Due to historical reasons, there were two implementations of
R7FA4M1AB3CFM. However, the migration has been completed,
so the old one is now being removed.
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
The current default RAT configuration puts the first 512MB of
address space on top of the first 512MB of DRAM. This DRAM
can include the carveout region assigned for IPC with the
host core, for instance the M4 on AM62 uses 0x9cc00000.
Split this first translation from 0x80000000 to 0x60000000 and
0xc0000000. Shrink the 0x40000000 translation and move down
to 0x70000000. This provides the same system IP coverage without
blocking access to the first 512MB of DRAM.
While here, fix typo with leading 0 for a couple BASE_ADDR
translations, no functional change.
Signed-off-by: Andrew Davis <afd@ti.com>
This is the initial commit to support PINCTRL driver for Renesas RZ/T2L
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Signed-off-by: Hieu Nguyen <hieu.nguyen.ym@bp.renesas.com>
On ZynqMP, the RPU Cortex-R5 cores come up by default without
instruction and data caches enabled. Enable them as part of
soc_early_init_hook when CONFIG_CACHE_MANAGEMENT is enabled.
Signed-off-by: Robert Hancock <robert.hancock@calian.com>
This patch will set MMU permissions for .cold* sections
Fixes cold section execution if MMU is enabled
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
Improve naming of the scheduler and call it what it is: simple. Using
'dumb' for the default scheduler algorithm in Zephyr is a bad idea.
Signed-off-by: Anas Nashif <anas.nashif@intel.com>
A few option defaults that were so far defined in the board _defconfig
files are actually entirely SoC family (nRF54L) dependant, so it makes
much more sense to have them defined at the SoC family level in order
for all boards based on these SoCs to automatically inherit them.
Signed-off-by: Carles Cufi <carles.cufi@nordicsemi.no>
Currently, coex application is enable the mbedtls and PAS feature,
this causes BT_LONG_WQ thread to use more stack size.
Signed-off-by: Author You <author.you@nxp.com>
The part numbers for MCXC141VLH and MCXC142VFM
have all been set to MCXC141VFM, which lead to
build errors.
Signed-off-by: Maximilian Werner <maximilian.werner96@gmail.com>
This is the initial commit to support pinctrl driver for Renesas RZ/N2L
Signed-off-by: Hoang Nguyen <hoang.nguyen.jx@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
This commit aligns the value of `CONFIG_PRIVILEGED_STACK_SIZE` to the
alignment specified by the value of `XCHAL_MPU_ALIGN`, which for
`sample_controller32` is equal to 4096.
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
Protection circuit must be disabled to use NFCT antenna pins
as GPIOs. It can be done by adding nfct-pins-as-gpios to nfct
node in the devicetree in cpuapp. Node must be disabled as
NFCT is not used. In legacy platforms same property was added
to uicr node because that information was stored in UICR. In
nrf54h20 it is not part of UICR so property is part of nfct
node.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add initial support for nuvoton numaker m55m1x SoC series
including basic init and device tree source include.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
VPR (FLPR) on nRF54L series has fixed issue with sleeping so
custom CPU idle function does not need to be used there.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add support for the Octavo's OSD32MP1-BRK platform. The board uses
Octavo's OSD32MP15x SiP which integrates STM32MP157F MCU and
its SoC configuration.
Signed-off-by: Jakub Wasilewski <jwasilewski@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
MD5 and SHA1 are not supposed to be used nowadays on security context.
Some ancillary scripts in tree do use them, but for verification only -
or where externally mandated, such the SPDX tool.
This patch marks those usages as `usedforsecurity=False`, which helps
clarify intent.
Signed-off-by: Ederson de Souza <ederson.desouza@intel.com>
Update the NEORV32 SoC, peripheral drivers, and board to support NEORV32
v1.11.1. Notable changes include:
- Optional RISC-V ISA Kconfigs are now selected on the board level.
- Peripheral registers are now automatically reset in hardware, no need for
software initialization code.
- The NEORV32 GPIO controller now supports 32 pins, not 64. Interrupt
support will be submitted in a separate PR.
- Default board configuration has 64k RAM and is clocked at 18 MHz.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
Originally, when Zephyr support for the NEORV32 was introduced, the idea
was to support multiple version of the SoC in Zephyr as development on the
open-source RISC-V processor continued.
Unfortunately, this has proven to be much harder than anticipated in part
due to incompatible changes between NEORV32 versions and part due to the
added test burden of verifying all changes on many different versions and
configurations.
Going forward, Zephyr will support a given release of the NEORV32
processor.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
