drivers: pinctrl: Add support for cc23x0 pinctrl
Add support for pinctrl to cc23x0 SoC. Like for other TI SoCs, a node approach is implemented (no grouping approach). Signed-off-by: Lars Thalian Morstad <l-morstad@ti.com> Signed-off-by: Vebjorn Myklebust <v.myklebust@ti.com> Signed-off-by: Stoyan Bogdanov <sbogdanov@baylibre.com> Signed-off-by: Julien Panis <jpanis@baylibre.com>
This commit is contained in:
Vebjorn Myklebust
Benjamin Cabé
parent
d28f3b81d1
commit
9d81b74ff1
7 changed files with 397 additions and 0 deletions
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@ -21,6 +21,7 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_IMX pinctrl_imx.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_SIFIVE pinctrl_sifive.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_IOCON pinctrl_lpc_iocon.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_CC13XX_CC26XX pinctrl_cc13xx_cc26xx.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_CC23X0 pinctrl_cc23x0.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_ESP32 pinctrl_esp32.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_RV32M1 pinctrl_rv32m1.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_INFINEON_CAT1 pinctrl_ifx_cat1.c)
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@ -50,6 +50,7 @@ source "drivers/pinctrl/Kconfig.imx"
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source "drivers/pinctrl/Kconfig.sifive"
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source "drivers/pinctrl/Kconfig.lpc_iocon"
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source "drivers/pinctrl/Kconfig.cc13xx_cc26xx"
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source "drivers/pinctrl/Kconfig.cc23x0"
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source "drivers/pinctrl/Kconfig.esp32"
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source "drivers/pinctrl/Kconfig.rv32m1"
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source "drivers/pinctrl/Kconfig.ifx_cat1"
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11
drivers/pinctrl/Kconfig.cc23x0
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11
drivers/pinctrl/Kconfig.cc23x0
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@ -0,0 +1,11 @@
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# Copyright (c) 2024 Texas Instruments Incorporated
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# Copyright (c) 2024 BayLibre, SAS
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#
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# SPDX-License-Identifier: Apache-2.0
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config PINCTRL_CC23X0
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bool "TI SimpleLink CC23X0 pinctrl driver"
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default y
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depends on DT_HAS_TI_CC23X0_PINCTRL_ENABLED
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help
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Enable the TI SimpleLink CC23X0 pinctrl driver
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36
drivers/pinctrl/pinctrl_cc23x0.c
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36
drivers/pinctrl/pinctrl_cc23x0.c
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@ -0,0 +1,36 @@
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/*
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* Copyright (c) 2024 Texas Instruments Incorporated
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* Copyright (c) 2024 BayLibre, SAS
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ti_cc23x0_pinctrl
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#include <zephyr/drivers/pinctrl.h>
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#include <inc/hw_types.h>
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#define IOC_BASE_REG DT_REG_ADDR(DT_NODELABEL(pinctrl))
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#define IOC_BASE_PIN_REG 0x00000100
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#define IOC_ADDR(index) (IOC_BASE_REG + IOC_BASE_PIN_REG + (sizeof(uint32_t) * (index)))
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static int pinctrl_cc23x0_set(uint32_t pin, uint32_t func, uint32_t mode)
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{
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uint32_t iocfg_reg = IOC_ADDR(pin);
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HWREG(iocfg_reg) = mode | func;
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return 0;
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}
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
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{
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ARG_UNUSED(reg);
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for (uint8_t i = 0U; i < pin_cnt; i++) {
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pinctrl_cc23x0_set(pins[i].pin, pins[i].iofunc, pins[i].iomode);
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}
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return 0;
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}
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62
dts/bindings/pinctrl/ti,cc23x0-pinctrl.yaml
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62
dts/bindings/pinctrl/ti,cc23x0-pinctrl.yaml
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@ -0,0 +1,62 @@
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# Copyright (c) 2024 Texas Instruments Incorporated
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# Copyright (c) 2024 BayLibre, SAS
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# SPDX-License-Identifier: Apache-2.0
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description: |
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TI SimpleLink CC23X0 pinctrl node.
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Device pin configuration should be placed in the child nodes of this node.
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Populate the 'pinmux' field with a pair consisting of a pin number and its IO
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functions.
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The node has the 'pinctrl' node label set in your SoC's devicetree,
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so you can modify it like this:
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&pinctrl {
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/* your modifications go here */
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};
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All device pin configurations should be placed in child nodes of the
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'pinctrl' node, as in the i2c0 example shown at the end.
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Here is a list of
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supported standard pin properties:
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- bias-disable: Disable pull-up/down.
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- bias-pull-down: Enable pull-down resistor.
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- bias-pull-up: Enable pull-up resistor.
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- drive-open-drain: Output driver is open-drain.
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- drive-open-source: Output driver is open-source.
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- input-enable: enable input.
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- input-schmitt-enable: enable input schmitt circuit.
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compatible: "ti,cc23x0-pinctrl"
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include: base.yaml
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properties:
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reg:
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required: true
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child-binding:
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description: |
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This binding gives a base representation of the CC23X0
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pins configuration.
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include:
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- name: pincfg-node.yaml
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property-allowlist:
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- bias-disable
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- bias-pull-down
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- bias-pull-up
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- drive-open-drain
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- drive-open-source
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- input-enable
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- input-schmitt-enable
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properties:
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pinmux:
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required: true
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type: array
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description: |
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CC23X0 pin's configuration (IO pin, IO function).
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227
include/zephyr/dt-bindings/pinctrl/cc23x0-pinctrl.h
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227
include/zephyr/dt-bindings/pinctrl/cc23x0-pinctrl.h
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@ -0,0 +1,227 @@
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/*
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* Copyright (c) 2024 Texas Instruments Incorporated
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* Copyright (c) 2024 BayLibre, SAS
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef CC23X0_PINCTRL_COMMON_H_
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#define CC23X0_PINCTRL_COMMON_H_
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/*
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* The whole TI CC23X0 pin configuration information is encoded in a 32-bit
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* bitfield organized as follow:
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*
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* - 31: Reserved
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* - 30: Input hysteresis
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* - 29: Input capability of IO
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* - 28..27: Reserved
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* - 26..24: IO mode
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* - 23..22: Reserved
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* - 21..20: Wakeup configuration from shutdown
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* - 19: Reserved
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* - 18: Wakeup capability from standby
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* - 17..16: Edge detection configuration
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* - 15: Reserved
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* - 14..13: Pull control
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* - 12..3: Reserved
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* - 2..0: Function configuration
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*/
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/* TI CC23X0 function configuration */
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#define IOC_PORTCFG_BASE 0U
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#define IOC_PORTCFG_PFUNC1 1U
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#define IOC_PORTCFG_PFUNC2 2U
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#define IOC_PORTCFG_PFUNC3 3U
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#define IOC_PORTCFG_PFUNC4 4U
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#define IOC_PORTCFG_PFUNC5 5U
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#define IOC_PORTCFG_ANA 6U
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#define IOC_PORTCFG_DTB 7U
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/* TI CC23X0 peripheral pin mapping */
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#define DIO0_GPIO0 IOC_PORTCFG_BASE
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#define DIO0_SPI0_CSN IOC_PORTCFG_PFUNC1
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#define DIO0_I2C0_SDA IOC_PORTCFG_PFUNC2
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#define DIO0_T3_C2 IOC_PORTCFG_PFUNC3
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#define DIO0_ADC5 IOC_PORTCFG_ANA
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#define DIO1_GPIO1 IOC_PORTCFG_BASE
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#define DIO1_T3_C1 IOC_PORTCFG_PFUNC1
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#define DIO1_LRFD7 IOC_PORTCFG_PFUNC2
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#define DIO1_T1_F IOC_PORTCFG_PFUNC3
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#define DIO1_UART0_RTS IOC_PORTCFG_PFUNC4
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#define DIO1_ADC4 IOC_PORTCFG_ANA
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#define DIO1_DTB2 IOC_PORTCFG_DTB
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#define DIO2_GPIO2 IOC_PORTCFG_BASE
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#define DIO2_T0_PE IOC_PORTCFG_PFUNC1
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#define DIO2_T2_C1N IOC_PORTCFG_PFUNC2
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#define DIO2_UART0_CTS IOC_PORTCFG_PFUNC3
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#define DIO2_ADC3 IOC_PORTCFG_ANA
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#define DIO3_GPIO3 IOC_PORTCFG_BASE
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#define DIO3_LFCI IOC_PORTCFG_PFUNC1
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#define DIO3_T0_C1N IOC_PORTCFG_PFUNC2
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#define DIO3_LRFD0 IOC_PORTCFG_PFUNC3
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#define DIO3_T3_C1 IOC_PORTCFG_PFUNC4
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#define DIO3_T1_C2 IOC_PORTCFG_PFUNC5
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#define DIO3_LFXT_P IOC_PORTCFG_ANA
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#define DIO3_DTB7 IOC_PORTCFG_DTB
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#define DIO4_GPIO4 IOC_PORTCFG_BASE
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#define DIO4_T0_C2N IOC_PORTCFG_PFUNC1
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#define DIO4_UART0_TXD IOC_PORTCFG_PFUNC2
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#define DIO4_LRFD1 IOC_PORTCFG_PFUNC3
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#define DIO4_SPI0_MOSI IOC_PORTCFG_PFUNC4
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#define DIO4_T0_C2 IOC_PORTCFG_PFUNC5
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#define DIO4_LFXT_N IOC_PORTCFG_ANA
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#define DIO4_DTB8 IOC_PORTCFG_DTB
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#define DIO5_GPIO5 IOC_PORTCFG_BASE
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#define DIO5_T2_C2 IOC_PORTCFG_PFUNC1
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#define DIO5_LRFD6 IOC_PORTCFG_PFUNC3
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#define DIO5_ADC2 IOC_PORTCFG_ANA
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#define DIO6_GPIO6 IOC_PORTCFG_BASE
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#define DIO6_SPI0_CSN IOC_PORTCFG_PFUNC1
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#define DIO6_I2C0_SCL IOC_PORTCFG_PFUNC2
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#define DIO6_T1_C2 IOC_PORTCFG_PFUNC3
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#define DIO6_LRFD2 IOC_PORTCFG_PFUNC4
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#define DIO6_UART0_TXD IOC_PORTCFG_PFUNC5
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#define DIO6_ADC1_AREFP IOC_PORTCFG_ANA
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#define DIO6_DTB6 IOC_PORTCFG_DTB
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#define DIO7_GPIO7 IOC_PORTCFG_BASE
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#define DIO7_T3_C1 IOC_PORTCFG_PFUNC1
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#define DIO7_LRFD4 IOC_PORTCFG_PFUNC3
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#define DIO7_ADC0_AREFM IOC_PORTCFG_ANA
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#define DIO8_GPIO8 IOC_PORTCFG_BASE
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#define DIO8_SPI0_SCLK IOC_PORTCFG_PFUNC1
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#define DIO8_UART0_RTS IOC_PORTCFG_PFUNC2
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#define DIO8_T1_C0N IOC_PORTCFG_PFUNC3
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#define DIO8_I2C0_SDA IOC_PORTCFG_PFUNC4
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#define DIO8_T0_C0N IOC_PORTCFG_PFUNC5
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#define DIO8_DTB3 IOC_PORTCFG_DTB
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#define DIO9_GPIO9 IOC_PORTCFG_BASE
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#define DIO9_T3_C0 IOC_PORTCFG_PFUNC1
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#define DIO9_LRFD3 IOC_PORTCFG_PFUNC3
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#define DIO10_GPIO10 IOC_PORTCFG_BASE
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#define DIO10_LPC0 IOC_PORTCFG_PFUNC1
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#define DIO10_T2_PE IOC_PORTCFG_PFUNC2
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#define DIO10_T3_C0N IOC_PORTCFG_PFUNC3
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#define DIO11_GPIO11 IOC_PORTCFG_BASE
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#define DIO11_SPI0_CSN IOC_PORTCFG_PFUNC1
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#define DIO11_T1_C2N IOC_PORTCFG_PFUNC2
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#define DIO11_T0_C0 IOC_PORTCFG_PFUNC3
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#define DIO11_LRFD0 IOC_PORTCFG_PFUNC4
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#define DIO11_SPI0_MISO IOC_PORTCFG_PFUNC5
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#define DIO11_DTB9 IOC_PORTCFG_DTB
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#define DIO12_GPIO12 IOC_PORTCFG_BASE
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#define DIO12_SPI0_MISO IOC_PORTCFG_PFUNC1
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#define DIO12_SPI0_MOSI IOC_PORTCFG_PFUNC2
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#define DIO12_UART0_RXD IOC_PORTCFG_PFUNC3
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#define DIO12_T1_C1 IOC_PORTCFG_PFUNC4
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#define DIO12_I2C0_SDA IOC_PORTCFG_PFUNC5
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#define DIO12_DTB13 IOC_PORTCFG_DTB
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#define DIO13_GPIO13 IOC_PORTCFG_BASE
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#define DIO13_SPI0_MISO IOC_PORTCFG_PFUNC1
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#define DIO13_SPI0_MOSI IOC_PORTCFG_PFUNC2
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#define DIO13_UART0_TXD IOC_PORTCFG_PFUNC3
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#define DIO13_T0_C0N IOC_PORTCFG_PFUNC4
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#define DIO13_T1_F IOC_PORTCFG_PFUNC5
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#define DIO13_DTB4 IOC_PORTCFG_DTB
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#define DIO14_GPIO14 IOC_PORTCFG_BASE
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#define DIO14_T3_C2 IOC_PORTCFG_PFUNC1
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#define DIO14_T1_C2N IOC_PORTCFG_PFUNC2
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#define DIO14_LRFD5 IOC_PORTCFG_PFUNC3
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#define DIO14_T1_F IOC_PORTCFG_PFUNC4
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#define DIO15_GPIO15 IOC_PORTCFG_BASE
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#define DIO15_UART0_RXD IOC_PORTCFG_PFUNC1
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#define DIO15_T2_C0N IOC_PORTCFG_PFUNC2
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#define DIO15_CKMIN IOC_PORTCFG_PFUNC3
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#define DIO16_GPIO16 IOC_PORTCFG_BASE
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#define DIO16_SPI0_MOSI IOC_PORTCFG_PFUNC1
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#define DIO16_UART0_RXD IOC_PORTCFG_PFUNC2
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#define DIO16_I2C0_SDA IOC_PORTCFG_PFUNC3
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#define DIO16_T1_C2 IOC_PORTCFG_PFUNC4
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#define DIO16_T1_C0N IOC_PORTCFG_PFUNC5
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#define DIO16_DTB10 IOC_PORTCFG_DTB
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#define DIO17_GPIO17 IOC_PORTCFG_BASE
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#define DIO17_SPI0_SCLK IOC_PORTCFG_PFUNC1
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#define DIO17_UART0_TXD IOC_PORTCFG_PFUNC2
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#define DIO17_I2C0_SCL IOC_PORTCFG_PFUNC3
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#define DIO17_T1_C1N IOC_PORTCFG_PFUNC4
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#define DIO17_T0_C2 IOC_PORTCFG_PFUNC5
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#define DIO17_DTB11 IOC_PORTCFG_DTB
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#define DIO18_GPIO18 IOC_PORTCFG_BASE
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#define DIO18_T3_C0 IOC_PORTCFG_PFUNC1
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#define DIO18_LPC0 IOC_PORTCFG_PFUNC2
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#define DIO18_UART0_TXD IOC_PORTCFG_PFUNC3
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#define DIO18_SPI0_SCLK IOC_PORTCFG_PFUNC4
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#define DIO18_DTB12 IOC_PORTCFG_DTB
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#define DIO19_GPIO19 IOC_PORTCFG_BASE
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#define DIO19_T3_C1 IOC_PORTCFG_PFUNC1
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#define DIO19_T2_PE IOC_PORTCFG_PFUNC2
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#define DIO19_SPI0_MOSI IOC_PORTCFG_PFUNC4
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#define DIO19_DTB0 IOC_PORTCFG_DTB
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#define DIO20_GPIO20 IOC_PORTCFG_BASE
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#define DIO20_LPC0 IOC_PORTCFG_PFUNC1
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#define DIO20_UART0_TXD IOC_PORTCFG_PFUNC2
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#define DIO20_UART0_RXD IOC_PORTCFG_PFUNC3
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#define DIO20_T1_C0 IOC_PORTCFG_PFUNC4
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#define DIO20_SPI0_MISO IOC_PORTCFG_PFUNC5
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#define DIO20_ADC11 IOC_PORTCFG_ANA
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#define DIO20_DTB14 IOC_PORTCFG_DTB
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#define DIO21_GPIO21 IOC_PORTCFG_BASE
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#define DIO21_UART0_CTS IOC_PORTCFG_PFUNC1
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#define DIO21_T1_C1N IOC_PORTCFG_PFUNC2
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#define DIO21_T0_C1 IOC_PORTCFG_PFUNC3
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#define DIO21_SPI0_MISO IOC_PORTCFG_PFUNC4
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#define DIO21_LRFD1 IOC_PORTCFG_PFUNC5
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#define DIO21_ADC10_LPCP IOC_PORTCFG_ANA
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#define DIO21_DTB15 IOC_PORTCFG_DTB
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#define DIO22_GPIO22 IOC_PORTCFG_BASE
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#define DIO22_T2_C0 IOC_PORTCFG_PFUNC1
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#define DIO22_UART0_RXD IOC_PORTCFG_PFUNC2
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#define DIO22_T3_C1N IOC_PORTCFG_PFUNC3
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#define DIO22_ADC9 IOC_PORTCFG_ANA
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#define DIO22_DTB1 IOC_PORTCFG_DTB
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#define DIO23_GPIO23 IOC_PORTCFG_BASE
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#define DIO23_T2_C1 IOC_PORTCFG_PFUNC1
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#define DIO23_T3_C2N IOC_PORTCFG_PFUNC3
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#define DIO23_ADC8_LPCP_LPCM IOC_PORTCFG_ANA
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#define DIO24_GPIO24 IOC_PORTCFG_BASE
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#define DIO24_SPI0_SCLK IOC_PORTCFG_PFUNC1
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#define DIO24_T1_C0 IOC_PORTCFG_PFUNC2
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#define DIO24_T3_C0 IOC_PORTCFG_PFUNC3
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#define DIO24_T0_PE IOC_PORTCFG_PFUNC4
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#define DIO24_I2C0_SCL IOC_PORTCFG_PFUNC5
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#define DIO24_ADC7_LPCP_LPCM IOC_PORTCFG_ANA
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#define DIO24_DTB5 IOC_PORTCFG_DTB
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#define DIO25_GPIO25 IOC_PORTCFG_BASE
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#define DIO25_SPI0_MISO IOC_PORTCFG_PFUNC1
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#define DIO25_I2C0_SCL IOC_PORTCFG_PFUNC2
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#define DIO25_T2_C2N IOC_PORTCFG_PFUNC3
|
||||
#define DIO25_ADC6 IOC_PORTCFG_ANA
|
||||
|
||||
#endif /* CC23X0_PINCTRL_COMMON_H_ */
|
||||
59
soc/ti/simplelink/cc23x0/pinctrl_soc.h
Normal file
59
soc/ti/simplelink/cc23x0/pinctrl_soc.h
Normal file
|
|
@ -0,0 +1,59 @@
|
|||
/*
|
||||
* Copyright (c) 2024 Texas Instruments Incorporated
|
||||
* Copyright (c) 2024 BayLibre, SAS
|
||||
*
|
||||
* SPDX-License-Identifier: Apache-2.0
|
||||
*/
|
||||
|
||||
#ifndef TI_SIMPLELINK_CC23X0_SOC_PINCTRL_H_
|
||||
#define TI_SIMPLELINK_CC23X0_SOC_PINCTRL_H_
|
||||
|
||||
#include <zephyr/types.h>
|
||||
|
||||
/* IO enabling/disabling */
|
||||
#define IOC_INPUT_ENABLE BIT(29)
|
||||
#define IOC_INPUT_DISABLE 0U
|
||||
#define IOC_HYST_ENABLE BIT(30)
|
||||
#define IOC_HYST_DISABLE 0U
|
||||
|
||||
/* IO modes */
|
||||
#define IOC_IOMODE_NORMAL 0U
|
||||
#define IOC_IOMODE_INV BIT(24)
|
||||
#define IOC_IOMODE_OPEN_DRAIN_NORMAL BIT(25)
|
||||
#define IOC_IOMODE_OPEN_DRAIN_INV GENMASK(25, 24)
|
||||
#define IOC_IOMODE_OPEN_SRC_NORMAL BIT(26)
|
||||
#define IOC_IOMODE_OPEN_SRC_INV (BIT(26) | BIT(24))
|
||||
|
||||
/* IO pull */
|
||||
#define IOC_NO_IOPULL 0U
|
||||
#define IOC_IOPULL_UP BIT(14)
|
||||
#define IOC_IOPULL_DOWN BIT(13)
|
||||
|
||||
typedef struct pinctrl_soc_pin {
|
||||
uint32_t pin;
|
||||
uint32_t iofunc;
|
||||
uint32_t iomode;
|
||||
} pinctrl_soc_pin_t;
|
||||
|
||||
/* Convert DT flags to SoC flags */
|
||||
#define CC23X0_PIN_FLAGS(node_id) \
|
||||
(DT_PROP(node_id, bias_pull_up) * IOC_IOPULL_UP | \
|
||||
DT_PROP(node_id, bias_pull_down) * IOC_IOPULL_DOWN | \
|
||||
DT_PROP(node_id, bias_disable) * IOC_NO_IOPULL | \
|
||||
DT_PROP(node_id, drive_open_drain) * IOC_IOMODE_OPEN_DRAIN_NORMAL | \
|
||||
DT_PROP(node_id, drive_open_source) * IOC_IOMODE_OPEN_SRC_NORMAL | \
|
||||
DT_PROP(node_id, input_enable) * IOC_INPUT_ENABLE | \
|
||||
DT_PROP(node_id, input_schmitt_enable) * IOC_HYST_ENABLE)
|
||||
|
||||
#define CC23X0_DT_PIN(node_id) \
|
||||
{.pin = DT_PROP_BY_IDX(node_id, pinmux, 0), \
|
||||
.iofunc = DT_PROP_BY_IDX(node_id, pinmux, 1), \
|
||||
.iomode = CC23X0_PIN_FLAGS(node_id)},
|
||||
|
||||
#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \
|
||||
CC23X0_DT_PIN(DT_PROP_BY_IDX(node_id, prop, idx))
|
||||
|
||||
#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
|
||||
{DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT)}
|
||||
|
||||
#endif /* TI_SIMPLELINK_CC23X0_SOC_PINCTRL_H_ */
|
||||
Loading…
Add table
Add a link
Reference in a new issue