soc: silabs: Introduce new SoC SiWG917
Introduce minimal support for Silicon Labs SiWx91x family. SiWx91x provide many device and especially Bluetooth and Wifi connectivity. This patch prepare Zephyr to receive further drivers. Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
This commit is contained in:
parent
ffb1c0de61
commit
aac0b343b5
17 changed files with 500 additions and 3 deletions
115
dts/arm/silabs/siwg917.dtsi
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115
dts/arm/silabs/siwg917.dtsi
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@ -0,0 +1,115 @@
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/*
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* Copyright (c) 2024-2025 Silicon Laboratories Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <zephyr/dt-bindings/clock/silabs/siwx91x-clock.h>
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/ {
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chosen {
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zephyr,flash = &flash0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-m4f";
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reg = <0>;
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};
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};
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sram0: memory@0 {
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compatible = "mmio-sram";
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reg = <0x00000000 DT_SIZE_K(191)>;
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};
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flash0: flash@8202000 {
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compatible = "soc-nv-flash";
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reg = <0x8202000 DT_SIZE_K(2040)>;
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write-block-size = <1>;
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erase-block-size = <4096>;
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};
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soc {
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clock0: clock@46000000 {
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compatible = "silabs,siwx91x-clock";
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reg = <0x46000000 0x100>,
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<0x46000800 0x100>,
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<0x24041400 0x100>,
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<0x24048000 0x200>;
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#clock-cells = <1>;
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status = "okay";
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};
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ulpuart: uart@24041800 {
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compatible = "ns16550";
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reg = <0x24041800 0x1000>;
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interrupts = <12 0>;
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reg-shift = <2>;
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clocks = <&clock0 SIWX91X_CLK_ULP_UART>;
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current-speed = <115200>;
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status = "disabled";
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};
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uart1: uart@44000000 {
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compatible = "ns16550";
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reg = <0x44000000 0x1000>;
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interrupts = <38 0>;
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reg-shift = <2>;
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clocks = <&clock0 SIWX91X_CLK_UART1>;
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current-speed = <115200>;
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status = "disabled";
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};
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uart2: uart@45020000 {
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compatible = "ns16550";
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reg = <0x45020000 0x1000>;
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interrupts = <39 0>;
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reg-shift = <2>;
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clocks = <&clock0 SIWX91X_CLK_UART2>;
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current-speed = <115200>;
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status = "disabled";
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};
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ulpi2c: i2c@24040000 {
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compatible = "snps,designware-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x24040000 0x100>;
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interrupts = <13 0>;
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interrupt-names = "i2c2";
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clocks = <&clock0 SIWX91X_CLK_ULP_I2C>;
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status = "disabled";
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};
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i2c0: i2c@44010000 {
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compatible = "snps,designware-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x44010000 0x100>;
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interrupts = <42 0>;
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interrupt-names = "i2c0";
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clocks = <&clock0 SIWX91X_CLK_I2C0>;
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status = "disabled";
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};
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i2c1: i2c@47040000 {
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compatible = "snps,designware-i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x47040000 0x100>;
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interrupts = <61 0>;
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interrupt-names = "i2c1";
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clocks = <&clock0 SIWX91X_CLK_I2C1>;
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status = "disabled";
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};
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <6>;
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};
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20
dts/arm/silabs/siwg917m111mgtba.dtsi
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20
dts/arm/silabs/siwg917m111mgtba.dtsi
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@ -0,0 +1,20 @@
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/*
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* Copyright (c) 2023 Antmicro
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* Copyright (c) 2024 Silicon Laboratories Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <silabs/siwg917.dtsi>
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/ {
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soc {
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compatible = "silabs,siwg917m111mgtba", "silabs,siwg917",
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"silabs,siwx91x", "simple-bus";
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};
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};
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&flash0 {
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reg = <0x08202000 DT_SIZE_K(2048-8)>;
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};
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@ -1,9 +1,11 @@
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# SPDX-License-Identifier: Apache-2.0
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# Copyright (c) 2017 Christian Taedcke
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add_subdirectory(common)
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zephyr_include_directories(${SOC_FAMILY})
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zephyr_include_directories(${SOC_FAMILY}/${SOC_SERIES})
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add_subdirectory_ifdef(CONFIG_SOC_FAMILY_SILABS_S2 silabs_s2)
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add_subdirectory_ifdef(CONFIG_SOC_SERIES_SIM3U silabs_sim3/sim3u)
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add_subdirectory(common)
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add_subdirectory_ifdef(CONFIG_SOC_FAMILY_SILABS_S2 silabs_s2)
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add_subdirectory_ifdef(CONFIG_SOC_FAMILY_SILABS_SIWX91X silabs_siwx91x)
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add_subdirectory_ifdef(CONFIG_SOC_SERIES_SIM3U silabs_sim3/sim3u)
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@ -5,6 +5,7 @@ config SOC_FAMILY
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default "silabs_s0" if SOC_FAMILY_SILABS_S0
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default "silabs_s1" if SOC_FAMILY_SILABS_S1
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default "silabs_s2" if SOC_FAMILY_SILABS_S2
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default "silabs_siwx91x" if SOC_FAMILY_SILABS_SIWX91X
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default "silabs_sim3" if SOC_FAMILY_SILABS_SIM3
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rsource "*/Kconfig.soc"
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14
soc/silabs/silabs_siwx91x/CMakeLists.txt
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14
soc/silabs/silabs_siwx91x/CMakeLists.txt
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# Copyright (c) 2024 Silicon Laboratories Inc.
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# SPDX-License-Identifier: Apache-2.0
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add_subdirectory(siwg917)
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# Necessary to not overwrite NWP Firmware
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math(EXPR FLASH_LOAD_ADDRESS "(${CONFIG_FLASH_BASE_ADDRESS}) + (${CONFIG_FLASH_LOAD_OFFSET})")
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set_property(GLOBAL APPEND PROPERTY extra_post_build_commands
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COMMAND ${PYTHON_EXECUTABLE} ${CMAKE_CURRENT_SOURCE_DIR}/siwx91x_isp_prepare.py
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--load-addr ${FLASH_LOAD_ADDRESS}
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${KERNEL_BIN_NAME}
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${KERNEL_BIN_NAME}.rps
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)
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11
soc/silabs/silabs_siwx91x/Kconfig
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11
soc/silabs/silabs_siwx91x/Kconfig
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# Copyright (c) 2023 Antmicro
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# Copyright (c) 2024 Silicon Laboratories Inc.
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# SPDX-License-Identifier: Apache-2.0
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config SOC_FAMILY_SILABS_SIWX91X
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select ARM
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select CPU_CORTEX_M4
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select CPU_HAS_FPU
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select CPU_HAS_ARM_MPU
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select HAS_SILABS_WISECONNECT
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select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
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39
soc/silabs/silabs_siwx91x/Kconfig.defconfig
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39
soc/silabs/silabs_siwx91x/Kconfig.defconfig
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# Copyright (c) 2024 Silicon Laboratories Inc.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_FAMILY_SILABS_SIWX91X
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config WISECONNECT_NETWORK_STACK
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bool
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select CMSIS_RTOS_V2
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select POLL
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select DYNAMIC_THREAD
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select THREAD_NAME
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select THREAD_STACK_INFO
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select THREAD_MONITOR
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select INIT_STACKS
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if WISECONNECT_NETWORK_STACK
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# WiseConnect create threads with realtime priority. Default (10kHz) clock tick
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# prevent proper use of the system with these threads.
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config SYS_CLOCK_TICKS_PER_SEC
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default 1024
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config NUM_PREEMPT_PRIORITIES
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default 56
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config CMSIS_V2_THREAD_DYNAMIC_MAX_COUNT
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default 2
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config CMSIS_V2_THREAD_DYNAMIC_STACK_SIZE
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default 1024
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config CMSIS_V2_THREAD_MAX_STACK_SIZE
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default 2048
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endif # WISECONNECT_NETWORK_STACK
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rsource "*/Kconfig.defconfig"
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endif # SOC_FAMILY_SILABS_SIWX91X
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7
soc/silabs/silabs_siwx91x/Kconfig.soc
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7
soc/silabs/silabs_siwx91x/Kconfig.soc
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# Copyright (c) 2023 Antmicro
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# SPDX-License-Identifier: Apache-2.0
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config SOC_FAMILY_SILABS_SIWX91X
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bool
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rsource "*/Kconfig.soc"
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6
soc/silabs/silabs_siwx91x/siwg917/CMakeLists.txt
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6
soc/silabs/silabs_siwx91x/siwg917/CMakeLists.txt
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# Copyright (c) 2024 Silicon Laboratories Inc.
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# SPDX-License-Identifier: Apache-2.0
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zephyr_sources_ifdef(CONFIG_SOC_SERIES_SIWG917 soc.c)
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set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")
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6
soc/silabs/silabs_siwx91x/siwg917/Kconfig
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6
soc/silabs/silabs_siwx91x/siwg917/Kconfig
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# Copyright (c) 2023 Antmicro
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# Copyright (c) 2024 Silicon Laboratories Inc.
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_SIWG917
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select SOC_EARLY_INIT_HOOK
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12
soc/silabs/silabs_siwx91x/siwg917/Kconfig.defconfig
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12
soc/silabs/silabs_siwx91x/siwg917/Kconfig.defconfig
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# Copyright (c) 2024 Silicon Laboratories Inc.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_SIWG917
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config NUM_IRQS
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default 99
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config BUILD_OUTPUT_HEX
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default y
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endif
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21
soc/silabs/silabs_siwx91x/siwg917/Kconfig.soc
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21
soc/silabs/silabs_siwx91x/siwg917/Kconfig.soc
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# Copyright (c) 2024 Silicon Laboratories Inc.
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_SIWG917
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bool
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select SOC_FAMILY_SILABS_SIWX91X
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help
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SiWG917 Series MCU
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config SOC_PART_NUMBER_SIWG917M111MGTBA
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bool
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select SOC_SERIES_SIWG917
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config SOC_SERIES
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default "siwg917" if SOC_SERIES_SIWG917
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config SOC
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default "siwg917m111mgtba" if SOC_PART_NUMBER_SIWG917M111MGTBA
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config SOC_PART_NUMBER
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default "SIWG917M111MGTBA" if SOC_PART_NUMBER_SIWG917M111MGTBA
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14
soc/silabs/silabs_siwx91x/siwg917/linker.ld
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14
soc/silabs/silabs_siwx91x/siwg917/linker.ld
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/*
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* Copyright (c) 2023 Antmicro
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* Copyright (c) 2024 Silicon Laboratories Inc.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/arch/arm/cortex_m/scripts/linker.ld>
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SECTIONS
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{
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.common_tcm_code :
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{
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*(.common_tcm_code*)
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} > FLASH
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}
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21
soc/silabs/silabs_siwx91x/siwg917/soc.c
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21
soc/silabs/silabs_siwx91x/siwg917/soc.c
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/*
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* Copyright (c) 2023 Antmicro
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* Copyright (c) 2024 Silicon Laboratories Inc.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <zephyr/init.h>
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#include <zephyr/kernel.h>
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#include <zephyr/device.h>
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#include <zephyr/sw_isr_table.h>
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#include "em_device.h"
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void soc_early_init_hook(void)
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{
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SystemInit();
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}
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/* SiWx917's bootloader requires IRQn 32 to hold payload's entry point address. */
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extern void z_arm_reset(void);
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Z_ISR_DECLARE_DIRECT(32, 0, z_arm_reset);
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10
soc/silabs/silabs_siwx91x/siwg917/soc.h
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10
soc/silabs/silabs_siwx91x/siwg917/soc.h
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/*
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* Copyright (c) 2024 Silicon Laboratories Inc.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef SIWG917_SOC_H
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#define SIWG917_SOC_H
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#include "si91x_device.h"
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#endif
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193
soc/silabs/silabs_siwx91x/siwx91x_isp_prepare.py
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193
soc/silabs/silabs_siwx91x/siwx91x_isp_prepare.py
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#!/usr/bin/env python3
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#
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# Copyright (c) 2023 Antmicro
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# Copyright (c) 2024 Silicon Laboratories Inc.
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#
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# SPDX-License-Identifier: Apache-2.0
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import argparse
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import struct
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import sys
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import intelhex
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# For reference:
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# width=32 poly=0xd95eaae5 init=0 refin=true refout=true xorout=0
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def create_table() -> list[int]:
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crc_table = [0] * 256
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for b in range(256):
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register = b
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for _ in range(8):
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lsb = register & 1
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register >>= 1
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if lsb:
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# Reflected polynomial: 0xd95eaae5
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register ^= 0xA7557A9B
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crc_table[b] = register
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return crc_table
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def calc_crc32(data: bytes) -> int:
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crc_table = create_table()
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register = 0
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for b in data:
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register = crc_table[(b ^ register) & 0xFF] ^ (register >> 8)
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return register
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def calc_checksum(data: bytes | bytearray, size: int, prev_sum: int) -> int:
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# Truncate
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data = data[:size]
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# Zero-pad data to mul of 4 bytes
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nzeros = ((len(data) + 3) // 4 * 4) - len(data)
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data += b"\0" * nzeros
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# Reinterpret data as LE u32
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ints = list(x[0] for x in struct.iter_unpack("<I", data))
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# Sum
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chk = prev_sum + sum(ints)
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# Convert to u32 and account each overflow as 1"s complement addition
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chk = (chk & 0xFFFFFFFF) + (chk >> 32)
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chk = (~chk) & 0xFFFFFFFF
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return chk
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def set_bits(x: int, off: int, size: int, field: int) -> int:
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field = int(field)
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mask = ((1 << size) - 1) << off
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x &= ~mask
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x |= (field << off) & mask
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return x
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def get_bootload_entry(
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ctrl_len: int = 0,
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ctrl_reserved: int = 0,
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ctrl_spi_32bitmode: bool = False,
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ctrl_release_ta_softreset: bool = False,
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ctrl_start_from_rom_pc: bool = False,
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ctrl_spi_8bitmode: bool = False,
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ctrl_last_entry: bool = True,
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dest_addr: int = 0,
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) -> bytes:
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# Format bootload_entry struct
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ctrl = 0
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ctrl = set_bits(ctrl, 0, 24, ctrl_len)
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ctrl = set_bits(ctrl, 24, 3, ctrl_reserved)
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ctrl = set_bits(ctrl, 27, 1, ctrl_spi_32bitmode)
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ctrl = set_bits(ctrl, 28, 1, ctrl_release_ta_softreset)
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ctrl = set_bits(ctrl, 29, 1, ctrl_start_from_rom_pc)
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ctrl = set_bits(ctrl, 30, 1, ctrl_spi_8bitmode)
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ctrl = set_bits(ctrl, 31, 1, ctrl_last_entry)
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return struct.pack("<II", ctrl, dest_addr)
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def get_bootload_ds(offset: int, ivt_offset: int, fixed_pattern: int = 0x5AA5) -> bytes:
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ret = b""
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ret += int(fixed_pattern).to_bytes(2, "little")
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ret += int(offset).to_bytes(2, "little")
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ret += int(ivt_offset).to_bytes(4, "little")
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for i in range(7):
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||||
ret += get_bootload_entry(ctrl_last_entry=i == 0)
|
||||
return ret
|
||||
|
||||
|
||||
def get_fwupreq(flash_location: int, image_size: int) -> bytes:
|
||||
# Field values
|
||||
cflags = 1
|
||||
sha_type = 0
|
||||
magic_no = 0x900D900D
|
||||
fw_version = 0
|
||||
# Initially CRC value is set to 0, then the CRC is calculated on the
|
||||
# whole image (including fwupreq header), and injected here
|
||||
crc = 0
|
||||
mic = [0, 0, 0, 0]
|
||||
counter = 0
|
||||
rsvd = [0, 0, 0, 0, magic_no]
|
||||
# Format
|
||||
ret = b""
|
||||
ret += cflags.to_bytes(2, "little")
|
||||
ret += sha_type.to_bytes(2, "little")
|
||||
ret += magic_no.to_bytes(4, "little")
|
||||
ret += image_size.to_bytes(4, "little")
|
||||
ret += fw_version.to_bytes(4, "little")
|
||||
ret += flash_location.to_bytes(4, "little")
|
||||
ret += crc.to_bytes(4, "little")
|
||||
for x in mic:
|
||||
ret += x.to_bytes(4, "little")
|
||||
ret += counter.to_bytes(4, "little")
|
||||
for x in rsvd:
|
||||
ret += x.to_bytes(4, "little")
|
||||
return ret
|
||||
|
||||
|
||||
def main():
|
||||
parser = argparse.ArgumentParser(
|
||||
description="Converts raw binary output from Zephyr into an ISP binary for Silabs SiWx91x",
|
||||
allow_abbrev=False,
|
||||
)
|
||||
parser.add_argument(
|
||||
"ifile",
|
||||
metavar="INPUT.BIN",
|
||||
help="Raw binary file to read",
|
||||
type=argparse.FileType("rb"),
|
||||
)
|
||||
parser.add_argument(
|
||||
"ofile",
|
||||
metavar="OUTPUT.BIN",
|
||||
help="ISP binary file to write",
|
||||
type=argparse.FileType("wb"),
|
||||
)
|
||||
parser.add_argument(
|
||||
"--load-addr",
|
||||
metavar="ADDRESS",
|
||||
help="Address at which the raw binary image begins in the memory",
|
||||
type=lambda x: int(x, 0),
|
||||
required=True,
|
||||
)
|
||||
parser.add_argument(
|
||||
"--out-hex",
|
||||
metavar="FILE.HEX",
|
||||
help="Generate Intel HEX output in addition to binary one",
|
||||
type=argparse.FileType("w", encoding="ascii"),
|
||||
)
|
||||
args = parser.parse_args()
|
||||
|
||||
img = bytearray(args.ifile.read())
|
||||
|
||||
# Calculate and inject checksum
|
||||
chk = calc_checksum(img, 236, 1)
|
||||
print(f"ROM checksum: 0x{chk:08x}", file=sys.stderr)
|
||||
img[236:240] = chk.to_bytes(4, "little")
|
||||
|
||||
# Get bootloader header, pad to 4032 and glue it to the image payload
|
||||
bl = bytearray(get_bootload_ds(4032, args.load_addr))
|
||||
padding = bytearray(4032 - len(bl))
|
||||
img = bl + padding + img
|
||||
|
||||
# Get fwupreq header and glue it to the bootloader payload
|
||||
fwupreq = bytearray(get_fwupreq(args.load_addr - 0x8001000, len(img)))
|
||||
img = fwupreq + img
|
||||
|
||||
# Calculate and inject CRC
|
||||
crc = calc_crc32(img)
|
||||
print(f"Image CRC: 0x{crc:08x}", file=sys.stderr)
|
||||
img[20:24] = crc.to_bytes(4, "little")
|
||||
|
||||
args.ofile.write(img)
|
||||
|
||||
# If you want to compare this file with the .hex file generated by Zephyr,
|
||||
# You have to reformat the Zephyr output:
|
||||
# import intelhex
|
||||
# hx = intelhex.IntelHex()
|
||||
# hx.fromfile("zephyr.hex", "hex")
|
||||
# hx.write_hex_file("zephyr.out.hex", byte_count=32)
|
||||
if args.out_hex:
|
||||
hx = intelhex.IntelHex()
|
||||
# len(bl) + len(padding) + len(fwupreq) == 4096
|
||||
hx.frombytes(img, args.load_addr - 4096)
|
||||
hx.write_hex_file(args.out_hex, byte_count=32)
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
main()
|
|
@ -69,6 +69,11 @@ family:
|
|||
socs:
|
||||
- name: efr32mg29b140f1024im40
|
||||
- name: efr32mg29b230f1024cm40
|
||||
- name: silabs_siwx91x
|
||||
series:
|
||||
- name: siwg917
|
||||
socs:
|
||||
- name: siwg917m111mgtba
|
||||
- name: silabs_sim3
|
||||
series:
|
||||
- name: sim3u
|
||||
|
|
Loading…
Add table
Add a link
Reference in a new issue