Some ESP32 images may not end with a segment whose
load_addr is 0xFFFFFFFF, especially if the flash was not fully
erased or the image tool does not write an explicit end marker.
This can cause the loader to process leftover or unrelated data as
additional segments, resulting in boot failures.
Update the IS_LAST() macro to treat any segment not matching
a valid memory region as the end of the segment list.
This ensures only valid segments are loaded and any trailing
invalid data is safely skipped.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
There is no need to call stm32_pwr_wkup_pin_cfg_pupd() because
the SoC does not have a pull-up/pull-down on the WKUP pin.
Call LL_PWR_ClearFlag_SB() before entering StandBy power mode.
Signed-off-by: Oleh Kravchenko <oleg@kaa.org.ua>
Some of ESP32 Radio calls present in blobs needs to be
executed from IRAM or RAM instead of flash to avoid
cache disabled issues.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This Kconfig was deprecated in Zephyr 3.5, remove allowing it to
be selected but keep the symbol as the HAL needs to be updated
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Check for STM32F1 series was done with "#ifdef SOC_SERIES_STM32F1X"
but this symbol comes from Kconfig.
Use the correct "CONFIG_SOC_SERIES_STM32F1X" instead.
Signed-off-by: Oleh Kravchenko <oleg@kaa.org.ua>
Move the IronSide APIs to soc/nordic from drivers/firmware since
these are vendor specific APIs. The header files are now included
from <nrf_ironside/*.h>. Adjust code that uses these APIs accordingly.
Also move the DT binding for "nordic,ironside-call" from
bindings/firmware to bindings/misc.
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
Utilize a code spell-checking tool to scan for and correct spelling errors
in `Kconfig` files within the `soc` and `subsys` directory.
Additionally, incorporates a fix recommended by the reviewer.
Signed-off-by: Pisit Sawangvonganan <pisit@ndrsolution.com>
The marking procedures can be reverted, since at this stage
it is already allowed to use the stack.
The MSP is temporairly set to interrupt stack in `reset.S` file before
calling s2ram procedures..
Signed-off-by: Adam Kondraciuk <adam.kondraciuk@nordicsemi.no>
This reverts commit e68d110f7c175f2a9275659d023c9d37d1e4b4f1.
Fix for compiling i2s drivers on the NXP mimxrt1010_evk board.
For mimxrt1011, the defines kCLOCK_Sai2... are not defined as the sai2
peripheral does not exist. Trying to compile gives error. Fixed by adding
check for device tree node around code that uses the defines. Also added
same for sai1 and sai3. Thanks @lucien-nxp, @ZhaoxiangJin from NXP.
Signed-off-by: Imran Sajjad <imran.sajjad@iconfitness.com>
Don't force select INIT_SYS_PLL at SOC level. Instead use default y so
that board can unset it. Keep previous case where we would default y
which was only on RT1040. Also, this config is not used in RT1170 soc,
so move it to RT10xx series kconfig instead of family level. And it
appears to be on all the RT10xx, so ifdef is not needed.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Don't force select the INIT_VIDEO_PLL config so that board level can
unset it. Also clean up the code a bit in soc.c files.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The LDO config should not be forcefully selected at SOC level. Instead,
use soft default y so that board definition can unset it if desired.
Also, in the soc.c, the LDO code should be on both the rt1160 and
rt1170, so the definitions should exist, and ifdef is not needed. So can
switch to IS_ENABLED to decrease configuration complexity of the source
code.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The DCDC should be on all the platforms and the functions and structs
should therefore be defined on all the platforms. So the ifdef is not
needed, we can remove it to increase code compilation coverage unity
across configurations slightly. Compiler should optimize out the block
when IS_ENABLED is false statically.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Don't forcefully select this config in SOC level. Make it softer default
y so board can unselect it.
The config should not be possible if there is no arm pll, namely on
RT101x and RT102x. So add dependency clause about this.
And of course, code for this was a mess, clean up a bit.
Also remove the ifdeffry for selecting a default value for the two SOCs,
because they already put the same default value in the SOC Devicetree
DTSI, so that code had no purpose as long as a board didn't completely
redefine the SOC DT.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Initial motivation for this commit was to not force select
the INIT_ENET_PLL config from SOC level to allow for board level
configuration which might want it to be off.
While doing that, I discovered that RT11xx actually does not have
anything called by "ENET PLL" in the reference manual. So I have
removed the config for RT11xx. The default clock source for this soc.c
code for RT11xx is PLL1 DIV2, which I changed to just be configured if
ethernet is enabled, which was the reason to configure this pll as it
stands now, even though it is not specific to ethernet (although the
DIV2 output is mostly for ethernet). Another config is therefore not
needed.
For RT10xx, the situation is a lot more complicated. There is a lot of
discrepancy again between what is considered the "ENET PLL" both
conceptually and literally between the RM, SDK, and Zephyr config. And
also the code to define the config struct was a complete mess. So I have
simplified the code and changed it so that the config is only a soft
default to y instead of selected forcefully. Also, for the case of the
RT1010 and RT1020 series, the SDK is appearing to configure PLL6 (again
there is no clear ENET PLL meaning on these platforms) 500M output
through this "enet pll" configuration function. So similarly instead of
always enabling this output for those platforms, I added a new config
which can be set or unset by board level.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
The original logic relied on the tick passed in. This method
is inaccurate as the tick value passed in was the exit latency.
Update the code to calculate the remaining time left and set
a counter using this value.
Signed-off-by: Mahesh Mahadevan <mahesh.mahadevan@nxp.com>
Several reason cause loopback test failed:
a) FlexIO input frequency is not correct, on RT11xx, input freq is 24M,
while max baud rate can reach 1/4 of input freq, so it can only support
6Mbps.
b) Flexio shift register depend on correct timer output to triggger TX
and RX, if timer comparison value is not accurate, RX error happens on
high baud rate. This is the reason why test fails on RT1060.
also fix a error on FlexIO clock ID calculation.
Signed-off-by: Raymond Lei <raymond.lei@nxp.com>
Use default value 0 if board DT doesn't define it.e
It's totally fine if the board device tree doen't define
load_capacitance_picofarads for the crystal oscillator. In that case,
just fallback to 0.
Signed-off-by: jens rudberg <jens@teenage.engineering>
The siwx91x need a specific firmware image format. These image end with
.rps extension. The current name of the image is zephyr.bin.rps. However,
the .bin suffix is not relevant. It makes even more sense if we consider
the output of west sign: zephyr.signed.bin.rps. We can simplify these name
by remove the .bin suffix.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Once the keys has been provisioned on the Silabs siwx91x, the chip expects
the firmware to be properly signed.
This PR automate the signing process. Hence, "west flash" will work as
expected.
Co-developed-by: Aasim Shaik <aasim.shaik@silabs.com>
Signed-off-by: Aasim Shaik <aasim.shaik@silabs.com>
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Silabs siwx91x support signed and encrypted firmwares. This PR includes
support for these features in "west sign"
Co-developed-by: Aasim Shaik <aasim.shaik@silabs.com>
Signed-off-by: Aasim Shaik <aasim.shaik@silabs.com>
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Disable generation of .hex output, since the Commander runner
prefers it over the .bin output but SiWx91x needs a .bin.rps file.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Co-developed-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Use runners_yaml_props_target to set the name of the file to
flash, rather than hard-coding it for each board.
Co-developed-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Floating-Point System ID register (FPSID) = 0x41033094
AArch32 Media and VFP Feature Register 0 (MVFR0) = 0x10110222
AArch32 Media and VFP Feature Register 0 (MVFR1) = 0x1111111
MVFR1 SIMDFMAC, bits [31:28] = 0; FMAC is not supported
Signed-off-by: Simon Maurer <mail@maurer.systems>
Enlarge NUM_IRQS by 32 which is the number of interrupts for
SGI (Software Generated Interrupts) and PPI (Private Peripheral
Interrupts).
Signed-off-by: Tony Han <tony.han@microchip.com>
Obtain the divisor value for generate the corresponding MCKx from the
register instead of from the variable to avoid wrong result caused by
un-synced division ratios.
Signed-off-by: Tony Han <tony.han@microchip.com>
Obtain generic clock division ratio from the register instead of
from the variable to avoid wrong result caused by un-synced
division ratios.
Signed-off-by: Tony Han <tony.han@microchip.com>
Adding supporting soc files for the k32lx platforms and updating
soc.yaml.
Signed-off-by: Ishraq Ibne Ashraf <ishraq.i.ashraf@gmail.com>
soc: nxp: kinetis: k32lx: Use device tree provided value
This clock frequency value will be defined in the board device tree.
Signed-off-by: Ishraq Ibne Ashraf <ishraq.i.ashraf@gmail.com>
