Add initial support for nuvoton numaker m335x SoC series
including basic init and device tree source include.
Signed-off-by: cyliang tw <cyliang@nuvoton.com>
Add support for configuring the High-Speed Low-Voltage (HSLV) mode
in the GPIO port manager based on the DT configuration. This
enhancement allows for improved performance at lower voltages.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
This adds the soc files for the Synaptics SR100 SoC.
Signed-off-by: Łukasz Kędziora <lkedziora@antmicro.com>
Signed-off-by: Piotr Zierhoffer <pzierhoffer@antmicro.com>
Signed-off-by: Andreas Weissel <andreas.weissel@synaptics.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
This adds support for Cadence SweRV S420 SoC which is similar
to S400 but with support for 2 threads.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Use `IRQ_CONNECT` to register the ROM-implemented `Peripheral_Handler`
for `Peripheral_IRQn` on rtl87x2g and rtl8752h SoCs.
This bridges the hardware-specific Level 1 interrupt routing from the
ROM into Zephyr's standard IRQ system, making sure that the
sub-interrupts under `Peripheral_IRQn` are properly enabled and functional.
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
GDB crashes with a segfault when loading ELF files built
for Espressif SoCs. Starting with GDB 13 (commit
5abbfa982215), finish_block_internal() calls
SECT_OFF_TEXT(m_objfile) which requires sect_index_text to
be initialized. This index is only set when a section
named exactly ".text" exists in the ELF. Without it, the
index stays at -1 and GDB segfaults (upstream PR 25678).
Espressif linker scripts named the flash-mapped code
output section ".flash.text" instead of ".text", so the
final ELF had no ".text" section. Other Xtensa vendors
(Intel ADSP, Cadence) use ".text" as their output section
name and collect .iram0.text as input into it, avoiding
the problem.
Fix this by renaming the ".flash.text" output section to
".text" across all Espressif SoC linker scripts. The
section name is internal to the linker script; the runtime
loader uses linker-generated symbols (_image_irom_start,
etc.), not section names. This change is transparent to
the boot path, flash image generation, and MMU mapping.
Affected SoCs: ESP32, ESP32-S2, ESP32-S3, ESP32-C2,
ESP32-C3, ESP32-C5, ESP32-C6, ESP32-H2.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
- Define the HCI node in the SoC series' dtsi.
- Adjust main thread stack sizes and buffer counts required for
Bluetooth operation.
- Enable meta-irq to configure the bee-bt-controller thread as a
meta-irq thread.
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
Implement the custom stack guard using the Andes StackSafe hardware
stack protection. It triggers an exception on stack overflow when the
stack pointer exceeds the configured limit.
Signed-off-by: Rick Tsao <rick592@andestech.com>
Qemu includes support for the OpenRISC 1000 CPU architecture. This patch
adds a Zephyr SoC definition which enables usage of this feature.
The SoC definition closely mirrors the Qemu MIPS Malta SoC definition.
Signed-off-by: Joel Holdsworth <jholdsworth@nvidia.com>
Compiling for NVL/NVL-S reports:
warning: implicit declaration of function 'intel_adsp_clock_soft_off_exit'
Because the ace4 version of adsp_power.h is missing the declaration of
intel_adsp_clock_soft_off_exit().
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Use new Kconfig preprocessor helper to compute CONFIG_NUM_IRQS during build
instead of hardcoding it based on product Reference Manual
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Make the build to fail when CONFIG_TRUSTED_NONSECURE is enabled and
the DT files do not provide the non-secure memory address ranges.
The test only checks pinctrl node which should be enough to ensure
other the right peripherals address range is applied.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Condition NPU configuration to NPU_PRESENT directive from the STM32 HAL
to prevent build errors when targeting a STM32N6xx series that do not
implement the NPU.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Do not enforce enabling of CONFIG_TRUSTED_EXECUTION_SECURE for
stm32n6x SoC series. This prepare support for non-secure Zephyr
application on related platforms.
This change requires that all board defconfig files running application
in secure state need to explicitly enable TRUSTED_EXECUTION_SECURE
since it is indirectly expected by STM32 HAL for embedding resources
related to security features as SAU support and RIF firmware configuration
functions.
Update migration guide accordingly.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Change stm32n6xx SoCs DTSI files to ease how a board can use the
secure or non-secure IOMEM and internal SRAMs address ranges depending
on whether the Zephyr application runs in secure or non-secure
world. This relies on use of the ranges DT property.
By default, the existing stm32n6xx SoC DTSI files define the secure
address mapping as prior this change, hence no functional changes.
Boards/platforms embedding a stm32n657X0 compliant SoC and expecting
to run in non-secure world can apply use the standard SoC DTSI file
and apply last stm32n657X0_ns.dtsi overlay file to select the non-secure
mapping address ranges.
For this purpose, use ranges DT properties and a node level for
peripherals and SRAMs:
- Insert axisram12@24000000 node level for the AXI SRAM1 and SRAM2 nodes
with a ranges property to define the address range of these
internal RAMS.
- Add a ranges property in ramcfg@* nodes to define the address ranges
for the AXI SRAMs they each define.
- Insert peripherals@40000000 node level with a ranges property for the
peripherals in soc node and its subnode to define the address ranges
applied.
Update stm32n6x ram_check.ld linker script to consider address ranges
instead of the reg property raw value.
Update the HAL reference that bring pinctrl DTSI files that must be
consistent with the SoC DTSI files regarding pinctrl node path change.
Sync on a MCUboot repo change to consider ranges in stm32n6 memory DT
node properties.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Perform iosync configuration in the common stm32_gpioport_configure_pin()
function instead of doing it from the pinctrl driver. This simplifies the
pinctrl driver and also opens the door to iosync configuration using the
GPIO API (via vendor-specific extensions) in the future.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Implement a device driver for XSPI manager.
This allows to define the xspi controllers configuration that should
be applied towards the xspi IO ports:
- Muxed
- Swapped
- ...
Since its configuration has impact on final application location and
implies the deactivation of xspi clocks, it should be run only at fsbl
stage and not later.
Signed-off-by: Erwan Gouriou <erwan.gouriou@st.com>
Check if PWR_STOP3_SUPPORT is defined because if it is
SRAM1 does not support page-granular retention (pages 2–7).
Signed-off-by: Julien Racki <julien.racki-ext@st.com>
1. Keep drivers/timer/cortex_m_systick.h as a compatibility
shim for legacy Cortex-M-specific names.
2. Switch to use the generic low-power companion timer API
for the Cortex-M SysTick driver.
3. Mark the global CORTEX_M_SYSTICK_LPM_* kconfig options
as 'DEPRECATED' and replace them with SYSTEM_TIMER_LPM_*
4. Rename 'zephyr,cortex-m-idle-timer' to
'zephyr,system-timer-companion'
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
Some test failed because of orphaned section caused by missing
sections. This fixes the issue by including common-noinit.ld.
Signed-off-by: Marek Matej <marek.matej@espressif.com>
Add the MPU entry representing ROM region.
This configuration is incompatible with
`CONFIG_NULL_POINTER_EXCEPTION_DETECTION_MPU`. The first 32 bytes
of ROM contains some read-only data used by certain ROM functions.
Enabling this can break some ROM functions.
Refer to: https://github.com/raspberrypi/pico-bootrom-rp2350
Signed-off-by: Andy Lin <andylinpersonal@gmail.com>
Add the MPU entry representing ROM region.
This configuration is incompatible with
`CONFIG_NULL_POINTER_EXCEPTION_DETECTION_MPU`. The first 256 bytes
of ROM contains some read-only data used by certain ROM functions.
Enabling this can break some ROM functions.
Refer to: https://github.com/raspberrypi/pico-bootrom-rp2040
Signed-off-by: Andy Lin <andylinpersonal@gmail.com>
Wrap the picotool sign command (requires recent picotool) to build
signed ELF files (which can be later converted to UF2 as well).
The resulting files boot, yet this has not been tested with actual
Secure Boot yet.
Signed-off-by: Dmitrii Sharshakov <d3dx12.xx@gmail.com>
Add SoC-level support for the ESP32-C5, Espressif's first dual-band
Wi-Fi 6 SoC with a RISC-V core clocked up to 240 MHz and 384 KB SRAM.
The ESP32-C5 uses a CLIC interrupt controller (not PLIC like ESP32-C6).
CLIC requires special handling for mret to restore mintstatus.mil from
mcause.mpil: bit 31 (interrupt flag) must be set in mcause before mret,
otherwise mil is not restored and interrupts at the same level are
permanently blocked. This is handled via RISCV_SOC_CONTEXT_SAVE with
mcause and mintthresh save/restore in soc_irq.S, following the same
pattern used by GD32VF103 (Nuclei ECLIC) and Nordic VPR.
The systimer on ESP32-C5 always runs at 16 MHz regardless of the XTAL
frequency (40 or 48 MHz), which requires a SoC-specific override for
SYS_CLOCK_HW_CYCLES_PER_SEC.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Add timer subnodes under the MAX32657 Wake‑up Timer device nodes to
enable system timer configuration in devicetree.
Also set default SYS_CLOCK_TICKS_PER_SECOND to 8192 if Wake-up Timer is
selected as system timer.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Add platform shims, FreeRTOS compatibility layer, and linker scripts
to support the BL702 on-chip BLE controller binary blob under Zephyr.
The BLE blob expects a FreeRTOS environment and vendor HAL functions.
This commit provides:
- FreeRTOS API shim (xTaskCreate, xQueueGenericSend, pvPortMalloc,
etc.) mapping to Zephyr kernel primitives (k_thread, k_msgq,
k_malloc)
- Platform shims for bl_irq_*, bl_timer_*, BL702_Delay_*, GLB_*,
and UART stub functions the blob references
- RF calibration callbacks required by libbl702_rf.a
- Linker scripts placing BLE/FreeRTOS ROM writable data regions and
__global_pointer$ for GP-relative addressing from ROM code
- ROM function address table (PROVIDE symbols) as fallback for
un-shimmed FreeRTOS functions
- HAL module CMakeLists selecting controller library variant and
linking BLE/RF blobs
- Exchange memory configuration (8KB) when BLE is enabled
- RISCV_NO_MTVAL_ON_FP_TRAP selection for FPU trap handling
Signed-off-by: William Markezana <william.markezana@gmail.com>
If runtime power management is enabled for idle mode timer, it must be
explicitly resumed after waking up from suspend-to-RAM modes. Call
pm_device_runtime_put() before suspending to decrement the usage counter
so that pm_device_runtime_resume() can successfully resume the device
after wake up.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
The MPC is currently set up to allow R,W,X,Priv access to all RAM
and MRAM for all cores. This is not sufficient if CONFIG_USERSPACE
is enabled, in which case the application core will be accessing
memory unprivileged, using the MPU to manage memory access.
Update MPC configuration to allow R,W,X,Unpriv access to all RAM and
MRAM for all cores. The R,W,X MPC configuration has to be applied
regardless of CONFIG_USERSPACE, so no need to conditionally include
the MPU configuration based in CONFIG_USERSPACE.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Travis Lam <travis.lam@nordicsemi.no>
Enable UART_NS16550_TI_K3 driver by default for AM6X A53 cores.
This ensures the TI K3 specific UART variant is used on A53 cores,
matching the configuration already enabled for M4 and R5 cores.
Signed-off-by: Soumya Tripathy <s-tripathy@ti.com>
definition of KConfigs STM32WBA_LL_THREAD_STACK_SIZE,
STM32WBA_BLE_CTLR_THREAD_STACK_SIZE, STM32WBA_LL_THREAD_PRIO,
and STM32WBA_BLE_CTLR_THREAD_PRIO to confige the
threads dedicated to BLE Controller and Link Layer
process.
Signed-off-by: Vincent Tardy <vincent.tardy@st.com>
Ble host and link layer threads initialization is no more done
during the system initialization.
Add stm32wba_ble_ctlr_thread_init() and
stm32wba_ll_ctlr_thread_init() functions calls
during ble and ieee802.15.4 driver initialization
Signed-off-by: Vincent Tardy <vincent.tardy@st.com>
Add missing header file in stm32l1x poweroff.c drivers to get
stm32_enter_poweroff() and LL_DBGMCU_DisableDBGStandbyMode() declared.
Remove inclusion of stm32_ll_cortex.h that is not needed.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
The image array entry in the boot container had incorrect values for
offset, size, and load_addr fields, preventing use with NXP Secure
Provisioning Tool (SPT).
The offset was calculated as -1 * CONFIG_IMAGE_CONTAINER_OFFSET
(0xFFFFF000) instead of CONFIG_CONTAINER_USER_IMAGE_OFFSET (0xA000).
The size and load_addr fields did not account for the header region.
These fields now correctly reflect the flash layout with container
at 0x1000 and application code at 0xB000.
Signed-off-by: Jacob Wienecke <jacob.wienecke@nxp.com>
