If a warm reboot is issued (e.g., via mcumgr reset), the sam
controller just hangs because of loop in reboot.c. This can
be devastating if no watchdog is present to reboot the controller.
Signed-off-by: Jaro Van Landschoot <jaro.vanlandschoot@basalte.be>
Move most of the code that is used to interface with IronSide SE on the
nRF54H20/nRF9280 from the soc/nordic directory to the hal_nordic
repository. The interface code is now provided by the new IronSide
support package. Build system code and glue code that makes use of
Zephyr APIs is now located in the modules/hal_nordic directory.
Update the directory path for IronSide SE interface code in
MAINTAINERS.yml to match the move from soc/nordic/ironside to
modules/hal_nordic/ironside.
Also included are some refactoring changes and cleanup to match the new
supporting code.
C code and Kconfigs have been renamed to *ironside_se* / *IRONSIDE_SE*
to match the supporting code changes. Users of these APIs in zephyr
have been updated to match.
Individual configurations for different "IronSide services" have been
removed as the API serialization for all of these is now provided in
a single C file / header file (ironside/se/api.h).
The ironside_boot_report_get() API has been removed. The boot report
structure can be accessed through the IRONSIDE_SE_BOOT_REPORT macro.
Most configs relating to UICR / PERIPHCONF have been moved under the
"IronSide SE" menu to make it clear that these are part of the
IronSide SE interface.
The macros that in uicr.h that were used to add entries to the
PERIPHCONF section have been removed. The supporting code now provides
PERIPHCONF_XYZ() macros that can be used to initialize structures that
go into this section, and the zephyr part now only contains a macro
UICR_PERIPHCONF_ENTRY() that is used to place an arbitrary structure
into the section. The gen_periphconf_entries.py script used to generate
PERIPHCONF entries based on devicetree has been updated to use the new
macro system.
IronSide SE integration code/configs is now guarded by HAS_IRONSIDE_SE.
Note that the UICR build system integration that relies on Sysbuild
remains under the soc/nordic directory for now, but will be moved to
the modules/hal_nordic directory once it is clear how the integration
will look there.
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
This patch is a workaround to a know issue when Bluetooth and pm
is activated.
We actually need to set the tx power to the Bluetooth controller
(network coprocessor) before sending power saving request to the
coprocessor.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Power profile property doesn't need to be defined in device three.
It is a configuration value that is defined if we want pm with
Bluetooth and/or Wifi .
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
The default MCXW7x platform's clock uncertainty in microseconds for
Coordinated Sampled Listening (CSL) timing synchronization in
OpenThread shall be set to 20.
Signed-off-by: Xavier Razavet <xavier.razavet@nxp.com>
Use the last configured region in the boot config for the next boot,
as opposed to a default region.
Signed-off-by: Muzaffar Ahmed <muzaffar.ahmed@silabs.com>
Currently all drivers which uses a slot from the debug window have fragile
hardwired slot 'mapping', they are locked to use specific slots even if
there are free slots available for them to take.
The new API hides the management of the slots and descriptors and users
can ask, release or even seize slots that they want to use.
Add a new debug slot manager API and a new default no config option to
allow selection between the hardwired or dynamic debug slot management.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Resize the reserved part of the debug window to cover the first 1K and
define the partial_page0 which will cover the partial slot in page 0.
Add comment to describe the debug window layout.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
The current default of 8192 will provide only 2 pages in debug window:
page0: descriptors
page1: slot0
However, the coredump is hardwired to use slot1, which by default is not
valid.
Increase the default window size to 12288 to allow three pages.
This change affects CAVS25 only as it is using default window sizes and the
window 3 is not used in this configuration at all (it was used with IPC3
only), so we do have enough space for the three page - we could even
increase the default to cover 4 pages (8192+8192), but let's be
conservative on this.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
The z_gdb_backend_init() is defined to return with success/error code
with return type of int.
Fixes: a9c47a47a4 ("intel_adsp: cavs: add gdb support")
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Add required CMake directives to enable working CONFIG_SRAM_VECTOR_TABLE=y
on STM32F0 series when CONFIG_CMAKE_LINKER_GENERATOR=y.
Builds OK with both ZEPHYR_TOOLCHAIN_VARIANT undefined (uses GNU toolchain
from Zephyr SDK) and set to "iar" (uses IAR toochain from EWARM v9.70.1).
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Don't quote the section names provided to Z_GENERIC_SECTION: the macro
already performs stringification on our behalf.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Remove selecting `CONFIG_HAS_HW_NRF_RADIO_IEEE802154` that should be
generated from DTS based on the SoC selection.
Signed-off-by: Michał Grochala <michal.grochala@nordicsemi.no>
RIF configuration is now done at soc init time in a centralized
way so it is no more necessary for drivers to perform this
configuration.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Perform all the IPs RIF configuration at init time in case of this
isn't yet performed by an earlier entity during the boot sequence.
This configuration depends on TRUSTED_EXECUTION_SECURE which is
currently always enabled on STM32N6x but will be configurable in
future.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Set dma tcd queue size to 4 defaultly to fix build issues,
- error: static assertion failed: NUM_DMA_BLOCKS_RX_PREP must be
< CONFIG_DMA_TCD_QUEUE_SIZE
#define BUILD_ASSERT(EXPR, MSG...) _Static_assert((EXPR),...
drivers/i2s/i2s_mcux_sai.c:45: note: in expansion of
macro BUILD_ASSERT
BUILD_ASSERT(MAX_TX_DMA_BLOCKS > NUM_DMA_BLOCKS_RX_PREP,
Signed-off-by: Biwen Li <biwen.li@nxp.com>
All power.c files in Espressif SoCs depends on un-registered
soc log module. When CONFIG_LOG=y and CONFIG_LOG_DEFAULT_LEVEL=4,
build fails as LOG_DBG used in those files won't have its proper
declaration.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The `st,stm32-ccm` is now used though the generic DTCM mechanism: remove
all SoC-specific code which was used to implement support for it.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Selecting the correct CTRLSEL value for VPR IO pins relies on
mapping any pinctrl psel value with the correct port/pin set on the
VPR nodes in devicetree to the same CTRLSEL value, to avoid enumerating
all permutations of (pin function, port, pin).
However, the mechanism did not work as intended and ended up mapping all
these pins to GPIO instead, which meant that the pins did not behave
as expected.
Update the handling so that it works as intended.
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
- Enable the DTCM region in soc.c
- Apply MPU configuration for the new memory region (itcm, dtcm,
sram,...)
- Turn on the Kconfig to relocate the vector table to 0x0.
Signed-off-by: Phuc Pham <phuc.pham.xr@bp.renesas.com>
Signed-off-by: Nhut Nguyen <nhut.nguyen.kc@renesas.com>
Use CONFIG_CACHE_HAS_MIRRORED_MEMORY_REGIONS instead.
The new kconfig reflects more correctly on what is going on
in hardware. Also, this is not enabled by default if CPU
cache is not coherent. CPU cache can be incoherent and yet
there are no mirrored memory regions. Those relying on this
deprecated default behavior has their config adding
CONFIG_CACHE_HAS_MIRRORED_MEMORY_REGIONS separately.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This re-implements the CONFIG_XTENSA_RPO_CACHE and its cached
and uncached region support in the SoC layer. This is in
preparation for removing RPO cache in the architecture layer
as this is a SoC feature and not an architecture feature.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This allows SoC to define their custom cache related functions
and are used by sys_cache_*() functions.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
arch_mem_coherent() is cache related so it is better to move it
under cache subsys. It is renamed to sys_cache_is_mem_coherent()
to reflect this change.
The only user of arch_mem_coherent() is Xtensa. However, it is
not an architecture feature. That's why it is moved to the cache
subsys.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The macro ARCH_XTENSA_SET_RPO_TLB is only used for Intel Audio
DSP. The specific memory mapping requiring this is SoC specific
feature and not a feature on Xtensa in general. It should not be
declared in the architecture layer. So move it.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds a kconfig to indicate a memory mapping where physical
memory regions are both mirrored and mapped in different
addresses. Accessing one set of addresses is via CPU cache
while the other is directed to memory.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This moves the ace-link.ld into include/linker to indicate it is
to be included by the main linker script. Also rename it to
ace-link-mirrored.ld to indicate that it is for the mirrored
cache configuration.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The Zephyr linker script usually puts something before
z_mapped_start (where .text is), for example, vecbase vectors.
So we need to reserve those space or else k_mem_map() would be
mapping those which may result in faults.
To avoid mapping there, CONFIG_ARCH_HAS_RESERVED_PAGE_FRAMES
needs to be used. Since it is common when MMU is enabled, we
should enable it by default using imply. All current Xtensa
MMU SoCs all have this selected anyway. Using 'imply' instead
of 'select' is to allow it to be disabled if so desired.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Rework the SoC MMU mappings in preparation for removal of
double mapping code in Xtensa architecture code. This will let
the SoC layer and application to fine tune memory mappings
instead of having double mapping forcibly applied everywhere.
The modified mapping array mimics what the double mapping
would have done simply to have the same behavior. Future
optimizations can be done to remove unnecessary mappings.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This adds the arch default MMU mappings into the SoC mapping
array. This is in preparation of not forcibly doing double
mapping in architecture code as this type of double mapping
should be specified for individual regions. This allows
the SoC layer to fine tune the mappings as not anything
needs to be double-mapped.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Moves the HiFi related kconfigs to their respective SoC
kconfigs as it is specific to the SoC... and this requires
creating new kconfigs for each SoC series.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
The SCMI CPU protocol is in fact a vendor extension from NXP. The current
naming used for the CPU protocol definitions (i.e. functions, structures,
macros) follows that of the SCMI standard protocols, which might be
misleading.
Include "nxp" in the name of all of the CPU protocol definitions.
This change was performed mechanically using "git grep" and "sed -i"
with some manual intervention.
Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
When the firmware wrote data to KBC/AUX output buffer, the hardware
automatically generated IRQ1/12 to notify the host. After the host read
the data, the EC received an output buffer empty (OBE) interrupt to
indicate that the next byte could be written. However, on the NPCX9M7FB,
this mechanism may cause IRQ1/12 to be missed if the firmware write new
data immediately after detecting that the output buffer is empty,
resulting in incorrect behavior.
To avoid missing IRQ1/12, the flow is changed so that it first checks
VWIRE_AVAIL to ensure no pending VW events. If no VW event is pending,
the firmware writes data to the output buffer and explicitly asserts
IRQ1/12 to notify the host. After the host reads the data and the OBE
interrupt triggers, the firmware clears IRQ1/12.
This updated sequence prevents IRQ1/12 from being lost and ensure
correct notification behavior.
Signed-off-by: Tom Chang <CHChang19@nuvoton.com>
Add DT helper file for PIC32CX-SG family devices to support
SoC-specific device tree definitions and utilities.
Signed-off-by: Arunprasath P <arunprasath.p@microchip.com>
