On nrf54h20 RISC-V cores, large sw_isr_table growth can place small data
outside the GP-relative 12-bit range and trigger linker errors like:
"relocation truncated to fit: R_RISCV_GPREL_I against ..."
Disable small-data generation for VPR cores by adding
zephyr_compile_options(-msmall-data-limit=0)
Signed-off-by: Riadh Ghaddab <riadh.ghaddab@nordicsemi.no>
The shared STM32 GPIO port helper only programs OTYPER when a pin is
configured in GPIO output mode. Alternate-function pins skip that step,
so AF open-drain configurations are left in the reset push-pull state.
This breaks STM32 peripherals such as I2C: the controller registers can
be configured correctly, but SDA/SCL are electrically misconfigured and
transfers fail with an address-phase NACK.
Apply OTYPER for both alternate-function and output modes before the pin
mode is committed.
Signed-off-by: Zafer SEN <zafersn93@gmail.com>
Enable pinctrl sleep state for all Nordic SoCs. It allows to put
pins into sleep state also when PM is disabled.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Introduce a hidden Kconfig option selected by SoCs on which the OTP area
must be accessed using uncached reads/writes. More specifically, this is
selected on STM32C5 and STM32H5 series where cached operations are done
by ST "ICACHE" using 128-bit requests, but the flash's OTP bus interface
rejects such accesses with a bus error - the issue isn't in caching but
rather in the data size of cacheable accesses.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
cm0 (cpu1) core is not configured correctly. It does not have DWT
and SYS_CLOCK_HW_CYCLES_PER_SEC is set to cpu0 frequency.
Select DWT for CPU0 only. Set SYS_CLOCK_HW_CYCLES_PER_SEC based on
selected core.
Signed-off-by: Michal Smola <michal.smola@nxp.com>
- Power on display and camera mix for mipi dsi
- Configure display clock settings
- Add pixel link configuration
Signed-off-by: Ruoshan Shi <ruoshan.shi@nxp.com>
Add supports for XIAO ESP32C5, a compact development board based on the
ESP32-C5 SoC.
Assisted-by: Cursor:composer-2
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
- Add header for clock defintions used by the devicetree.
- Add clock node.
- In soc.c, parse clock node config from the devicetree and apply them.
Signed-off-by: Scott Laboe <scottyl2.718@gmail.com>
Update preprocessor condition to use the correct
Kconfig macro so the debug configuration is
applied as intended.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Add QDEC driver support for Realtek Bee series SoCs,
including RTL87x2G (AON QDEC) and RTL8752H (Basic QDEC).
This driver supports:
- X, Y, and Z axis count reading
- Hardware interrupt-based event trigger
Signed-off-by: Yuzhuo Liu <yuzhuo_liu@realsil.com.cn>
Extend hwreg0 region end from 0x100000 to 0x100800
to include new register space on ACE 3.0.
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
Extend hwreg0 region end from 0x100000 to 0x101800
to include new register space on ACE 4.0.
Signed-off-by: Adrian Bonislawski <adrian.bonislawski@intel.com>
Application can now enable cache management
for M7 core on i.MX8MP via CONFIG_CACHE_MANAGEMENT
option.
Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
With the switch to zephyr,mapped-partition, the upstream Kconfig
stops exposing FLASH_LOAD_OFFSET when FLASH_USES_MAPPED_PARTITION
is set, so the Espressif Kconfig defaults that populated it no
longer apply. Drop the custom FLASH_LOAD_OFFSET defaults in the
SoC family, esp32c5 and esp32c6 defconfig files, and read the
image flash offset directly from the devicetree partition node
in the common CMakeLists.txt so the esp32 runner keeps getting
the correct --esp-app-address.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Move siwx91x SoC power management initialization from early_init_hook
function to a dedicated function in "power.c" file. This reduces
initialization complexity.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
CONFIG_SOC_SIWX91X_PM_BACKEND_PMGR adds an unnecessary layer,
as everything can be handled by the CONFIG_PM symbol.
Removing it reduces complexity in the siwx91x SoC files.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
The usual denomination for the SoC power related file is "power.c".
Hence renaming siwx91x SoC power related file to "power.c" in order
to reduce complexity in files naming for this SoC.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
Add SoC and board support for AMD Audio Co-Processor (ACP) 7.0.
This includes the SoC definition, board configuration, defconfig,
Kconfig options, linker script, and register/memory headers for
the Xtensa HiFi5-based AMD ACP 7.0 audio DSP.
Signed-off-by: Siva Subramanian Ravi Saravanan <sravisar@amd.com>
Updates all bouffalo lab SOC's to avoid selecting FLOAT_HARD (i.e. floating
point ABI). FLOAT_HARD is the default for RISC-V SOC's that have an FPU and
are not RV32E, and explicitly selecting at the SOC level makes it
impossible for an application to override.
Signed-off-by: Dan Mangum <georgedanielmangum@gmail.com>
Add SoC definition for Bouffalo Labs BL808 with T-Head E907 core:
- Early boot: disable interrupts, D-cache, and speculation before
mtvec is configured to prevent unhandled traps
- SoC initialization with CLIC interrupt controller setup
- Power controller compatibility for BL808 register layout
Signed-off-by: William Markezana <william.markezana@gmail.com>
Combine the Cortex-M7 ENET workaround updates into one commit.
- clear CACHE_ENET on i.MX RT11xx Cortex-M7 for ERR050396
- disable ETH_NXP_ENET_USE_DTCM_FOR_DMA_BUFFER by default on Cortex-M7
- keep the final Kconfig condition independent of
DT_HAS_NXP_ENET1G_ENABLED
This avoids touching the same Kconfig and SoC files in follow-up
commits while preserving the intended behavior for PR #106679.
Validation:
- branch history squashed so workaround files are updated once
in the series
Signed-off-by: Hake Huang <hake.huang@nxp.com>
Enabling frame pointer is possible, but enabling it for leaf
functions will crash the VPR, likely due to too few registers
available. The default with the new SDK seems to be
no-omit-leaf-frame-pointer, so we need to explicitly omit them
moving forward. The option only has any effect if
no-omit-frame-pointer, so only set the option if
no-omit-frame-pointer to make it clear why we are setting it.
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Use custom cpu_idle implementation for all VPRs and implement
workarounds for erratas which impact sleeping
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
This places the L1 and L2 page tables continuously in memory,
and keeping them together. This avoids some fragmentations in
the virtual memory space.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Add Kconfig entries to allow compile own s2ram implementation.
Signed-off-by: Andrzej Puzdrowski <andrzej.puzdrowski@nordicsemi.no>
Signed-off-by: Jakub Zymelka <jakub.zymelka@nordicsemi.no>
Add STM32_INT_FLASH_SECURE_BASE_ADDRESS kconfig symbol to define
the base address of the memory mapped STM32 SoC secure internal flash
address range. This configuration and only apply to STM32 Cortex-M SoCs
that embed and internal flash and support TrustZone.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Using macrobatics, shrink the GPIO ports table such that it only contains
as many elements as required to access all enabled GPIO ports. This saves
a lot of ROM compared to the previously fixed-size table which had one
pointer for each *possible* GPIO port, regardless of whether or not they
existed on the target HW and were enabled in Devicetree.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The `pinctrl_soc_pin_t` format occupied two uint32_t even though all info
it stores can be compressed in 32 bits only, and also didn't map very well
to the hardware (especially on STM32F1). Due to defects, the format was
also NOT what the `stm32_gpioport_configure_pin()` function consumed to
actually configure a GPIO port, requiring additional decoding/manipulation
logic.
Introduce a vastly reworked format which only requires 32-bit per pinctrl
entry and maps nicely to hardware and becomes the new format consumed by
stm32_gpioport_configure_pin(). This heavily simplifies the pinctrl driver
since it no longer needs to examine the actual values (except to determine
the target GPIO port and pin - this is done on purpose!). The GPIO driver
converts Zephyr flags to this new format too.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Use a single `if` chain to configure all mode-specific elements to make
the code easier to follow. While at it, add/update a few comments.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Move the logic which sets the output level based on configuration to the
common `stm32_gpioport_configure_pin()` function to reduce duplication.
To support the GPIO use case where a pin's configuration is changed without
modifying its output state, a new parameter is introduced which specifies
whether or not the output level should be modified.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
All defines use just the target register's name as part of the define.
Follow this convention for DELAY/ADVCFGR.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Use `_Pos`/`_Msk` suffixed defines for pinctrl format bits definitions and
declare `_Msk` already shifted. This is aligned with the CMSIS definitions
format which shorter, easier to understand and enables use of
macros _FLD2VAL/_VAL2FLD.
Update all code using these defines accordingly.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Set MAX_IRQ_PER_AGGREGATOR to 52, fixing spurious PLIC interrupts
caused by the default of 0.
Signed-off-by: Adrian Śliwa <asliwa@internships.antmicro.com>
Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
The SoC supports L32EX/S32EX to do atomic CAS ops. Since we now
have support for these, we move sample_controller32 to use that
for testing.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
Apollo4P requires cache to be configured and enabled early in the
boot process for proper interrupt timing and 96 MHz operation.
Without cache initialization, interrupts can be delayed by hundreds
of microseconds, causing timing anomalies in time-critical applications.
This aligns Apollo4P initialization with:
- Apollo3 SoC initialization (which includes cache init)
- Official Ambiq SDK examples (uart_async, etc.)
- Ambiq application notes for maximum performance
The cache must be initialized before low power init to ensure
proper memory access timing throughout the boot sequence.
Fixes interrupt timing delays observed in UART TDMA applications
running at 2 Mbaud with 1ms frame timing.
Signed-off-by: Tibor Kiss <kiss.tibor@gmail.com>
Remove the whitespace from dt_has_compat. The whitespace would be part of
the compatible name and never match the device-tree. Therefore, this config
would never be enabled by the DT.
Also fix a typo in BOOT_XSPI_NOR's message.
Signed-off-by: Daniel Schultz <dschultz@baylibre.com>
Ensure Zephyr post build sequence is run when TF-M is embedded
on a STM32 target since TF-M/STM can install its regression.sh
script which must be processed by running STM postbuild.sh
to be functional.
This change fixes an issue where running 'west build' on an
already built project, or running 'west flash' makes the
regression.sh script to be reinstalled raw from TF-M source tree
(platform/target/ext/stm/...) without being updated trough
postbuild.sh script.
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Move set_target_properties for runners_yaml_props_target below
board.cmake include so that UICR image always flashes its own
output regardless of the main image configuration.
When the main image targets cpuapp/ns (TF-M), import_kconfig()
pulls CONFIG_TFM_FLASH_MERGED_BINARY into the UICR image's CMake
scope. This causes board.cmake to override hex_file with
tfm_merged.hex, which does not exist in the UICR utility image,
resulting in a flash failure.
Signed-off-by: Dhanoo Surasarang <dhanoo.surasarang@nordicsemi.no>
Add support for the ODRIVE (output drive) field at bits 12-13 of the
IOPCTL register on RT7XX. This field controls the transmitter current
drive impedance selection (100/66/50/33 ohm).
- Add nxp,drive-current property to the rt-iocon-pinctrl binding
- Add IOPCTL_PIO_ODRIVE macro to pinctrl_soc.h
- Extend pin config mask from 0xFFF to 0x3FFF to include ODRIVE bits
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
The Cortex-R frequency for the TI K3 series relies on the clock frequency
of the external crystal since it uses the DMTimer interrupt and the DMTimer
uses the external crystal clock as input clock. While some SoC series
inside the K3 family only allow one frequency for the external crystal
(based on the bootmode pin documentation inside the TRM) other allow
multiple possible frequencies. For SoC series that only allow one frequency
it is stored inside the series defconfig (am64x and j722s) and for series
that allow multiple frequencies it was moved to the board defconfigs
(j721e).
Additionally this frequency was wrong for the am64x and j722s series and
got corrected to 25 MHz.
Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>
The SoCs in the TI K3 family enable the OpenAMP resource table
automatically in the Kconfig instead of being disabled due to being
optional in some cases. It is optional when booting after a SBL from the TI
MCU+ SDK but it is required when booting via remoteproc from Linux.
Due to this the enabling has been moved to the board level and whether it
is enabled is based on the documented boot method. For the undocumented
Cortex-R cores on the SK-AM64 it has been enabled since the Cortex-M core
has documentation for booting via remoteproc and for the Cortex-M core on
the AM243-EVM it has been disabled due to having no Cortex-A cores to run
Linux on.
Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>
The Cortex-R cores in the AM64x SoC have 256 instead of 512 interrupts.
This was set wrong since the AM64x Cortex-R options came from the J72x
options which has 512 interrupts connected to the Cortex-R via the VIM.
Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>
Split up the am6x Kconfig files into am62x, am62lx, am64x and j72x to allow
different configurations for different SoC series. While this adds some
redundancy it allows better separation in case some configuration options
between SoCs need to be different, like the number of interrupts on
Cortex-R processors.
Furthermore some ARM-cores were theoretically configured but not actually
supported as build target for the general am6x SoC series, sometimes
because the cores are not present in the SoC itself (e.g. non Cortex-A
cores for the AM62Lx series) and sometimes because nobody added support yet
(e.g. Cortex-A on the AM64x series). Therefor all currently non-supported
combinations have been removed.
Finally the common files were put into the K3 family directory and
clang-format was run on them.
Signed-off-by: Mika Braunschweig <mika.braunschweig@siemens.com>
