The soc.c non-secure build initialisation was using __NRF_TFM__, which
is meant to be for sdk-nrf only. New ifdef function is updated to
replace the secure initialisation condition. So that now power related,
wifi, wicr setup is done in secure environment for non secure build.
Also updated SystemCoreClock as global variable with retrival from the
DT. SystemCoreClock setting will be done in non secure environment
aligning to other nordic soc.
Signed-off-by: Travis Lam <travis.lam@nordicsemi.no>
The newly added/enabled microchip,xec-kbd driver in input_xec_kbd.c
relies on the XEC_KBD_ register offsets for accessing keyboard scan
registers. These offsets are defined in the Zephyr-specific
soc/microchip/mec/common/reg/mec_keyscan.h header.
However, the legacy mec15xx SoC port does not include the common
soc_common.h or reg/mec_keyscan.h headers in its soc.h due to Fatal
Name Collisions with the vendor HAL's component/keyscan.h structs
(which are not present or were refactored in newer MEC SoCs).
Because other drivers like GPIO and UART work around this by only
including their respective isolated register headers, we do the same
for keyscan by defining the missing 5 legacy offsets directly in
mec15xx/soc.h. This restores compatibility with the new input driver
without breaking any of the vendor HAL dependencies.
Assisted-by: Antigravity:gemini-1.5-pro
Signed-off-by: Jeremy Bettis <jbettis@google.com>
Modified the Microchip XEC eSPI TAF V2 driver adding support for
MEC174x/5x/165x. We agree with code quality tool analysis the eSPI
TAF register structure is too larger and not maintainable. The driver
now uses Zephyr's system memory mapped register access routines.
quality check tools find the structure too large.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Add a soc_core_clock_get() helper returning the core clock frequency in
Hz across the MEC15xx, MEC172x and newer series, and extend the eSPI
TAF and QMSPI register headers with the offsets, field helpers and
opcode definitions needed by the V2 driver.
Correct the RPMC OP1/OP2 chip-select 1 opcodes to 0x23/0x24, keeping the
previous 0x83/0x84 values as deprecated aliases, and remove the
deprecated monolithic register structs.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Since backup mode is enabled by default, lock this power state during
for the duration of standby delay as well.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
With NVIC state preserved across S2RAM, restoring the counter state via PM
device runtime ops is no longer necessary.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
WICR is now programmed at runtime. Remove the build-time hex
generator (gen_wicr.py), its sysbuild integration, and the
SB_CONFIG_SOC_NRF71_GENERATE_WICR Kconfig option.
Signed-off-by: Dhanoo Surasarang <dhanoo.surasarang@nordicsemi.no>
Program the Wi-Fi Information Configuration Registers (WICR) at boot.
Values are derived from devicetree phandles and travel inside the
application image, making them DFU-upgradable.
The programming logic lives in wicr_setup.c, shared between the
Zephyr secure build and TF-M. Out-of-tree Wi-Fi patches can override
the ROM patch addresses via compile definitions. Writes are skipped
when the register already holds the correct value to minimise MRAM
wear.
Signed-off-by: Dhanoo Surasarang <dhanoo.surasarang@nordicsemi.no>
This macro eliminates manual size/alignment management and prevents
namespace collisions by moving internal queues to file-private scope.
Signed-off-by: Cesar Vandevelde <cesar.vandevelde@gmail.com>
Skipping the LL_PWR_DisableUCPDDeadBattery() call is not sufficient to
guarantee the Type-C dead-battery CC pull-downs are active by the time
the application runs. PWR->UCPDR.DBDIS is not reset by a chain-load, so
whatever an earlier boot stage left behind in the same power cycle
persists into the application.
MCUboot is the common case: its own build enables neither USB device
stack, so its pass through this hook disables the pull-downs, and it
then chain-loads the application without an intervening hardware reset.
The application's own (now correct) condition evaluates false, leaves
the register alone, and the port is still dead.
Make the application pass authoritative by explicitly re-enabling the
pull-downs when a USB device stack is in use.
Verified on stm32h5f5j_dk booting through MCUboot: PWR->UCPDR read back
0x1 (DBDIS set) on the idling application with only the condition fix
in place, and 0x0 with this change, sampled over SWD.
Signed-off-by: Arkadiusz Grzelka <devitwise@gmail.com>
soc_early_init_hook() disables the USB Type-C dead-battery CC
pull-downs (PWR->UCPDR.DBDIS = 1) whenever there is no devicetree UCPD
node and CONFIG_USB_DEVICE_DRIVER is not enabled. That condition only
knows about the legacy USB device stack.
A board on the new usbd/UDC stack (CONFIG_USB_DEVICE_STACK_NEXT ->
CONFIG_UDC_DRIVER, e.g. CONFIG_UDC_STM32) has neither a UCPD node nor
the legacy driver, so the hook wrongly classifies it as "no USB
present" and removes the pull-downs. Without an Rd on CC a Type-C
source never applies VBUS, so the device port stays dead no matter
what the UDC driver does afterwards. This affects every STM32H5 board
using the new USB device stack.
Extend the condition so the pull-downs are only disabled when neither
USB device stack is in use.
Verified on stm32h5f5j_dk: with the stock condition PWR->UCPDR read
back 0x1 (DBDIS set) on a booted application using CONFIG_UDC_STM32,
sampled over SWD; with this change the port is no longer disabled by
the SoC init hook.
Signed-off-by: Arkadiusz Grzelka <devitwise@gmail.com>
Espressif RISC-V SoCs enter through their own __start in
soc/espressif/common/start.S rather than the common
arch/riscv __initialize. That entry exists because the ROM
hands over on a stack that can overlap .bss, so gp, the
stack and the vector table must be set up before any
compiler-generated prologue runs. As a side effect the
0xaa painting of z_interrupt_stacks done by the common
reset code was never executed.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
zephyr_file_copy() only existed because file(COPY_FILE ...) was not
available with CMake 3.20. With the minimum required CMake version now
being 3.28.3, call the native command directly everywhere in-tree and
deprecate the wrapper, which is kept for out-of-tree users.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Raise the minimum required CMake version from 3.20.0 (documented as
3.20.5) to 3.28.0, which is satisfied by the CMake 3.28.3 package
shipped in the Ubuntu 24.04 LTS repositories. Ubuntu 24.04 is the
current Ubuntu LTS release targeted by the Zephyr getting started
guide, and by the time of the next Zephyr release, Ubuntu 22.04 will be
within months of its end of standard support. Users of distributions
shipping an older CMake can use the Kitware APT repository or a
pip-installed CMake, as the documentation already suggests.
Raising the floor to 3.28 unlocks a range of modern CMake features for
the build system, among which the cmake_file_api() command (3.27),
file(COPY_FILE) (3.21), block()/endblock() (3.25), and allows removal
of several version-conditional workarounds.
The tree-wide cmake_minimum_required() occurrences in samples, tests
and boards are updated accordingly, together with the documentation
and the sysbuild CMake presets. The IAR C-STAT integration keeps its
own higher requirement (4.1.0).
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
config_wakeup_gpio_pins() re-muxes the AON wakeup pads with no bias on
every low power entry, clearing their pull. Sleep-force drive is also
skipped for these pads (GPIO 22-27), so the SoC no longer holds them in
sleep and, absent an external pull, they drift low. With a low-level
wakeup that is the active level and wakes the SoC immediately.
Apply a pull opposing the wakeup-level so the SoC holds the pad at the
inactive level.
Signed-off-by: Jacob Wienecke <jacob.wienecke@nxp.com>
Add a pin controller driver for the WCH CH570 SoC.
Implements `pinctrl_configure_pins` to enable GPIO initialization and
alternate function configuration.
Update hal_wch revision in west.yml and hal_ch32fun.h to sync with
changes merged in zephyrproject-rtos/hal_wch#6
Signed-off-by: Elie Carrot <elie.carrot@smile.fr>
power.c calls PMCTLSetVoltageRegulator() from a SYS_INIT() hook that
is meant to always run, but CMakeLists.txt only compiled the file
when CONFIG_PM was enabled. With CONFIG_PM=n, the file was skipped
entirely and the DC-DC regulator was never selected.
Compile power.c unconditionally. Its own "#ifdef CONFIG_PM" guard
already excludes the PM-only code when CONFIG_PM is disabled.
Verified by checking that power_initialize is run
with CONFIG_PM=n.
Signed-off-by: Min Xu <m-xu@ti.com>
Signed-off-by: Lars Thalian Morstad <l-morstad@ti.com>
Assisted-by: Claude:claude-sonnet-5
Add Kconfig symbols for the MCXA537 SoC and MCXA537VLL part-number
variant. Select the MCXAXX7 SoC series for MCXA537.
Signed-off-by: Julian Paul <julian.paul@siemens.com>
Add support for the AE822FA0E5597BS0 SoC from the Ensemble
E8 series. The SoC contains two Cortex-M55 CPU clusters:
RTSS-HP (Real Time SubSystem - High performance), RTSS-HE
(Real Time SubSystem - High Efficiency) and a Cortex-A32
CPU cluster: APSS (Application Processor SubSystem). Support
for all three clusters has been added.
Signed-off-by: Silesh C V <silesh@alifsemi.com>
Keep the RTC timer retention state in RTC FAST memory,
so time reads remain safe when flash is unavailable during sleep.
Carve CONFIG_RESERVE_RTC_MEM from the end of usable LP RAM on
C5/C6/P4 so the timer retention slot sits before retainedmem/mbox,
add the missing C6 guard, and assert the reserved section fits.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Use #include <> instead of #include "" to include a header file which path
is not relative to the directory path of the file emitting the #include
directive.
This change was made running scripts/check_quoted_includes.py script
proposed in https://github.com/zephyrproject-rtos/zephyr/pull/112135
with the Linux shell command below and manually selecting the applicable
changes:
$ scripts/check_quoted_includes.py -w soc/realtek
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
Add SOC_ESP32_APPCPU_TARGET, a hidden symbol set whenever the
build targets the APPCPU image of a dual-core SoC. Replace all
places that checked SOC_ESP32_APPCPU and SOC_ESP32S3_APPCPU
together with the new symbol.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
This commit adds a compile time check to ensure that the ESP32 P4
only builds with supported frequencies. The later revisions go up
to 400 MHz, but the earlier revision stops at 360 MHz.
Assisted-by: Claude:claude-opus-4.8
Signed-off-by: Perry Naseck <pnaseck@media.mit.edu>
Replace the placeholder sai nodes, which carried a compatible with
no binding or driver, with real nxp,mcux-i2s nodes: MC_CGM clocks,
eDMA channels and requests (SAI0 on DMAMUX0, SAI1 on DMAMUX1), and
the bus clock as bit clock source since this SoC has no audio PLL
or MCLK routing. For the same reason, default I2S_HAS_PLL_SETTING
to n so the driver derives the bit clock from the module clock.
The nodes stay disabled; the existing delete-node entries of the
smaller derivatives are unaffected.
Verified with tests/drivers/i2s/i2s_speed on frdm_mcxe31b.
Signed-off-by: Lucien Zhao <lucien.zhao@nxp.com>
NXP_RF_IMU was already selected by default when CONFIG_IEEE802154 is
enabled. Extend this to also cover CONFIG_NXP_IEEE802154_MAC, which
uses the NBU co-processor for 802.15.4 without going through the
standard IEEE 802.15.4 driver.
Signed-off-by: Cristian Bulacu <cristian.bulacu@nxp.com>
Header file include/zephyr/sys_clock.h is deprecated and will be removed
someday. Update the whole file tree to include zephyr/sys/clock.h
straight instead of zephyr/sys_clock.h.
This change was made running the sed shell command below:
$ sed -i 's/zephyr\/sys_clock\.h/zephyr\/sys\/clock\.h/' \
`grep -rsl "zephyr/sys_clock\.h" soc/`
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
We updated the XEC clock control driver to support MEC174x/5x
and move away from hard to maintain CMSIS register structures.
Addition device tree properties were added for tuning the driver's
XTAL configuration sequence. Note: MEC15xx does not have the
clock monitor hardware for checking XTAL health and no way to
fallback if the XTAL fails.
Many MEC15xx/MEC172x legacy Zephyr drivers are using XEC specific
clock control driver PCR sleep and reset APIs. Until all old
drivers are converted to use the same functionality from the MEC SoC
layer we must keep these APIs. We converted them to call the SoC
layer. Once all drivers have been converted we can removed these
custom APIs from the clock control driver.
The domain clock-cells parameter was renamed to clkid matching usage
in the DW I2C driver and many other clock control drivers.
We changed domain to clkid in the only two drivers remaining that
use it, interrupt-controller and crypto.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
We added register defines and macros required to port the
XEC clock control driver to MEC174x/5x and remove CMSIS
register structures. Only specific SoC families and variants
include I3C hardware with a specific I3C PLL clock of 192MHz.
We added HAS_MCHP_MEC_I3C to MEC175x and MEC165xB. The clock
control driver will use this to detemine if it should response
to queries and control of the 192MHz I3C clock.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
pm_state_set() called xthal_window_spill(), the Cadence Xtensa
HAL's register window spill routine, before saving core context
for PM_STATE_SOFT_OFF (D3). Zephyr has its own native equivalent,
xtensa_spill_reg_windows, meant to be entered directly via CALL0
ABI (only A0 needs to be saved/restored by the caller). Use it
instead of pulling in the HAL routine.
Signed-off-by: Liam Girdwood <liam.r.girdwood@linux.intel.com>
Use #include <> instead of #include "" to include a header file which path
is not relative to the directory path of the file emitting the #include
directive.
This change was made running scripts/check_quoted_includes.py script
proposed in https://github.com/zephyrproject-rtos/zephyr/pull/112135
with the Linux shell command below and manually selecting the applicable
changes:
$ ./scripts/check_quoted_includes.py -w soc/espressif
Signed-off-by: Etienne Carriere <etienne.carriere@st.com>
In order to stabilise USE_SWITCH, it is best if we can
test it in the CI to avoid regressions. This commit
enables USE_SWITCH for corstone300 and corstone320.
USE_SWITCH is left off for corstone310/315 so that
the CI tests both the feature being enabled and disabled.
Signed-off-by: Laurie Fay <Laurie.Fay@arm.com>
Enables CTIMER clock divider that is halted out of reset.
As with the divider halted, the CTIMER receives
no functional clock, so the first register access made
by HAL CTIMER_Init() hanged the system during driver initialization.
Tested on LPCXpresso55s36.
Signed-off-by: Andrej Butok <andrey.butok@nxp.com>
Commit 3953f4b43d ("arch: arm64: mmu: map the GIC regions in the
arch core") added automatic mapping of every reg bank of the "arm,gic"
DT node in arch/arm64/core/mmu.c (mmu_gic_regions[]), explicitly to
let individual SoCs stop repeating those entries in their own
arm_mmu_regions.c. versal, versal2 and versalnet were not updated
when that landed, so their GIC reg banks were mapped twice: once by
the SoC's own mmu_regions[], and again by the generic
mmu_gic_regions[] pass in setup_page_tables().
Remove the redundant per-SoC GIC entries; the generic mapping in
arch/arm64/core/mmu.c already covers them with identical attributes
and addresses. versal's arm_mmu_regions.c had no other entries, so
with the GIC ones gone it maps nothing at all - delete the file
entirely and let arch/arm64/core/mmu_default_config.c's __weak empty
mmu_config apply instead, rather than keep a source file whose only
content is an empty array. versalnet's file is in the same state in
this tree and gets the same treatment. versal2 keeps its file, since
it still maps several other device regions.
Fixes: 3953f4b43d
("arch: arm64: mmu: map the GIC regions in the arch core")
Signed-off-by: Appana Durga Kedareswara rao <appana.durga.kedareswara.rao@amd.com>
When flashing this AMP part and running firmware built for the M55 with
--sysbuild using west flash --erase would erase twice leaving the part
in a non-bootable state.
Add the needed soc.yml runner options to only run --erase once
regardless of how many images were being flashed.
Signed-off-by: Tom Burdick <thomas.burdick@infineon.com>
add support for the esp32 in the generic
dwc_mac driver.
esp32 specific code is based
the init of the original esp32 eth driver in zephyr.
The esp32 uses HW version 3.70.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
For I2C target wake, the SMB controller must stay enabled during
suspend-to-ram so it can sample SCL/SDA and wake on a START from an
external master. Skip disabling a controller whose START-bit wake is
enabled in the deep-sleep block save; others are disabled as before.
Signed-off-by: Manimaran A <manimaran.a@microchip.com>
Add the initial pinctrl driver support for the ELAN EM32 SoC family.
This driver provides basic pin multiplexing and electrical configuration
support. Device tree bindings are included for pin function definitions.
Signed-off-by: Johnny Chuang <johnny.chuang@emc.com.tw>
Add the infoctrl syscon register block to the EM32Fxxx SoC DTSI.
The block contains oscillator trim and device information registers.
Add register offsets and field masks in soc_infoctrl.h for driver use.
Signed-off-by: Johnny Chuang <johnny.chuang@emc.com.tw>
Emit the option settings sections only when the image is a standalone
app or MCUboot. Don't emit the option settings when the image is an
app being chain-loaded by MCUboot.
This avoids populating addresses outside of the code-partition area
in the app image.
Signed-off-by: Jeremy Dick <jdick@pivotint.com>
On ESP32-P4, an mret whose mcause.interrupt does not match the trap
entry type corrupts the CLIC state: after an exception-entered trap
(e.g. ecall context switch) exits with mcause.interrupt forced set,
the illegal-instruction exception is never delivered again.
Match mcause.interrupt to the trap entry type instead of forcing it,
clearing mpil for exception-saved frames so they resume at level 0.
Fixes#114028
Signed-off-by: Hongquan Li <hongquan.li@processmission.com>
