After commit b1afb494b0, zephyr,flash points to the
soc-nv-flash child node instead of the
nxp,imx-flexspi-nor controller. This shifts the DTS
hierarchy by one level, so
DT_PARENT(DT_CHOSEN(zephyr_flash)) now returns the
flash controller node, not the FlexSPI bus node.
Use DT_CHOSEN(zephyr_flash_controller) to directly
reference the flash controller, and DT_PARENT of it
to reach the FlexSPI bus where needed.
Signed-off-by: Ofir Shemesh <ofirshemesh777@gmail.com>
Having a differing number of ACL buffers available between the host
and controller causes unnecessary "impedance" when communicating over HCI.
The Zephyr Bluetooth host also warns about this during initialization:
Num of Controller's ACL packets != ACL bt_conn_tx contexts (15 != 3)
Update the default for BT_BUF_ACL_TX_COUNT to match the controller. Also
update BT_BUF_EVT_RX_COUNT and BT_CONN_TX_MAX appropriately. The latter
should generally match TX_COUNT, while the former needs to be at least as
large to deal with Number of Completed Packets events from the controller.
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
The syslib delay function are implemented in an assembly file.
Even with the relocation done in CMakeLists.txt this file does not
properly get copied because gen_relocate_app.py does not keep
in consideration plain regions (e.g. just .text rather than .text.xyz).
Therefore force the relocation using the ramfunc and itcm linker
section for cm33 and cm55 respectively.
Signed-off-by: Laura Carlesso <laura.carlesso@infineon.com>
The linker region rwdata was including sections ramfunc
and itcm which should instead be placed in a code region.
Created itcm_mem.ld and ramfunc_mem.ld for cm55 and
cm33 respectfully to place the section accordingly.
Added the linker sources in cmakelists.txt
Signed-off-by: Laura Carlesso <laura.carlesso@infineon.com>
Now that the cores have dedicated executable regions
for the code relocation, give executable permissions only
to those rather than the entire RAM region.
Additionally, removed the rwdata exception for the assembly
file given that it now gets properly placed in the correct region
by the relocate script.
Signed-off-by: Laura Carlesso <laura.carlesso@infineon.com>
Change 'select ARM_MPU' to 'imply ARM_MPU' so that tests and
applications can override it with CONFIG_ARM_MPU=n. The previous
'select' caused a prefetch abort in the LLEXT module_build sample,
which disables MPU to allow execution from heap-allocated memory.
Signed-off-by: Ibrahim Abdalkader <i.abdalkader@gmail.com>
The SPI SRAM memory test runs on the entire mapped PSRAM
region during boot. At lower clock speeds (e.g. 40MHz),
this can take over 10 seconds for a 4MB device, delaying
startup significantly.
Remove the default y so the memtest is opt-in. Users can
still enable it with CONFIG_ESP_SPIRAM_MEMTEST=y when
needed for hardware validation.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The SPIRAM heap address was set from the linker symbol
_ext_ram_heap_start, which may not match the actual MMU
mapping at runtime. On SoCs with unified cache (C5, C6,
H2), the virtual address depends on MMU page allocation
and can differ from the linker estimate.
Use esp_psram_get_mapped_region() to obtain the actual
mapped address and size at runtime.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
The ext_dram_seg was placed at DROM_SEG_ORG + DROM_SEG_LEN
(0x43000000), but the MMU maps PSRAM into the first free
pages in the unified cache address space (0x42000000+).
This mismatch caused the SPIRAM heap to point to unmapped
memory, resulting in data corruption and crashes.
Move ext_dram_seg origin to IROM_SEG_ORG and add an
.ext_ram.dummy section that skips past both IROM and DROM
MMU page reservations, matching the runtime behavior of
esp_mmu_map_reserve_block_with_caps().
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
soc_random_enable() was called inside hardware_init() which
only runs for CONFIG_MCUBOOT and CONFIG_ESP_SIMPLE_BOOT. For
MCUboot-loaded apps (CONFIG_BOOTLOADER_MCUBOOT), hardware_init
is skipped, so soc_random_enable() never ran. However,
soc_random_disable() was called unconditionally in loader.c,
causing periph_module_disable() to decrement the peripheral
clock reference counter below zero. This prevented
periph_module_enable() from actually enabling the hardware
clock for any peripheral touched by soc_random_disable(),
such as I2S0 on ESP32, breaking drivers that depend on it.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Move to the post kernel. Set priority which is higher than the
IPC service and NRFS.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Wrap BT controller initialization with CONFIG_BT to prevent its
background thread from starting in non-Bluetooth applications.
This avoids unexpected preemption that causes kernel scheduler tests
like `priority_preemptible_wait_prio` to fail.
Signed-off-by: Zhiyuan Tang <zhiyuan_tang@realsil.com.cn>
Setting NUM_IRQS on RISC-V core to only the IRQ's used (up to GPIOTE30_1)
where VREGUSB, LFXO, LFRC, HFXO64M, AUXPLL interrupts aren't
used in drivers.
This is because on RISC-V with CONFIG_RISCV_GP, the linker may relax
accesses to some globals into gp-relative instructions; the offset from
__global_pointer$ to each such symbol must fit in a 12-bit signed range
(+/-2 KiB). _sw_isr_table in RAM is NUM_IRQS × 8 bytes and sits between
small data and much of .bss, so a smaller NUM_IRQS shortens that gap
and can keep symbols such as _kernel within gp-relative range, avoiding
R_RISCV_GPREL_I relocation truncation at link time.
Signed-off-by: David Jewsbury <david.jewsbury@nordicsemi.no>
Prevent unused function warning that comes from having a control module
node but no ti,unlock-offsets property. Do this by checking for the
aforementioned property alongside already present compat string.
Signed-off-by: Amneesh Singh <amneesh@ti.com>
RT1166 and RT1176 CM4 parts use the MCUX LMEM cache block
and expose both code and system-bus cache in their HAL
feature headers.
Select the LMEM cache driver path, advertise both ICACHE
and DCACHE, and default these CM4 builds to
CACHE_MANAGEMENT with the external cache driver.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
This commit introduces 2 changes:
- cleans up the mpu initialziation, the old function is not
required because the initialziation is done properly via
mpu_regions.c for all cores
- defaults to using SystemCoreClockSetup instead of
SystemCoreClockUpdate because the former takes the
input from DT whereas the latter would read the info
from the HF clocks which in case of TF-M are secured
and not directly accessible from the cm33/ns (if SRF is
not set up)
Signed-off-by: Laura Carlesso <laura.carlesso@infineon.com>
71aa3be37b removed the directive which used
to source these files but forgot to delete them - do so now.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
To address the "warning: orphan section", added
.llext_heap, .llext_ext_heap, and .llext_metadata_heap
sections to the #ifndef CONFIG_USERSPACE noinit section
in the linker script, wrapped in #ifdef CONFIG_LLEXT.
Signed-off-by: Bill Waters <bill.waters@infineon.com>
SweRV S4xx SoCs has an external interrupt controller by design.
The corresponding driver is enabled via CONFIG_SWERV_PIC.
However, it is not fully supported in the whisper simulator.
Accessing the controller's MMIO space will result in access
fault when PMP is enabled with catchall entry. To workaround
this, we simply skip building the driver so there will be no
invalid memory access at boot. For this to work correctly,
we need to implement some basic arch_irq_*() function to
utilize the internal interrupt controller so we can still
boot and test. For non-PMP boards, we still have the driver
enabled so it is built in CI to avoid breakage.
Signed-off-by: Daniel Leung <daniel.leung@intel.com>
This commit removes the unused mcr_regs.h header from the power.c file
in the MAX32 SoC directory.
The header is not required for current power management implementation.
Furthermore, since some MAX32 SoC variants do not include this specific
register definition, removing it prevents potential build failures and
improves cross-SoC compatibility within the series.
Signed-off-by: Furkan Akkiz <hasanfurkan.akkiz@analog.com>
If Zephyr is booted from U-Boot, ENET clock has been initialized by
U-Boot and it works, but if Zephyr is booted by using SPSDK runner,
ENET clock is not initialized and ENET will not work, so adding ENET
clock initialization in Zephyr to fix this issue.
Fixes: #106398
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
The ulp_shm DTS node at 0x3bf0 overlapped with the last
16 bytes of the ulp_ram region (0x0..0x3c00) on both
ESP32-C5 and ESP32-C6.
Move ulp_shm to 0x3c00, right after ulp_ram, and shift
lp_rtc from 0x3c00 to 0x3c10 (shrinking it by 16 bytes
from 0xf8 to 0xe8) to make room. All other regions
(retainedmem, ipc_shm, mbox0) keep their addresses.
Update LP core linker scripts to stop subtracting
shared mem size from the ram segment length, since
ulp_shm is now outside the coprocessor reservation.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Mark .noinit as NOLOAD to prevent LLEXT heaps included in
snippets-noinit.ld from being marked as PROGBITS.
Fixes#105858
Signed-off-by: Lauren Murphy <lauren.murphy@intel.com>
NXP FlexSPI NOR flash nodes were missing the soc-nv-flash child
node expected by Zephyr's flash map API.
Without this child node, DT_MTD_FROM_FIXED_PARTITION resolved to
the FlexSPI memory controller instead of the flash device. Since
the controller has api = NULL, MCUboot could hit a NULL pointer
dereference during boot on Zephyr 4.4.
Fix this by updating the DTS structure to match the soc-nv-flash
convention used by the flash map infrastructure.
Changes:
- add a soc-nv-flash child under each nxp,imx-flexspi-nor node
- move erase-block-size, write-block-size, and partitions into it
- add ranges to flash controller nodes for address translation
- update zephyr,flash to point to the soc-nv-flash child
- add zephyr,flash-controller chosen for the flash driver node
- remove soc-nv-flash.yaml from nxp,imx-flexspi-nor.yaml
- use zephyr,flash-controller in flash CMake XIP decisions
- update FlexSPI XIP Kconfig logic to walk to the grandparent
This keeps the controller and flash device roles separate and
restores correct flash map resolution for MCUboot and XIP logic.
Signed-off-by: Ofir Shemesh <ofirshemesh777@gmail.com>
Since RM1170 Rev. 5 the RC400 gate control bits are marked reserved.
Remove the call to CLOCK_OSC_GateOscRc400M since the headers need
updating to remove it completely as done with the RT1180.
Signed-off-by: Bas van Loon <bas@arch-embedded.com>
- xt-clang seems to generate some memory access patterns which
result in the simulator accessing incorrect memory or messing
with cached TLB entries when spinlock validation is enabled.
- This is the same issue that was fixed for ace40 in commit
b98fc2740a (fixes#100885). Apply the same workaround to
ace30/ptl/sim and ace30/wcl/sim.
Signed-off-by: Jjateen Gundesha <jjateen97@gmail.com>
Replace SOC_SERIES_CH32V00X with SOC_SERIES_QINGKE_V2C to maintain
consistent naming across SOC series.
Signed-off-by: Jianxiong Gu <jianxiong.gu@outlook.com>
- Add shared_memory to custom mpu regions for Infineon pse84 soc series
- This resolves a bug in the wdt_basic_api test running on the m55 core
for both the kit_pse84_eval and kit_pse84_ai platform
Signed-off-by: McAtee Maxwell <maxwell.mcatee@infineon.com>
These Kconfigs were showing up in my build for a completely different
vendor. These are meant to be hidden Kconfigs meaning they do not have
descriptor strings next to their type.
Signed-off-by: Tom Burdick <thomas.burdick@infineon.com>
SoC, DTS, and board files should live in directories named after the
vendor prefix so rename all occurrences of synaptics/ to syna/.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The real RAM size from DT is correct but the power manager API expect to
receive either 192/256/320 KB value, so we need to round it up to the
next boundary to avoid powering down the top M4 SRAM bank.
Signed-off-by: Martin Hoff <martin.hoff@silabs.com>
POWER_ClearWakeupStatus for RTC was called on the PM3 exit path,
clearing the status before the application could query the wakeup source
via NXP_GET_WAKEUP_SIGNAL_STATUS().
Move the clear to the PM3 entry path, just before re-arming the wakeup
source. This matches the existing GPIO wakeup status handling which
already clears on entry.
Signed-off-by: Jacob Wienecke <jacob.wienecke@nxp.com>
The system clock frequency was not initialized, causing the
`Cy_SysLib_Delay` family of PDL functions to delay for an incorrect amount
of time.
This was fixed for the M55 in #101015, but the fix was not applied to the
M33.
Fixes#106232.
Signed-off-by: Jonathan Keller <jonathan.keller@infineon.com>
Wire the Kinetis LMEM-capable SoCs into the generic cache
management path by selecting the LMEM driver, enabling the
available instruction and system-bus cache capabilities, and
defaulting these parts to CACHE_MANAGEMENT with the external
cache backend.
Keep MCUX eDMA descriptors in the default SRAM placement on
SYSMPU-based Kinetis parts. Their SRAM region remains outside
the cached LMEM area, so they do not use the generic
NOCACHE_MEMORY path.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Update the UICR generator image to correctly track outputs and
dependencies as these depend on the options provided. This fixes
an issue where the UICR generation step was always rebuilt when
secondary PERIPHCONF was disabled, since secondary_periphconf.hex
was specified as an output but never produced. It also fixes
missing outputs/dependencies for mpcconf.hex/secondary_mpcconf.hex.
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
Add Kconfig and soc.yml entries for the BL706C00Q2I, which is the
base BL706 in QFN48 package without internal flash or PSRAM.
Signed-off-by: William Markezana <william.markezana@gmail.com>
In driver file flash_stm32wba_fm.c, rename ble_ctrl_work_q
to ble_ctle_work_q and make ble_ctle_work_q non-static
in SoC code
Signed-off-by: Vincent Tardy <vincent.tardy@st.com>
NRF_RTC and its numbered variants (NRF_RTC0, NRF_RTC1, NRF_RTC2,
NRF_RTC130, NRF_RTC131) are not defined on RTC-less SoCs such as
the nRF54L and nRF54H series. Wrapping the CHECK_DT_REG calls in
#ifdef guards prevents a build error when a devicetree node (e.g.
an external I2C RTC) happens to use one of these node labels.
Fixes#101686
Signed-off-by: Mohit Talwar <talwarmohit2005@gmail.com>
Add sleep hold flag to allow setting groups of pins to
automatically hold pad value during low power states (light/deep sleep).
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Add hardware pad function, configurable in DTS, which holds the pin
state when transitioning to a low power state (light/deep sleep).
Once set in DTS, PM interface will automatically handle holding
the pin state before transitioning it into a low power state.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
Guard the STM32WBAX power driver `mpu_state` variable with
CONFIG_ARM_MPU.
With this change, CONFIG_PM=y and CONFIG_ARM_MPU=n now build
correctly on STM32WBA.
Signed-off-by: Lubos Koudelka <lubos.koudelka@st.com>
Include file for mapping DFP macros to follow a common
macro name across multiple SoC for sercom uart g1 driver
Signed-off-by: Fabin V Martin <Fabinv.Martin@microchip.com>
