The default 'near' mode results in zero exit latency ticks, which
prevents `sys_clock_set_timeout` from being called. This causes
the system to remain stuck in deep sleep modes. Use ceiling method
to obtain a nonzero exit latency tick count.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
Fixed build fail since 4c93fcd35b.
Fixed test run fail on Ambiq platforms.
Added Ambiq section in the test.
Signed-off-by: Swift Tian <swift.tian@ambiq.com>
Transition nrf54h away from the soc specific gpd
(global power domain) driver which mixed power domains, pinctrl
and gpio pin retention into a non scalable solution, forcing soc
specific logic to bleed into nrf drivers.
The new solution uses zephyrs PM_DEVICE based power domains to
properly model the hardware layout of device and pin power domains,
and moves pin retention logic out of drivers into pinctrl and
gpio, which are the components which manage pins (pads).
Signed-off-by: Bjarki Arge Andreasen <bjarki.andreasen@nordicsemi.no>
Add a new shared_heap section. Update the xtensa_soc_mmu_ranges structure
to include a new memory range for the shared heap.
Signed-off-by: Adrian Warecki <adrian.warecki@intel.com>
GIC redistribute and ITS on i.MX 95 is DMA noncoherent, so enable
CONFIG_GIC_V3_RDIST_DMA_NONCOHERENT and CONFIG_GIC_V3_GIC_DMA_NONCOHERENT.
Signed-off-by: Jiafei Pan <Jiafei.Pan@nxp.com>
Made some order in the Kconfig's for silabs series 2 socs.
Made a distinction between silabs "generic family" (e.g. xg21) and silabs
"device family" (e.g. efr32mg21).
Signed-off-by: Yishai Jaffe <yishai1999@gmail.com>
Since the change to HWmv2 we do not need to have this options in the
top level anymore. Let's move them into the top level Nordic SOC
Kconfig file.
(Note they moving into into each individual soc Kconfig would
add a dependency on SOC_FAMILY_NORDIC_NRF which is not set for
bsim targets)
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Add build asserts for "memory-regions" property in nrf drivers which is
required on targets with DMM for saadc, pdm, pwm, twim, twim_rtio, twis,
tdm, uarte, spim and spis. On targets where the property is not required
the assertion macro expands to nothing.
Signed-off-by: Michał Bainczyk <michal.bainczyk@nordicsemi.no>
Add initial support for i.MX 95 15x15 LPDDR4x EVK board. This board
uses the i.MX 95 15x15 SoC that shares many similarities to the
already supported i.MX 95 19x19 SoC used for the i.MX 95 19x19
LPDDR5 EVK.
This enables Zephyr to boot and run on the i.MX 95 15x15 EVK and
provides a foundation for further peripheral enablement and
application development.
Signed-off-by: Aziz Sellami <aziz.sellami@nxp.com>
Adds SoC support for the STM32C091, and the STM32C092 SoCs
which are part of the STM32C0 series.
Signed-off-by: Thomas Stranger <thomas.stranger@outlook.com>
Booting the radio core when it is not programmed will typically
cause a reset loop. This can happen when programming multiple
images to a device, and the app core image is programmed before
the radio core.
With this change we avoid the reset loop in that case.
Signed-off-by: Håkon Amundsen <haakon.amundsen@nordicsemi.no>
Add support for generating UICR and associated artifacts in a
format compatible with IronSide SE, to be used for Nordic SoCs
in the Haltium family.
The main feature added with this is the ability to configure certain
global domain peripherals that are managed by the secure domain
through setting UICR.PERIPHCONF. This register points at a blob of
(register address, register value) pairs which are loaded
into the peripherals by IronSide SE ahead of the application boot.
The added helper macros in uicr.h can be used to add register
configurations to the PERIPHCONF. Entries added through these macros
are then extracted by a script, post-processed and placed in a blob
located at specific part of MRAM.
A default PERIPHCONF configuration has been added for the nrf54h20
soc to support the standard BLE use case (matching the configuration
in the soc devicetree).
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
With IronSide SE there is only one defined UICR which is at
the location of the APPLICATION UICR. Update the devicetree
definition accordingly, and use the "nordic,nrf-uicr" compatible
on the node since the domain distinction added by the v2 compatible
is no longer relevant.
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
This replaces the legacy SDFW compatible board configuration with the
IronSide SE compatible one, thus removing support for running samples
and tests on nRF54H20 devices with the old firmware.
All applications are expected to work on `nrf54h20dk/nrf54h20/cpuapp`
out of the box. For other board targets, all applications are expected
to boot, but may require additional peripheral configuration in UICR.
Build system support for the new UICR format is to be added separately.
Co-authored-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
Signed-off-by: Jonathan Nilsen <jonathan.nilsen@nordicsemi.no>
Signed-off-by: Grzegorz Swiderski <grzegorz.swiderski@nordicsemi.no>
Add soc_early_init_hook() function to update the SystemCoreClock variable,
which represents the reference clock.
Signed-off-by: Arnaud Pouliquen <arnaud.pouliquen@foss.st.com>
Default MPU configuration marks whole flash area as cacheable. When
reading from an erased section of flash, cache controller may fill cache
lines with ECC corrected data. To prevent this, disable caching on
storage section so that ECC workaround can be applied during reads and
correct data is returned.
Signed-off-by: Tahsin Mutlugun <Tahsin.Mutlugun@analog.com>
To reduce the SEMC clock to a usable speed we had to divide down
the output clock of System PLL2 PFD1. To do this I had to override
the hardcoded defaults. This commit adds the flexibility to
override them in your board files.
Signed-off-by: Bas van Loon <bas@arch-embedded.com>
Errata ERR050396 causes data corruption if writes happen to TCM memory
so work around it by not marking AXI transaction cacheable. Workaround
taken from NXP SDK example.
Signed-off-by: Bas van Loon <bas@arch-embedded.com>
Add stm32l1_disco and nucleo_l152re overlays for testing
sleep/stop/standby modes:
- samples/boards/st/power_mgmt/blinky;
- samples/boards/st/power_mgmt/wkup_pins;
I've measured consumption for each low-power mode:
- low-power sleep ~1.72mA;
- stop mode ~324uA;
- standby mode ~2.2 uA;
It's possible to use RTC as idle timer to exit from stop mode.
Signed-off-by: Oleh Kravchenko <oleg@kaa.org.ua>
Adds additional MPU memory permissions to userspace applications by
default. This change addresses an MPU fault encountered when running
tests/kernel/common and tests/drivers/adc/adc_api.
This approach opens additional memory locations up to user space access.
This assumes that end users of applications will tune the MPU regions for
the needs of that application.
Signed-off-by: John Batch <john.batch@infineon.com>
If the application uses slot 1 (i.e. in Direct XIP mode),
boot radio slot 1 instead of slot 0.
Signed-off-by: Tomasz Chyrowicz <tomasz.chyrowicz@nordicsemi.no>
Currently the linker script for ACE defines memory regions for
literals in interrupt vector memory. This wastes memory and leads to
link failures when CONFIG_USERSPACE is enabled. Remove those regions
to reclaim 8 bytes per vector and fix linking. Also remove duplicated
level 4 interrupt vector sections and replace spaces with TABS.
Signed-off-by: Guennadi Liakhovetski <guennadi.liakhovetski@linux.intel.com>
There is no reason to place sli_siwx917_soc.h under #ifdef. Then, we can
get rid of the #if in the body of soc_early_init_hook().
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
Variable CONFIG_SOC_PART_NUMBER is only used in CMakeLists.txt of
hal_silabs. In fact, this variable can be easily calculated from CONFIG_SOC
by changing lower case in upper case.
So, let's drop this useless variable.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
SOC_GECKO_SDID is no more referenced since commit 955aca6c0 ("soc: silabs:
Initialize clock manager HAL from DT"). We can safety drop it.
Signed-off-by: Jérôme Pouiller <jerome.pouiller@silabs.com>
mspm0 family of SoC series is split into three category,
mspm0g - high performance
mspm0l - low power
mspm0c - entry level
With G already part added, add support for L series of SoC's.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
mspm0 series (currently g, l and c) shares the common SoC
level init functions and pin control/muxing configurations.
To avoid duplication for each series, create a common path
and move the SoC and pin control definitions.
Other common functionalities like Power Management, Power off
handling will be added in future, which will be common across
series.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Flash size and address is extracted from dts, which will be common
for all the upcoming series of SoC's like MSPM0L, MSPM0C. Move the
flash address and size to soc level defconfig.
Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
Systick is already enabled before late hook got called. In certain
circumstances systick could flooding the core and thus only handling
systicks. Enabling cache earlier using soc_early_init_hook ensures
that systick get handled quicker.
Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
m33 must ensure the TCM is ECC clean by initializing all dtcm memories
Otherwise, it can only run it by loading m33 under uboot.
Based on this fixed, we can run M33 by mkimage into flash.bin.
Signed-off-by: Yongxu Wang <yongxu.wang@nxp.com>
We want to simplify the maintenance burden and confusion of having
more than one driver for the same kernel timer peripheral used on
all Microchip MEC parts. The XEC version of the driver was converted
register definitions in the driver. Register access is performed using
Zephyr sys_read/write architecture specific inline routines. Driver DT
YAML was updated to use phandle for the 32-bit basic timer used for
ARCH_HAS_CUSTOM_BUSY_WAIT support, basic timer max value property,
and GIRQ interrtup aggregator hardware information.
SoC part Kconfigs, chip level/board level DTSI updated to use the
unified driver.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
All parts in the Microchip MEC family support ARM JTAG/SWD/SWO.
We add Kconfig logic to allow building projects with Segger's
RTT debug for Cortex-M.
Signed-off-by: Scott Worley <scott.worley@microchip.com>
Add ae350/clic soc, which shares the same peripherials as AE350 PLIC
platform but uses CLIC instead of PLIC, with different IRQ number.
Signed-off-by: Jimmy Zheng <jimmyzhe@andestech.com>
Turn MCX series into families.
Reasoning:
1. The MCX SOCs are quite different from each other and having them all
under one family in the HWMv2 hierarchy is fruitless because there
are so many differences that it is confusing to try to introduce
family-level code and configs since they would each only apply to a
subset of the series. There is almost nothing that can be shared
between all of them. Which is why there are comments in the MCX
family files saying not to put anything in them. This is a technical
waste.
2. Therefore, turning all of them into families is almost 0 effort and
makes sense. It will allow these different types of MCX to be
further subdivided into series in the future as the MCX portfolio
expands and such division will be necessary as new SOCs within each
letter family are released.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Add a STM32_APP_IN_EXT_FLASH to determine that an application
is eXecuting in Place on an external xspi flash.
That will control the clock init of this external xspi controller.
Signed-off-by: Francois Ramu <francois.ramu@st.com>
So we can enable features for both the real and simulated
targets based on these same options.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
In preparation for simulated nRF54LM20 targets, let's add kconfig
options aking to the ones we have for the nRF54L15 devices.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
After removing NATIVE_APPLICATION, only NATIVE_LIBRARY is
possible with SOC_POSIX.
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Following changes in e35ac8f and 14c1b4a to how external Q/OSPI Flash
nodes are declared in DT for boards with STM32 SoCs, FLASH_BASE_ADDRESS
needs to be set manually similar to XSPI Flash, so that it does not
default to (dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH)) which gives 0.
This change is critical for running apps with MCUboot from external
Q/OSPI Flash.
Signed-off-by: Abderrahmane JARMOUNI <git@jarmouni.me>
fix ulpm driver polarity issue.
when pin-pol set to falling need to set the POL bit to 1.
when pin-pol set to rising need to set the POL bit to 0.
Signed-off-by: Titan Chen <titan.chen@realtek.com>
