Commit graph

503 commits

Author SHA1 Message Date
Henrik Brix Andersen
a281dbfb6d soc: riscv: privilege: add neorv32 processor suppport
Add support for the open-source NEORV32 RISC-V compatible processor
system (SoC).

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-10-15 09:46:53 -04:00
Dino Li
48e0dbbca4 soc: it8xxx2: enable CONFIG_RISCV_GP
This will bring better performance on accessing global variables
that are in 4K span by the GP register.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2021-10-13 06:17:56 -04:00
Tim Lin
41c9b71450 ITE: soc: add cpu idle task
Implement the CPU idle task. The system should enter this task when
there is no any task to ensure power saving.

Tested on it8xxx2_evb board. It will reduce 12.5mA when system enters
the CPU idle task.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-10-08 13:01:06 +02:00
Dino Li
1e1c6151d7 soc: it8xxx2: enable CONFIG_UART_NS16550_WA_ISR_REENABLE_INTERRUPT
Fix issue where console get stuck.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2021-10-06 22:21:15 -04:00
Tim Lin
213c0c43e6 ITE: soc: pull-down GPIO L/K groups and set GPIOH7 output low at default
GPIO L/K groups:
On IT81202 (128-pins package), the pins of GPIO group K and L aren't
bonding with pad. So we configure these pins as internal pull-down
at default to prevent leakage current due to floating.

GPIOH7:
On IT81202/IT81302, the GPIOH7 isn't bonding with pad and is left
floating internally. We need to enable internal pull-down for the pin
to prevent leakage current, but IT81202/IT81302 doesn't have the
capability to pull it down. We can only set it as output low,
so we enable output low for it at initialization to prevent leakage.

After setting: power saving=2.26mA

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-10-04 20:41:37 -04:00
Felipe Neves
b97c2da2f2 interrupt_controller: intc_esp32c3: added intc driver
For esp32c3 and replaces the hardcoded interrupt
attaching procedures with this new driver.

Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-10-02 14:33:24 -04:00
Sylvio Alves
69311ccc3d soc: esp32: update clock configuration calls
Removed duplicated calls in clock subsystems.
Move proper includes to soc specific.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2021-09-30 21:42:20 -04:00
Felipe Neves
6020afe46a soc: riscv: esp32c3: update west version
to enable wifi subsystem for esp32c3, also
update the linker with proper wlog sections.

Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-09-30 06:39:55 -04:00
Felipe Neves
d4ed7f69d4 drivers: entropy: esp32: enable rng driver
for esp32c3 allowing wifi subsystem to use inside
its driver.

Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-09-30 06:39:55 -04:00
Ruibin Chang
d16ae76d30 ITE drivers/kscan: add keyboard scan driver for it8xxx2_evb
Add keyboard scan driver for board it8xxx2_evb.

Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
2021-09-28 19:53:15 -04:00
Dino Li
29d039335f cleanup: soc: it8xxx2: remove unnecessary code
Code removed:
- IT8XXX2 doesn't support soc level software interrupt hence remove
  them.
- To use common macro to access csr (control status register).
- To remove CONFIG_RISCV_HAS_PLIC related code. IT8XXX2 uses its own
  interrupt controller code.
- To remove ite_write and ite_read. We don't use them anymore.

Code changed:
- Return true from arch_irq_is_enabled() when external interrupt-enable
  bit, and SOC's IER are both true.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2021-09-28 11:36:23 +02:00
Alexandre Mergnat
05f205066b copyright: add missing license
Solderpad Hardware License

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
2021-09-24 17:07:37 -04:00
Torsten Rasmussen
15e834a687 linker: __data_region_start equal to __data_start
Fixes: #38591, #38207, #37861

The commit 65a2de84a9 aligned the data
linker symbol for sections and regions.

The data region symbol start has been placed outside the sections thus
being defined as the address of the region before alignment of the first
section in the data region, usually the `datas` section.

The symbol defining the start address of the data section is after
section alignment.
In most cases the address of the data region start and datas section
start will be identical, but not always.
The data region symbol is a new linker symbol and existing code has
been depending on the old data section start symbol.
Thus, the update to the use of the data region start symbol instead of
data ram start symbol thus results in a different address when the
section is aligned to a different address.

To ensure the original behavior in all cases, the data region start
address is now moved inside the data section.

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2021-09-24 15:13:13 -04:00
Henrik Brix Andersen
2e242c51fb soc: riscv: ite: it8xxx2: guard SoC Kconfig options
Guard the IT8XXX2 SoC specific Kconfig options with 'if ... endif'.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-09-15 23:11:43 -04:00
Henrik Brix Andersen
91a0372b5c soc: riscv: priv: call __reset during boot
Call __reset instead of directly calling __initialize from the common
RISC-V privileged SoC vectors __start. This allows injection of SoC
specific reset code just after setting up the machine trap vector.

RISC-V privilege SoCs without the need for custom reset code can set
CONFIG_INCLUDE_RESET_VECTOR=y to include a __reset stub which simply
calls __initialize.

Fixes: #38396

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-09-14 09:48:03 -04:00
Tim Lin
7a22dae91a ITE: soc: it8xxx2: add initialization setting for hibernate mode
Setting this bit will wake up CPU if it is in low power mode
and an interrupt is pending.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-09-03 09:56:17 -04:00
Tim Lin
234afe2d0d ITE: soc: it8xxx2: export PLL control routine to the head file
Export the PLL control routine to the head file for hibernate
mode accessing.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-09-03 09:54:52 -04:00
Katsuhiro Suzuki
ca853af0b9 soc: riscv: add initial support for SiFive Freedom U740
This patch adds support for SiFive Freedom U740 SoC.
First version is minimum only using UART, SPI and L2-LIM area.

Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
2021-09-03 09:52:26 -04:00
Katsuhiro Suzuki
82f75ed337 soc: riscv: add initial support for SiFive Freedom U540
This patch adds support for SiFive Freedom U540 SoC.
First version is minimum only using UART, SPI and DDR memory area.

Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
2021-09-03 09:52:26 -04:00
Tim Lin
f9a8a1dc0b ITE: soc: it8xxx2: move the timer registers to header file
The free run timer will be used to count before entering hibernate
mode. Move the related registers to the head file for accessing.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-09-03 08:07:08 -04:00
Jim Shu
78be3771bd soc: andes_v5: linker: fix many linker symbols name
PR #37938 aligns many linker symbols name like rom/rodata_regions ...,
but ae350 soc linker script doesn't update for that. Migrate all linker
symbols name to PR #37938 changes.

Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-09-01 12:27:14 -04:00
Jim Shu
d7b53226d1 soc: riscv: andes_v5: initial support of Andes L2 cache controller
This initial support of L2C driver only contains cache enable and HW
capability checking. Cache management operation isn't supported yet
in this driver.

Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-08-30 13:40:14 -04:00
Jim Shu
3b7221363a soc: riscv: andes_v5: introduce Andes V5 PMA to support nocache memory
Andes V5 PMA can let SW programmably configure memory attribute of
physical memory region. This commit enable CONFIG_NOCACHE_MEMORY of
Andes V5 CPUs based on the PMA. Use PMA region 0 to set whole nocache
section as uncached memory.

Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-08-30 13:40:14 -04:00
Jim Shu
7db0fedcfe soc: riscv: andes_v5: add custom CSR context switch support
Support custom RISC-V CSR context switch for Andes V5 CPUs.
Both AndeStar V5 DSP and PowerBrake features have it's own CSR to be
saved for thread and ISR context, so adding these CSRs into the RISC-V
SOC context management framework (CONFIG_RISCV_SOC_CONTEXT_SAVE).

Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-08-30 13:40:14 -04:00
Jim Shu
62a30eba86 soc: riscv: add initial support of andes_v5 soc series
Add andes_v5 SoC series and andes_ae350 SoC. It includes
soc initialization code, linker script, and custom CSR encoding.

Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-08-30 13:40:14 -04:00
Torsten Rasmussen
3d82c7c828 linker: align _image_text_start/end/size linker symbols name
Cleanup and preparation commit for linker script generator.

Zephyr linker scripts provides start and end symbols for each larger
areas in the linker script.

The symbols _image_text_start and _image_text_end sometimes includes
linker/kobject-text.ld. This mean there must be both the regular
__text_start and __text_end symbols for the pure text section, as well
as <group>_start and <group>_end symbols.

The symbols describing the text region which covers more than just the
text section itself will thus be changed to:
_image_text_start -> __text_region_start
_image_text_end   -> __text_region_end

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2021-08-28 08:48:03 -04:00
Torsten Rasmussen
c6aded2dcb linker: align _image_rodata and _image_rom start/end/size linker symbols
Cleanup and preparation commit for linker script generator.

Zephyr linker scripts provides start and end symbols for each larger
areas in the linker script.

The symbols _image_rom_start and _image_rom_end corresponds to the group
ROMABLE_REGION defined in the ld linker scripts.

The symbols _image_rodata_start and _image_rodata_end is not placed as
independent group but covers common-rom.ld, thread-local-storage.ld,
kobject-rom.ld and snippets-rodata.ld.

This commit align those names and prepares for generation of groups in
linker scripts.

The symbols describing the ROMABLE_REGION will be renamed to:
_image_rom_start -> __rom_region_start
_image_rom_end   -> __rom_region_end

The rodata will also use the group symbol notation as:
_image_rodata_start -> __rodata_region_start
_image_rodata_end   -> __rodata_region_end

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2021-08-28 08:48:03 -04:00
Torsten Rasmussen
65a2de84a9 linker: align __data_ram/rom_start/end linker symbol names
Cleanup and preparation commit for linker script generator.

Zephyr linker scripts provides start and end symbols for each section,
and sometimes even size and LMA start symbols.

Generally, start and end symbols uses the following pattern, as:
Section name:             foo
Section start symbol:     __foo_start
Section end symbol:       __foo_end

However, this pattern is not followed consistently.
To allow for linker script generation and ensure consistent naming of
symbols then the following pattern is introduced consistently to allow
for cleaner linker script generation.
Section name:             foo
Section start symbol:     __foo_start
Section end symbol:       __foo_end
Section size symbol:      __foo_size
Section LMA start symbol: __foo_load_start

This commit aligns the symbols for _data_ram/rom to other symbols and in
such a way they follow consistent pattern which allows for linker script
and scatter file generation.

The symbols are named according to the section name they describe.
Section name is `data`

A new group named data_region is introduced which instead spans all the
input and output sections that was previously covered by
__data_ram_start, __data_ram_end, and __data_rom_start.

The following symbols are aligned in this commit:
-  __data_ram_start  -> __data_region_start
-  __data_ram_end    -> __data_region_end
-  __data_rom_start  -> __data_region_load_start

The following new symbols are introduced so that the data section is
aligned with other sections:
-  __data_end
-  __data_start
       value identical to __data_region_start but describes start of
       the section.

Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
2021-08-28 08:48:03 -04:00
Martí Bolívar
02b45f522f soc: riscv-ite: use new DT pinctrl accessors
Update to use the new APIs.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2021-08-25 18:09:00 -04:00
Henrik Brix Andersen
e6a3e238b9 soc: riscv: privilege: define soc_interrupt_init() as weak symbol
Define soc_interrupt_init as a weak symbol in the common RISC-V
privileged instruction set SoC support.

This allows overriding soc_interrupt_init for SoCs which are not fully
compliant with the RISC-V privileged specification.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-08-25 18:05:50 -04:00
Henrik Brix Andersen
d8e0027082 soc: riscv: privilege: define __soc_handle_irq as weak symbol
Define __soc_handle_irq as a weak symbol in the common RISC-V privileged
instruction set SoC support.

This allows overriding __soc_handle_irq for SoCs which are not fully
compliant with the RISC-V privileged specification.

Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
2021-08-25 18:05:50 -04:00
Tim Lin
9938519c93 ITE: soc: it8xxx2: add register build asserts to validate the offsets
Add build asserts to validate the offsets are the expected value.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-08-25 18:04:37 -04:00
Tim Lin
033eb55aca ITE: riscv: it8xxx2: declare gctrl dts node and registers
Add general control(gctrl) node in dts, and declare gctrl registers

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-08-25 18:04:37 -04:00
Jim Shu
f3e926b6d0 soc: riscv: esp32c3: apply CONFIG_RISCV_GP option
esp32c3 has already supported RISC-V GP, just apply new kconfig option
to it. Forcely select CONFIG_RISCV_GP in esp32c3 at first because it
seems to be necessary in the esp32c3 SoC.

Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-08-20 18:53:23 -04:00
Jim Shu
9d34256ea4 soc: riscv: telink_b91: add GP relative addressing support
Add norelax option before initializing GP at common entry point.

Remove __global_pointer$ symbol in the SoC linker script because it's
in the arch one. Remove -mno-relax when GP support is enabled.

Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-08-20 18:53:23 -04:00
Jim Shu
c3ecf5331b soc: riscv: riscv-privilege: add GP relative addressing support
Initialize GP at common entry point of riscv-privilege SoCs so that
this commit add GP support of these SoCs at once.

As some privilege SoCs want to customize the entry point, they should
disable linker relaxation by `.norelax option` before entrying the
common entry point `__start`.

Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-08-20 18:53:23 -04:00
Shubham Kulkarni
60caed8d54 soc: esp32c3: Fix symbol placement in linker script
Creating static libraries for drivers moves some symbols out of IRAM.
This change fixes it.

Signed-off-by: Shubham Kulkarni <shubham.kulkarni@espressif.com>
2021-08-20 18:25:22 -04:00
Dino Li
9c47f314a5 flash: it8xxx2: add a short delay before #CS be driven high
The delay will ensure last byte has been latched in before

This also change the method of reading status register from re-send
read status command on each read to read status register continuously.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2021-08-18 20:10:05 -04:00
Sylvio Alves
57e7fba288 soc: esp32: move board config to soc context
log and libc optimization default config are soc related
and should be moved out from board context.

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2021-08-18 07:46:29 -04:00
Jim Shu
2cff73d3ba soc: riscv: esp32c3: remove RISCV_SOC_INIT_GP_VALUE option.
As this option is not needed and has been removed, also remove it
in the esp32c3 SoC.

Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-08-18 05:18:55 -04:00
Jim Shu
97fa203330 Revert "arch: riscv: added support for custom initialization of gp register"
This reverts commit 7b09d031fa. Because
context save of GP register is removed, we don't need to initialize GP
at thread init. GP will be a constant value so that it could only be
initialized at program start.

Signed-off-by: Jim Shu <cwshu@andestech.com>
2021-08-18 05:18:55 -04:00
Sylvio Alves
1d219250bc soc: esp32c3: fix implicit declaration
replace HAL call to direct read reg function

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2021-08-09 13:15:47 -04:00
Sylvio Alves
6ea12f0fbb linker: esp32c3: add thread storage area
This adds missing _end area and remove
unused definitions present in the linker script

Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
2021-08-09 13:15:47 -04:00
Fabio Baltieri
ef93bbad57 linker: add an initialized DATA_SECTIONS linker location option
Current location options for linker source files includes init and
noinit ram data, but only a noinit ram section. This makes it impossible
for application code to define an initialized RAM output section,
such as with the Z_ITERABLE_SECTION_RAM() helpers.

Adding a DATA_SECTIONS linker source option for this use case.

Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
2021-08-07 20:26:41 -04:00
Felipe Neves
4a0b5ce277 soc: riscv: esp32c3: fix ble controller init
By appending the right link layer controller configurarion

Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-08-07 19:59:27 -04:00
Felipe Neves
2a5c37829d soc: riscv: esp32c3: make use of atomic in C
esp32c3 SoC is an rv32imc, so it does not support the atomic builtin.

Since it relies in atomic instructions.

Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-08-07 19:59:27 -04:00
Felipe Neves
2474c9b3f3 soc: riscv: esp32c3: added initial support for ble
subsystem by linking esp32 vhci adapter to the
espressif ble controller adapter

Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-08-07 19:59:27 -04:00
Felipe Neves
d368087fc0 drivers: serial: added minimal uart driver for esp32c3
based on uart rom functions, also enable console driver
on top if this driver enabling logging

Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-08-03 11:20:06 -05:00
Tim Lin
438bc9ec2a ITE: soc/riscv riscv-ite: create a shared macro to access the pinctrl_0
Create a shared macro to access the pinctrl_0 property. The pinctrl_0
property includes pinmux phandle, pin and alternate function.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-07-29 11:48:13 -04:00
Dino Li
eba3ed1668 soc: it8xxx2: correct extensions
it8xxx2 supports 'm', 'a', and 'c' extensions.
Enable them to save flash space and also improve
latency of fetching code from flash.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2021-07-26 19:30:33 -04:00