Commit graph

503 commits

Author SHA1 Message Date
Ruibin Chang
21f0f958fe ITE drivers/ite_it8xxx2_timer: re-write ite timer driver
Re-write ite timer driver.

Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
2021-07-24 21:26:49 -04:00
Ruibin Chang
97d2d7317c ITE soc/riscv/ite/it8xxx2/Kconfig: correct hw clock freq
Correct SYS_CLOCK_HW_CYCLES_PER_SEC and
SYS_CLOCK_TICKS_PER_SEC to match our real setting value
for precise timing.

Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
2021-07-24 21:26:49 -04:00
Yuriy Vynnychek
3de6c05f63 soc: riscv: telink_b91: new Telink B91 (TLSR9) SoC system
A new RISC-V platform SoC for Telink B91 (TLSR9).

Signed-off-by: Yuriy Vynnychek <yura.vynnychek@telink-semi.com>
2021-07-21 05:37:12 -04:00
Dino Li
b316d18cb0 drivers: gpio: it8xxx2: add support for GPIO_VOLTAGE_ flags
Support GPIO_VOLTAGE_1P8, GPIO_VOLTAGE_3P3 flags on IT8xxx2 chips.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2021-07-15 13:53:54 -05:00
Dino Li
7d5411d6e0 soc: it8xxx2: introduce SOC_IT8XXX2_PLL_FLASH_48M option
Enable SOC_IT8XXX2_PLL_FLASH_48M at default to reduce latency of
fetching code from flash.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2021-07-13 09:44:29 -04:00
Dino Li
a42be2f071 soc: riscv-ite: fix __soc_handle_irq
Save ra to caller saved register is wrong because it might get
overwritten after another function is called, so we fix this.

Remove clear mip register operation. (it8xxx2 supports machine-mode
only, and MEIP bit of mip is read-only).

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2021-07-09 12:45:01 -05:00
Felipe Neves
600f8c64e1 soc: riscv: esp32c3: use the new esp_rom prefix
For esp32c3 related ROM located functions instead
of esp32c3_rom.

Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-07-07 20:58:50 -04:00
Felipe Neves
2d1bdd86b6 soc: riscv: esp32c3: adds _PrepC to the startup code
The _PrepC() function is the standard risc-v way
of zephyr entry point, so let it call the z_cstart instead
of calling this function directly.

Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-07-07 20:58:50 -04:00
Felipe Neves
4c60d2ccc7 soc: riscv: esp32c3: add z_bss_zero in startup code
replaces the plain memcpy to zero the bss with
the standard zephyr function that does this task.

Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-07-07 20:58:50 -04:00
Felipe Neves
132ab922a8 drivers: timer: esp32c3: add esp32c3 systimer driver to CODEOWNERS
Also added maintainer to the entry

Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-07-07 20:58:50 -04:00
Felipe Neves
7b09d031fa arch: riscv: added support for custom initialization of gp register
Plus added implementation for esp32c3 SoC.

Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-07-07 20:58:50 -04:00
Felipe Neves
5d736766ed soc: esp32c3: added initial soc support files for esp32c3
by adding the soc specific files such: soc initialization code,
linker scripts and support for esp32c3 devkitm

Signed-off-by: Felipe Neves <ryukokki.felipe@gmail.com>
Signed-off-by: Felipe Neves <felipe.neves@espressif.com>
2021-07-07 20:58:50 -04:00
Kumar Gala
0b7824aba9 riscv: openisa_rv32m1: Fix booting of rv32m1_vega
rv32m1_vega don't boot due to device init ordering and changes with the
device model.  The soc code is looking for a device pointer for the
intmux.  Change to using DEVICE_DT_GET here as that will ensure we get
a valid pointer and by the time we need to utilize the pointer the
intmux driver will have been initialized and thus the device pointer
will be ready.

Also set BUILD_OUTPUT_HEX since we utilize openocd to flash and west
flash is looking for a hex file for openocd targets.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2021-07-01 17:03:17 -05:00
Ruibin Chang
d0ce9bb877 ITE drivers/pwm: add PWM for it8xxx2
Add pulse width modulator (PWM) for it8xxx2.

Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
2021-07-01 13:21:06 -04:00
Dino Li
512ff06f84 ITE: soc: it8xxx2: correct the offset of eflash signature
This change corrects the offset to 80h and also add description
of flash signature.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2021-06-24 20:17:54 -04:00
Tim Lin
ef3c8507a6 ite: drivers/flash: add flash driver for it8xxx2
Add flash driver for it8xxx2. The driver can implement
flash read, write and erase that will be mapped to the
ram section for executing.

TEST="flash write 0x80000 0x10 0x20 0x30 0x40 ..."
     "flash read 0x80000 0x100"
     "flash erase 0x80000 0x1000"

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-06-22 15:15:20 -04:00
Rajnesh Kanwal
1c584127ba boards: risc-v: add BeagleV Starlight JH7100 board support
Adding support for beagleV Starlight board based on Starfive JH7100
SoC. It's a base support, no drivers other than uart has been tested.

Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal49@gmail.com>
2021-06-22 08:45:00 -04:00
Ruibin Chang
d45668480a ITE driver/watchdog: add watchdog timer for it8xxx2
Add watchdog timer for it8xxx2.

Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
2021-06-18 11:21:53 +02:00
Ruibin Chang
0c3bb75a05 ITE soc/riscv/riscv-ite/common/chipregs: add registers and IRQ num
Add registers and IRQ number for PD control.

Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
2021-06-17 12:42:19 +02:00
Tim Lin
8ea58d4389 ite: drivers/adc: create pinmux phandle to the ADC driver node
Create the pinmux phandle to the ADC driver node in the
devicetree. When the pinmux_pin_set function in
adc_it8xxx2_channel_setup can refer to the setting of
this phandle. It is more flexible to use.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-06-11 15:47:25 +02:00
Ruibin Chang
3360637aff ITE Keyboard scan: add registers for ITE keyboard scan driver
Add registers for it8xxx2 keyboard scan driver.

Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
2021-05-17 15:24:11 -04:00
Tim Lin
5f5fb7d792 ite: drivers/adc: it8xxx2: fix adc driver flow
This commit fixes the ADC driver flow. And add internal
reference voltage to ADC driver API. And correct the
data buffer that only need to store raw data.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-05-13 11:54:05 -04:00
Tim Lin
caa3328cc7 ite: drivers/pinmux: modify pinmux driver
Modify the pinmux control method and add support the fun3
& fun4 alternation function.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-05-05 08:45:16 -04:00
Ruibin Chang
37de0c4987 drivers/interrupt_controller/intc_ite_it8xxx2: global ite_intc_isr_clear()
We need to clear interrupt status, before we enable the interrupt.
So I let ite_intc_isr_clear() to be global function.

Signed-off-by: Ruibin Chang <ruibin.chang@ite.com.tw>
2021-05-03 19:58:40 -04:00
Dino Li
ee39291553 dts: it8xxx2: change flash size to 1M byte
Flash size of IT8xxx2 is 1M byte.

Change-Id: Ic1464b6e36f16291f14024a6fb49acbf3a243176
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
2021-04-29 16:47:47 -05:00
Tim Lin
14e9e7a814 soc: riscv/riscv-ite: chip_chipregs: add chip register address
Add register address including external timer and watchdog(ETWD),
general control(GCTRL), serial peripheral interface(SPI).


Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-04-23 07:03:10 -04:00
Dino Li
0ab51ff657 drivers: gpio: ite_it8xxx2: enable more gpio groups
This change enables A, C, D, E, G, H, I, J, K, and L groups,
and fix gpio interrupt function.

This change also pull (and rename) dt-bindings/irq.h to
dt-bindings/interrupt-controller/ite-intc.h, because it is
chip-specific.

Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Change-Id: Ifee039981c2cc4cf5980e663702a9921e629fc1e
2021-04-23 06:31:56 -04:00
Tim Lin
cd96046bee ite: drivers/adc: add adc drivers on it8xxx2_evb platform
This commit is about the it8xxx2 analog to digital converter
driver. Support 8 channels ch0~ch7 and 10-bit resolution.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-04-13 13:01:56 -04:00
Tim Lin
309992280c soc: riscv: enable COMPRESSED_ISA for ITE chips
Enable the config of COMPRESSED_ISA, this can work fine on
32-bit architecture.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-03-25 07:07:19 -04:00
Katsuhiro Suzuki
e58e2767f8 arch: riscv: add common stub reboot function
This patch adds weak sys_arch_reboot() function to avoid build error
with CONFIG_REBOOT=y. Some SoC has already had own reboot function
but others (Ex. qemu boards) faced buld error.

- openisa_rv32m1: Not change
- riscv-ite: Do nothing, remove and use arch/riscv function

Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
2021-03-04 11:09:51 -06:00
Kumar Gala
f6b7dd09ec pinmux: sifive: Convert SiFive pinmux to be devicetree based
Add a simple pinctrl node for the IOF registers under the GPIO
controller node to be used by the pinmux driver.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2021-02-15 08:33:00 -05:00
Adam Jeliński
86ca5ff562 m2gl025_miv: Adjust frequencies and performance
The default frequency for this board in Renode is 66 MHz. This needs to
be even with `SYS_CLOCK_HW_CYCLES_PER_SEC` to avoid such problems as in
the #31726 issue.

Unfortunately, the difference in these values was helpful for some tests
that are failing with 66 MHz set in both places. It created artificial
boost in certain circumstances.

The frequencies in the default Renode platform description (`.repl`)
file for MI-V were overridden with 4 MHz value that seems to be better
tolerated based on testing. The `SYS_CLOCK_HW_CYCLES_PER_SEC` was
adjusted as well.

To solve the rest of the issues, `cpu PerformanceInMips` was set to 4.
It seems tests are completed faster with such a value.

This commit fixes #31726.

Signed-off-by: Adam Jeliński <ajelinski@antmicro.com>
2021-02-09 19:41:27 -05:00
Katsuhiro Suzuki
85315c1238 soc/riscv: support reboot for QEMU RISC-V VirtIO
This patch adds reboot function for QEMU RISC-V VirtIO board.

Signed-off-by: Katsuhiro Suzuki <katsuhiro@katsuster.net>
2021-02-04 13:14:12 -05:00
Martin Åberg
152d3e46ad soc/riscv: add the QEMU "RISC-V VirtIO board"
The QEMU RISC-V VirtIO board is capable:
- 8 x CPU
- 256 MiB RAM
- PMP
- PCI
- ISA string: RVnnIMAFDCSU
  - mul/div
  - FPU with double precision
  - MMU
  - Compressed instructions

Devicetree was extracted from QEMU as described in virt.dtsi.
The same .dtsi SOC description is used for 32-bit and 64-bit.

Signed-off-by: Martin Åberg <martin.aberg@gaisler.com>
2021-01-15 13:06:33 -05:00
Tim Lin
981166eb8e drivers/i2c: add i2c driver on it8xxx2 platform
This commit is about the it8xxx2 i2c master driver which
includes six SMBus channels. The enhanced channel i2c3,
i2c4, i2c5 are controller which are designed to support
the I2C protocol.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-01-15 11:22:57 -05:00
Tim Lin
8f4692083c soc/riscv: correct the name of the register
correct the name of bit5 of GCR2 register from SMB4E to SMB3E.

Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
2021-01-15 11:22:57 -05:00
Cheryl Su
46efefbbe5 soc/riscv: it8xxx2 soc system
A new platform soc for it8xxx2.
Revising the test/kernel/context/src/main.c for it8xxx2 test case.

Signed-off-by: Cheryl Su <cheryl.su@ite.com.tw>
2020-12-16 08:47:36 -05:00
Anas Nashif
e0f3833bf7 power: remove SYS_ and sys_ prefixes
Remove SYS_ and sys_ from all PM related functions and defines.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2020-12-09 15:18:29 -05:00
Alexandre Mergnat
542a7fa25d arch: riscv: add memory protection support
The IRQ handler has had a major changes to manage syscall, reschedule
and interrupt from user thread and stack guard.

Add userspace support:
- Use a global variable to know if the current execution is user or
  machine. The location of this variable is read only for all user
  thread and read/write for kernel thread.
- Memory shared is supported.
- Use dynamic allocation to optimize PMP slot usage. If the area size
  is a power of 2, only one PMP slot is used, else 2 are used.

Add stack guard support:
- Use MPRV bit to force PMP rules to machine mode execution.
- IRQ stack have a locked stack guard to avoid re-write PMP
  configuration registers for each interruption and then win some
  cycle.
- The IRQ stack is used as "temporary" stack at the beginning of IRQ
  handler to save current ESF. That avoid to trigger write fault on
  thread stack during store ESF which that call IRQ handler to
  infinity.
- A stack guard is also setup for privileged stack of a user thread.

Thread:
- A PMP setup is specific to each thread. PMP setup are saved in each
  thread structure to improve reschedule performance.

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Reviewed-by: Nicolas Royer <nroyer@baylibre.com>
2020-11-09 15:37:11 -05:00
Daniel Leung
8a79ce1428 riscv: add support for thread local storage
Adds the necessary bits to initialize TLS in the stack
area and sets up CPU registers during context switch.

Signed-off-by: Daniel Leung <daniel.leung@intel.com>
2020-10-24 10:52:00 -07:00
Pawel Czarnecki
82acea40b3 soc: riscv: litex-vexriscv: change CSR accessors
Do not assume `reg_size` to be a multiple of 4 and
divide it on each call, expect the caller to provide
an already divided value instead.

This change require the LiteX GPIO driver to be modified,
which will come in the following commit.

Signed-off-by: Pawel Czarnecki <pczarnecki@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
2020-10-02 11:36:16 +02:00
Tomasz Bursztyka
e18fcbba5a device: Const-ify all device driver instance pointers
Now that device_api attribute is unmodified at runtime, as well as all
the other attributes, it is possible to switch all device driver
instance to be constant.

A coccinelle rule is used for this:

@r_const_dev_1
  disable optional_qualifier
@
@@
-struct device *
+const struct device *

@r_const_dev_2
 disable optional_qualifier
@
@@
-struct device * const
+const struct device *

Fixes #27399

Signed-off-by: Tomasz Bursztyka <tomasz.bursztyka@linux.intel.com>
2020-09-02 13:48:13 +02:00
Anas Nashif
ce59510127 arch: xip: cleanup XIP Kconfig
unify how XIP is configured across architectures. Use imply instead of
setting defaults per architecture and imply XIP on riscv arch and remove
XIP configuration from individual defconfig files to match other
architectures.

Signed-off-by: Anas Nashif <anas.nashif@intel.com>
2020-08-07 09:50:22 -04:00
Karsten Koenig
2e61137cc9 arch: riscv: thread: Init soc context on stack
The optional SOC_CONTEXT carries processor state registers that need to
be initialized properly to avoid uninitialized memory read as processor
state.
In particular on the RV32M1 the extra soc context stores a state for
special loop instructions, and loading non zero values will have the
core assume it is in a loop.

Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>
2020-07-13 15:00:19 -05:00
Karsten Koenig
dc725b7451 soc: riscv: rv32m1: Fix optional context save
Saving an extended context for RV32M1 should be optional, but it was
broken due to the offset calculation not taking the according option
into account.

Signed-off-by: Karsten Koenig <karsten.koenig.030@gmail.com>
2020-07-13 15:00:19 -05:00
Stephanos Ioannidis
3322489d22 config: Rename TEXT_SECTION_OFFSET to ROM_START_OFFSET
The `TEXT_SECTION_OFFSET` symbol is used to specify the offset between
the beginning of the ROM area and the address of the first ROM section.

This commit renames `TEXT_SECTION_OFFSET` to `ROM_START_OFFSET` because
the first ROM section is not always the `.text` section.

Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
2020-07-09 14:02:38 -04:00
Kumar Gala
9ca541a504 linker: Remove deprecated Kconfig options related to linker scripts
Remove Kconfig, linker script, and related bits associated with
CUSTOM_RODATA_LD, CUSTOM_RWDATA_LD, CUSTOM_SECTIONS_LD,
SOC_NOINIT_LD, SOC_RODATA_LD, and SOC_RWDATA_LD options that have been
deprecated since Zephyr 2.2.

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-06-12 11:14:28 +02:00
Kumar Gala
a1b77fd589 zephyr: replace zephyr integer types with C99 types
git grep -l 'u\(8\|16\|32\|64\)_t' | \
		xargs sed -i "s/u\(8\|16\|32\|64\)_t/uint\1_t/g"
	git grep -l 's\(8\|16\|32\|64\)_t' | \
		xargs sed -i "s/s\(8\|16\|32\|64\)_t/int\1_t/g"

Signed-off-by: Kumar Gala <kumar.gala@linaro.org>
2020-06-08 08:23:57 -05:00
Jakub Cebulski
7f6dbccba8 soc: litex: Add function for reading 64bit CSRs
This adds a helper function for reading LiteX 64-bit CSRs
to be used by LiteX drivers.

Signed-off-by: Jakub Cebulski <jcebulski@internships.antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
2020-05-26 21:43:30 +02:00
Martí Bolívar
6e8775ff84 devicetree: remove DT_HAS_NODE_STATUS_OKAY
Several reviewers agreed that DT_HAS_NODE_STATUS_OKAY(...) was an
undesirable API for the following reasons:

- it's inconsistent with the rest of the DT_NODE_HAS_FOO names
- DT_NODE_HAS_FOO_BAR_BAZ(node) was agreed upon as a shorthand
  for macros which are equivalent to
  DT_NODE_HAS_FOO(node) && DT_NODE_HAS_BAR(node) &&
- DT_NODE_HAS_BAZ(node), and DT_HAS_NODE_STATUS_OKAY is an odd duck
- DT_NODE_HAS_STATUS(..., okay) was viewed as more readable anyway
- it is seen as a somewhat aesthetically challenged name

Replace all users with DT_NODE_HAS_STATUS(..., okay), which is
semantically equivalent.

This is mostly done with sed, but a few remaining cases were done by
hand, along with whitespace, docs, and comment changes. These special
cases include the Nordic SOC static assert files.

Signed-off-by: Martí Bolívar <marti.bolivar@nordicsemi.no>
2020-05-13 18:24:42 +02:00