hal_espressif systimer HAL calls are based on 1MHz reference.
This changes systimer driver to allow max clocking reference of 16MHz
and increases soc tick resolution by reducing min delay interval.
This also sets all ESP32-C3 socs to 16MHz hardware cycles reference.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
IT8XXX2 HW support sha256 calculation, and its calculation is
faster than FW. We place SHA256 message, hash and key data
(total 512bytes) in RAM. If we enable hw sha256, because
HW limits, the sha256 data must place in first 4KB of RAM.
We add sections for hw sha256 calculation in linker.
Signed-off-by: Dino Li <Dino.Li@ite.com.tw>
Signed-off-by: Ruibin Chang <Ruibin.Chang@ite.com.tw>
Low-power management is part of the RTC peripherals' domain
on ESP32C3. This dependency implies the need to bring some RTC
registers to a known state, during system initialization, to
achieve proper low-power handling.
The RTC slow memory region is also delimited and used during
power domain options selection.
Signed-off-by: Glauber Maroto Ferreira <glauber.ferreira@espressif.com>
Add new variant configuration of it81202cx and it81302cx.
This cx variant of it81xx2 changes are as follows:
1. SRAM size will increase from 60k to 128k.
2. Configurable ILM size is still 60k.
3. Support M extension of RISC-V.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
- Put L2C init level in pre_kernel_2 to wait for syscon driver
- Check if SMU exists when preprocessing
Signed-off-by: Wei-Tai Lee <wtlee@andestech.com>
Use spisc_it8xxx2_regs instead of IT83XX_SPI_*** registers declaration
to fix in cros_shi_it8xxx2.c
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
IT8xxx2 uses a relatively slow SPI flash for ROM with a small 4k
I-cache. As a result in large or busy applications, instruction fetch
can be very costly due to I-cache misses. Since exception handling code
is some of the hottest code in most applications, add an option (enabled
by default) causing that code to execute out of RAM in order to improve
performance.
This is very similar to exception section placement on XIP niosii
platforms (which has similar motivation), but can still be disabled by
configuration.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
These functions are small and may be very hot depending on the workload,
so are usually a good choice to execute from RAM.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Executing code out of RAM on IT8xxx2 requires that the relevant
addresses be mapped onto the CPU's instruction memory bus, referred to
by ITE documentation as Instruction Local Memory (ILM). ILM mappings
configure blocks of RAM to be used for accesses to chosen addresses when
performing instruction fetch, instead of the memory that would normally
be accessed at that address.
ILM must be used for some chip features (particularly Flash
self-programming, to execute from RAM while writing to Flash), and has
historically been configured in the Flash driver. The RAM for that was
hard-coded as a single 4k block in the linker script. Configuring ILM
in the flash driver is confusing because it is used by other SoC code as
well, currently in code that cannot depend on the Flash being functional
or in hand-selected functions that seem performance-critical.
This change moves ILM configuration to a new driver and dynamically
allocates RAM to ILM in the linker script, allowing software use of the
entire 64k RAM depending on configuration. This makes ILM configuration
more discoverable and makes it much easier to correctly support the
CODE_DATA_RELOCATION feature on this SoC.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
The chip I2C driver uses chip_get_pll_freq(), so that function needs to
be built even when the PLL configuration is not changed at boot.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
Continue to phase out MP_NUM_CPUS, change Kconfig to be
MP_MAX_NUM_CPUS and make MP_MAX_NUM_CPUS the main Kconfig symbol.
Signed-off-by: Kumar Gala <kumar.gala@intel.com>
The soc.h from the espressif HAL module provides register definitions
like APB_CLK_FREQ, which are required for the Zephyr TWAI driver.
Signed-off-by: Martin Jäger <martin@libre.solar>
Some files were using macros defined in sys/util.h without including it,
e.g. for MHZ().
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Some SoCs define stuff in soc.h, used in drivers or SoC code. Note that
soc.h is not introduced here as a catch-all header. soc.h optimizations
or removal is out of the scope of this patch.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Add options about Internal RC(IRC) oscillator.
- GD32_HAS_IRC_32K/40K indicates IRC types.
- GD32_LOW_SPEED_IRC_FREQUENCY is the numeric value of frequency
Signed-off-by: TOKITA Hiroshi <tokita.hiroshi@gmail.com>
Linker scripts contains a `.last_section` section that is placed in rom
region as NOLOAD for the purpose of retrieve the actual number of bytes
contained in the image. See d85efe0b10
However, a previous section may cause the location counter to be
incremented for alignment purposes. This can result in the size of the
image to be 0x10FA but location counter to be 0x1100 because it has been
aligned for next section placement.
Therefore, two new Kconfig settings are introduced.
Those settings request the linker to will write a pattern in
`.last_section`. Together with removing NOLOAD and writing a patten to
the section then we ensure that data is written after alignment of
location counter, and thereby forces the image size to be in sync with
the location counter.
The default pattern used will be 0xE015 (end of last section).
Some systems may fill up the flash completely, or simply write data at
the end of the flash, which in both cases can result in overflow.
Therefore, the new settings can be disabled.
Signed-off-by: Torsten Rasmussen <Torsten.Rasmussen@nordicsemi.no>
Now that timer drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <galak@kernel.org>
This patch adds a clock control driver for GD32 platforms. It is
important to note that the driver is only able to handle peripheral
clocks, but not "system clocks" (e.g. PLL settings, SYS_CK, etc.). On
some similar platforms (STM32) this task is embedded in the same clock
driver, performed at init time but with no options to do any
manipulation at runtime via the API calls. The clock control API as-is
is really orthogonal to "system clocks", and it is arguably a bad idea
to embed system clock init code in a clock control driver. It can be
done at SoC level still using Devicetree as a source of hardware
description/initial configuration.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
As of today <zephyr/zephyr.h> is 100% equivalent to <zephyr/kernel.h>.
This patch proposes to then include <zephyr/kernel.h> instead of
<zephyr/zephyr.h> since it is more clear that you are including the
Kernel APIs and (probably) nothing else. <zephyr/zephyr.h> sounds like a
catch-all header that may be confusing. Most applications need to
include a bunch of other things to compile, e.g. driver headers or
subsystem headers like BT, logging, etc.
The idea of a catch-all header in Zephyr is probably not feasible
anyway. Reason is that Zephyr is not a library, like it could be for
example `libpython`. Zephyr provides many utilities nowadays: a kernel,
drivers, subsystems, etc and things will likely grow. A catch-all header
would be massive, difficult to keep up-to-date. It is also likely that
an application will only build a small subset. Note that subsystem-level
headers may use a catch-all approach to make things easier, though.
NOTE: This patch is **NOT** removing the header, just removing its usage
in-tree. I'd advocate for its deprecation (add a #warning on it), but I
understand many people will have concerns.
Signed-off-by: Gerard Marull-Paretas <gerard.marull@nordicsemi.no>
Place vector sections after ROM_START sections.
Also add init.ld script that will prevent overlapping .init sections
in telink_b91 SoC.
Fixes#49036.
Signed-off-by: Mateusz Sierszulski <msierszulski@antmicro.com>
Update all esp32 socs to include esp_timer early init, which
is part of hal v4.4.1 update.
Update reboot function to meet proper SoC init/deinit peripherals.
Signed-off-by: Sylvio Alves <sylvio.alves@espressif.com>
Now that clock control drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <galak@kernel.org>
Now that interrupt controller drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <galak@kernel.org>
This commit updates the custom target architecture type specified for
the `SOC_OPENISA_RV32M1_RI5CY` and `SOC_OPENISA_RV32M1_ZERO_RISCY` SoC
types to be compatible with the GCC 12, which now uses the ISA spec
20191213 by default.
Note that the hack overriding the build system-default `-march` flag
for these SoCs needs to be removed and they should be properly
specified using the ISA extension Kconfigs.
Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
Similar to pinctrl, almost all device drivers will depend on the reset
controller being available, so default the driver class to y at SoC
level.
Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
Pull more function into ram code section to effectively improve
access speed and performance.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Adding I2C FIFO mode can reduce the time between each byte to
improve the I2C bus clock stretching during I2C transaction.
The I2C master supports two 32-bytes FIFOs, channel A and C
are supported now.
I2C FIFO mode of it8xxx2 can support I2C APIs including:
i2c_write(), i2c_read(), i2c_burst_read.
Test:
1. tests\drivers\i2c\i2c_api --> pass
2. Reading 16 bytes of data through i2c_burst_read() can reduce
0.52ms(2.4ms->1.88ms) compared to the original pio mode when the
frequency is 100KHz.
3. It is normal to read sensor data through I2C on Nereid's platform.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
Now that peci drivers are enabled based on devicetree
we need to remove any cases of them getting enabled by
Kconfig.defconfig* files as this can lead to errors.
Signed-off-by: Kumar Gala <galak@kernel.org>
This option was previously enabled only if the M extension was
available, because typical compilers do not provide internal libraries
for RV32IAFC so builds fail at link-time. An appropriately-configured
compiler (such as GCC configured with
`--with-multilib-generator=rv32iac-ilp32--f`) can support such a build
however, so don't lie about the presence of an FPU.
This doesn't affect existing builds because CONFIG_FPU gates use of the
FPU, and is off by default. Enabling CONFIG_FPU will require an
appropriately-configured compiler, possibly also requiring careful
choice of CONFIG_FLOAT_HARD.
Signed-off-by: Peter Marheine <pmarheine@chromium.org>
