Two DMA channels are assigned to AES channels A and B respectively.
Each channel A/B has an interface to control the conditions that will
generate requests on the related DMA channel: trigger condition,
R/W address, and DMA done action.
Signed-off-by: Julien Panis <jpanis@baylibre.com>
The CYW43xxx for Infineon Controllers stops after the first LauncRAM
command. Newer Controllers like the CYW5557x update the firmware in
multiple stages, which is supported by this commit.
Signed-off-by: Matthias Ringwald <matthias@ringwald.ch>
make sure that autonegotiation is restarted, after
changing the speeds. Also make sure to only write
the changed registers, as mdio is pretty slow.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
remove phy related configs from eth config.
phy related configs chould go directly into the phy.
Most ethernet drivers didn't support the now removed
functions yet. Users should instead use `phy_configure_link()`
together with the `net_eth_get_phy()` function.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
Newer AIROC controllers like the CYW55573 don't support changing the
baudrate in Download Mode. However, a higher baud rate can be used
directly to sent HCI Reset.
This commit adds the KConfig flag CONFIG_AIROC_DOWNLOAD_MODE to enable
the new behaviour.
Signed-off-by: Matthias Ringwald <matthias@ringwald.ch>
Prevent integer underflow when sequence->channels is 0.
Add an explicit check before calling find_msb_set().
Coverity CID: 487765
Signed-off-by: sudarsan N <sudarsansamy2002@gmail.com>
Only include cmsis_core.h on ARM platforms, including it unconditionally
as it is now causes a build failure on all other platforms, namely x86
on the weekly build run.
Tested with:
west build -p -b up_squared/apollo_lake tests/drivers/build_all/led
(and others)
Signed-off-by: Fabio Baltieri <fabiobaltieri@google.com>
PG142 from AMD specifically says the uartlite IP generates a
"rising-edge sensitive interrupt" when interrupts are enabled. When
using this IP on a ZynqMP platform with
CONFIG_UART_INTERRUPT_DRIVEN enabled, the GIC does not get
configured correctly to detect these interrupts. Update driver to heed
the flags set by the interrupts property in the device tree.
Signed-off-by: Michael Estes <michael.estes@byteserv.io>
Fix channel ID check in dac_esp32_channel_setup as it was allowing to
set up a channel with ID greater than the number of channels.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The IRER registers are write-only and clear the enable bit for the
provided interrupt. Use a direct write instead of a read/modify/write
sequence to avoid generating a bogus read access and improve performance
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Some ADC's draw significant power while enabled, so make sure the
driver can handle ADC's that have device runtime PM enabled.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Reset the SPI peripheral to its default state
and register values on init by setting its SWRST bit.
This is important since the driver assumes that certain
registers are at their default values.
Signed-off-by: Pete Dietl <petedietl@gmail.com>
The sam0 SPI driver does not ensure that it clears the 32-bit extension
option during init. The 32-bit extension option, which comprises of a field
in the CTRLC register and the LENGTH register enables better bus
utilization by allowing 32-bit writes to the SPI DATA register
(as opposed to the usual 8-bit writes). The driver breaks down if this
option is enabled by causing each intended byte of output to become
four bytes. We fix this by explicitly disabling the 32-bit extension
option in init.
Signed-off-by: Pete Dietl <petedietl@gmail.com>
When not using dynamic interrupt mapping, various interrupt tables are
configured to be stored in read-only memory in the linker script.. Mark
them const so that the linker doesn't complain.
This affects _sw_isr_table, _irq_vector_table, and z_shared_sw_isr_table in
arch/common along with _VectorTable in arch/arc.
Signed-off-by: Keith Packard <keithp@keithp.com>
Change nxp_imx_mu_send() to return a negative errno value
on error.
The fsl_mu function MU_TriggerInterrupts() returns either
kStatus_Success or kStatus_Fail, which have the value 0
or 1, respectively. kStatus_Fail should not be returned
to the upper levels, which expect negative values for
errors, so add a check for the return value of
MU_TriggerInterrupts() and return an errno value on error.
Signed-off-by: Mike J. Chen <mjchen@google.com>
The mode is activated by the CONFIG_MODBUS_NONCOMPLIANT_SERIAL_MODE option
and allows any stop-bit setting for the serial port.
Signed-off-by: Maksim Salau <msalau@iotecha.com>
To determine whether device runtime PM is enabled on a device, use
`pm_device_runtime_is_enabled`. This results in the same behaviour when
`CONFIG_PM_DEVICE_RUNTIME=n`, but properly controls the clocks on a
per-instance basis when `CONFIG_PM_DEVICE_RUNTIME=y`.
Signed-off-by: Jordan Yates <jordan@embeint.com>
TI MSPM0 SoC series has General Purpose Timer and Advanced control timers
with Counting module, Capture block (measure input signal period/time) and
Compare block (to generate time expiry, output waveform like PWM).
Add a support for counter driver with alarm and counter top functions.
Signed-off-by: Saravanan Sekar <saravanan@linumiz.com>
IDLEOUT presence in PWM means that there are 3 sources from which
PWM pin can be driven:
- GPIO setting when PWM peripheral is disabled.
- IDLEOUT setting when PWM is enabled.
- PWM Sequence when it is in use.
IDLEOUT setting cannot be changed after enabling PWM so it is
configured to the initial state of the pin. It means that if duty
cycle is 100%, GPIO output is set to 1 but initial pin state was 0
(IDLEOUT setting) there will be a glitch between disabling a PWM
sequence and disabling a PWM peripheral.
By default, PWM driver tries to disable PWM peripheral if all channels
are 0% or 100% duty cycle to safe power. When IDLEOUT feature is
present there will be a short glitch on channels with 100% duty cycle.
In order to avoid that CONFIG_PWM_NRFX_NO_GLITCH_DUTY_100 option is
added (enabled by default). When option is enabled 100% duty cycle
is achieved by PWM sequence and not by driving a GPIO pin. It will
consume more power in cases where all channels are 0% or 100% with
at least one channel set to 100% duty cycle.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
New versions of the Wiseconnect HAL require a clock manager init
function to be called as part of clock configuration.
Without this, the default reference clock isn't configured correctly
for use with peripherals.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
Follow-up to PR #88631: fix missing variable declarations introduced in
the STM32 I2C LL driver after adding timeouts to blocking loops.
The missing declarations caused a build failure when interrupts were
disabled (CONFIG_I2C_STM32_INTERRUPT=n).
Fixes a regression introduced in #88631.
Signed-off-by: Jean Nanchen <jean.nanchen@gmail.com>
The uart_busy_set and uart_busy_clear are only used when runtime
pm is not enabled. So add #ifndef CONFIG_PM_DEVICE_RUNTIME to
enclose these two functions.
Signed-off-by: Leifu Zhao <leifu.zhao@intel.com>
AS6212 supports 0.25Hz, 1Hz, 4Hz, and 8Hz sampling frequencies, but the
current driver supports 0.25Hz, 1Hz, 4Hz, and 16Hz sampling frequencies.
Signed-off-by: Clément Laigle <c.laigle@catie.fr>
Two DMA channels are assigned to TX and RX respectively:
- A TX DMA request is asserted when there is space in the FIFO.
- A RX DMA request is asserted when data is in the FIFO.
When DMA is enabled for a peripheral, the DMA transfer completion is
signaled on the peripheral's interrupt only (here UART's interrupt).
It is not signaled on the DMA dedicated interrupt.
Also, when DMA is enabled for a peripheral, the DMA controller stops
the normal transfer interrupts for this peripheral from reaching the
NVIC (the interrupts are still reported in the interrupt registers of
the peripheral). Thus, when a large amount of data is transferred using
DMA, instead of receiving multiple interrupts from the peripheral as
data flows, the NVIC receives only one interrupt when the transfer
completes (unmasked peripheral error interrupts continue to be sent
to the NVIC).
Signed-off-by: Julien Panis <jpanis@baylibre.com>
The ADC has a dedicated interface for communicating with the DMA.
The ADC module provides four interrupt sources (one for each
conversion result storage register) which can be configured to
source the DMA trigger.
Signed-off-by: Julien Panis <jpanis@baylibre.com>
Add check for odr <= 0 and cast odr to uint32_t before multiplication
to avoid integer overflow and division by zero.
Fixes: CID 489220
Signed-off-by: sudarsan N <sudarsansamy2002@gmail.com>
For MAX32657, 'MXC_DMA_EnableInt' function requires DMA instance
and this causes build error. To fix this, created wrapper version
of this function and update driver with it.
Signed-off-by: Furkan Akkiz <hasanfurkan.akkiz@analog.com>
Registers driver with pm_device_driver_init(). Peform
software reset on TURN_ON. Added a small delay after
power-up
Signed-off-by: Van Petrosyan <van.petrosyan@sensirion.com>
Fixed typos in the preprocessor macros for pressure range initialization
Unfortunately this particular configuration is not covered in CI since
build_all test has pressue-range "D2" and the broken code was concerning
"D9"
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
To convey the correct data size, use the 'data->dfs' value instead
of '1' when moving the SPI context to the next buffer.
Signed-off-by: Andreas Wolf <awolf002@gmail.com>
Fix a bug in the touch threshold calculation where channel_num was
incorrectly used instead of channel_sens.
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
