Refactor ISR by:
1) making a helper function to put the tickful calculation in, to reduce
an indentation level and cognitively separate this case while reading
2) Rewrite the calculations to simplify them. More info on that below.
Math changes:
- In the ISR, there was a variable called "now" which represented the
current cycle count of the timer. last_count was updated using a
calculation based on the number of elapsed ticks
and the hardware cycles per second value. However, this is
redundant because mathematically, this is equivalent to "now". So the
variable can just be set to now.
Proof is that the previous calculation was (in programming language):
(1) last_count = last_count + elapsed_ticks * CYC_PER_TICK
So let's rewrite this as the following to be clear about the different
values we are talking about here (in math language):
(2) count[t] = count[t-1] + elapsed_ticks * CYC_PER_TICK
We calculated elapsed ticks in the function as:
(3) elapsed_ticks = (now - last_count) / CYC_PER_TICK
(4) elapsed_ticks = (now - count[t-1]) / CYC_PER_TICK
Rearranging (2), we see
(5) elapsed_ticks = ( count[t] - count[t-1] ) / CYC_PER_TICK
Substituting this into (4), we get:
(6) ( count[t] - count[t-1] ) / CYC_PER_TICK =
(now - count[t-1]) / CYC_PER_TICK
Doing simple algebra, you can see we result with:
(7) count[t] = now
So therefore, we can simplify the programming expression to
(8) last_count = now
- The other change is regarding the calculation of the next tick match
value for tickful kernel mode. The previous calculation was doing:
(1) next = now + CYC_PER_TICK
We know that last_count is equivalent to now, at this point in the code
with the first change:
(2) next = last_count + CYC_PER_TICK
And then, for some reason, we are adding yet another CYC_PER_TICK to
next if (next - now) < MIN_DELAY. The reason for that I do not
understand, but let's write that down:
(3) next - now < MIN_DELAY
Now rewrite (2) as (4) and (3) as (5):
(4) count[t+1] = count[t] + CYC_PER_TICK
(5) count[t+1] - count[t] < MIN_DELAY
And now we substitute (4) into (5):
(6) count[t] + CYC_PER_TICK - count[t] < MIN_DELAY
And simplify:
(7) CYC_PER_TICK < MIN_DELAY
So actually no runtime calculations are needed here, this is a
hardcoding. The reason for this calculation I don't know, but we can
simplify the code.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
There are a couple places where effectively the exact same calculation
is done. Refactor to share code to do this calculation to make it easier
to read, and explode the code to multiple statements to be even easier
to follow the calculation. Compiler will likely optimize the same way
when opt enabled. Rename dticks variable to be more explicit what that
means (elapsed ticks).
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
Refactor to remove nesting and consolidate lines of code.
I also ran clang format but that actually did not change very much in
addition to what I had already changed manually.
Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
1.Remove the code that sets the UTRIM register to 0,
because UTRIM is automatically loaded with a factory-trimmed
value, zeroing will affect the accuracy. Only need to clear
VREF UTRIM[TRIM2V1] at the initialization stage.
2. VREF does not have NXP_VREF_MODE_INTERNAL_REGULATOR mode,
the internal voltage regulator and chop oscillator are used
to suppress power supply noise and reduce voltage offset,
so remove the NXP_VREF_MODE_INTERNAL_REGULATOR mode.
there are only three modes in VREF, the first is the standby
mode (CSR[BUF21EN] = 0, CSR[HI_PWR_LV] = X), the second is
low power mode (CSR[BUF21EN] = 1, CSR[HI_PWR_LV] = 0), and
the third is high power mode (CSR[BUF21EN] = 1, CSR[HI_PWR_LV] = 1).
Signed-off-by: Zhaoxiang Jin <Zhaoxiang.Jin_1@nxp.com>
RP2350 adds four more PWM slices from the eight available on RP2040,
which are only broken out to package pins on RP2350B. This change fixes
the driver to support the correct number of slices on RP2350.
Tested by confirming that PWM can correctly be configured on GPIO 44 of
RP2350B.
Signed-off-by: Peter Marheine <peter@taricorp.net>
Replace direct assignment of evt.evt_data with structured access via
espi_evt_data_pvt. This change separates the incoming evt_data into
type and data fields.
This update alse includes support for handling PVT, PVT2, and PVT3
events using the structured event data.
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
For devices other than the stm32h745/747/755/757 that use
dual-core cortex-M4/cortex-M7, do not multiply flash
controller size by 2. Single-core stm32h7x devices define
their flash-controllers dtsi as a single area, not two banks.
Use the presence of the bank2-flash-size prop to determine if
this is a dual-core stm3h7x or not.
Signed-off-by: Rory Piper <rory.piper@signal-fire.com>
Introduce a new API function in the sdmmc_stm32 driver that allows
applications to access the Card Identification (CID) register of the
SD/MMC card. This functionality, already available in the SPI-based SD
and MMC subsystems, was previously missing from the STM32 SDMMC driver.
This enhancement enables use cases such as verifying the correct SD card
during manufacturing, ensuring that OEMs use the specified SD card, and
preventing mismatches.
Signed-off-by: Arthur Gay <arthur.gay@marshmallow.kids>
According to the STM32MP2 reference manual, the I2C controller uses
a single interrupt line for all events (EV + ERR), so the combined
interrupt must be enabled for the STM32MP2 series.
Signed-off-by: Tanguy Raufflet <tanguy.raufflet@savoirfairelinux.com>
The STM32MP2 series needs gpioz pinctrl support to be able to use
the GPIOZ pins.
Signed-off-by: Tanguy Raufflet <tanguy.raufflet@savoirfairelinux.com>
1. Add config and overlay file in test scatter_gather for adp_xc7k_ae350
and adp_xc7k_ae350_clic to support the test case.
2. Modify the config file in test chan_blen_transfer and loop_transfer
because the tests do not support the NOCACHE memory configuration,
the DCACHE configuration needs to be disabled.
Signed-off-by: Kevin Wang <kevinwang821020@google.com>
1. Upgrade the ATCDMAC driver to make it compatible with multiple
ATCDMAC series drivers.
2. Rename the driver from ATCDMAC300 to ATCDMACX00.
Signed-off-by: Kevin Wang <kevinwang821020@google.com>
This commit adds support for the new cs-high-time devicetree property.
The QUADSPI_DCR_CSHT is now configured according to the value indicated
in the devicetree, for both single and dual flash modes.
Signed-off-by: Thomas Altenbach <altenbach.thomas@gmail.com>
The QSPI 1/2 sample shift (SSHIFT) was only enabled in dual flash mode.
This feature is useful to guarantee that data is ready at the sampling
moment, even if the signals are a bit delayed due to PCB constraints.
Therefore, it should be enabled when possible (only supported in STR
mode).
Signed-off-by: Thomas Altenbach <altenbach.thomas@gmail.com>
Now that the timer kernel clocks are defined in device tree, use the
clock get API to fetch the clock frequency instead of calculating the
value in the driver.
Removes the now unused function get_tim_clk.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Now that the timer kernel clocks are defined in device tree, use the
clock get API to fetch the clock frequency instead of calculating the
value in the driver.
Removes the now unused function counter_stm32_get_tim_clk.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add support for timer kernel clock for STM32H7.
Define a new property for the timer prescaler in the RCC binding of H7.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Add support for timer kernel clock for STM32H5.
Define a new RCC binding for H5 with the timer prescaler property (timpre).
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
- Code optimization for platforms which don't use subscription feature
in the temperature service.
- Test adaptation to code changes
Signed-off-by: Rafal Dyla <rafal.dyla@nordicsemi.no>
This commit disables spi clock during idle to reduce power
consumption.
Tested with: reduce current cons. by around 0.08mA on it515xx_evb
Signed-off-by: Ren Chen <Ren.Chen@ite.com.tw>
Flush the data cache if cache management is enabled. Flushing the data
cache is required to ensure data retention across system resets.
Signed-off-by: Henrik Brix Andersen <henrik@brixandersen.dk>
After 8495e30726 some display controller
drivers failed to start. Make the start optional and enabled by default if
there are frame buffers allocated by the driver.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
The OTG_HS PHY from stm32u5a5xx device require the correct reference
clock frequency selction in SYSCFG_OTGHSPHYCR. The current default is
hard coded to 16Mhz (which matches the development board crystal).
However, a custom board my require a different crystal and then the
USB will not work. This add a required field in the
st,stm32u5-otghs-phy binding to force user to select the correct
clock reference. The current nucleo_u5a5zj_q baord was updated to
reflect the mandatory field.
Signed-off-by: BUDKE Gerson Fernando <gerson.budke@leica-geosystems.com>
The Locally Administered Address (LAA) bit should be set on the first
octet of the MAC address.
Signed-off-by: Pieter De Gendt <pieter.degendt@basalte.be>
Implementation should use a dedicated function to get OpenThread
instance instead of using the deprecated pointer from context.
Signed-off-by: Adrian Gielniewski <adrian.gielniewski@nordicsemi.no>
