Rework adc_stm32.c to consume the new two-level DT structure.
Config structures:
- adc_stm32_cfg (parent): now owns all shared/capability fields
(clk_cfg, clk_prescaler, resolution table, sampling_time_table,
sequencer_type, oversampler_type, internal_regulator,
has_deep_powerdown, has_channel_preselection,
has_differential_support, has_injected_support).
- adc_sub_stm32_cfg (child): reduced to instance-specific fields
(base address, parent pointer, irq_cfg_func, clk_cfg for F1/F4,
pcfg, differential_channels_used).
- Add adc_stm32_get_parent_cfg() helper to retrieve the parent config
from a child device.
Move runtime accesses to shared DT properties from the child config to
the parent config, and keep only instance-local settings in the child
device configuration.
For series with shared IRQ lines, generate a single common ISR per
IRQn and elect one owner per IRQn using DT_DEP_ORD. Only the owner
node installs and enables the interrupt.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Assisted-by-AI: GitHub Copilot (GPT-5.4)
Instead of defining custom DMA macros in the SAI driver, use the generic
newly created ones from the DMA driver.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
The slot argument from macros STM32_DT_INST_DMA_SLOT* was useless.
With it the macro was basically a redefinition a the Zephyr macro.
It is now removed to be similar to other STM32 DMA macros that call
DT_INST_DMAS_CELL_BY_NAME.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Typically Zephyr device tree macros that take a inst as argument
start with DT_INST_.
For the STM32 DMA driver we currently have several macros taking an inst as
argument but missing this prefix.
For consistency, it is added to these macros. The goal is to also define
DT_ variants of these macros that take a node_id as argument.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
Typically Zephyr device tree macros that take a node_id as argument
start with DT_ and those that take an inst start with DT_INST_.
For the STM32 clock driver we currently have two macros named
STM32_DT_INST_CLOCK_INFO_BY_NAME and STM32_CLOCK_INFO_BY_NAME.
For consistency, the latter is renamed STM32_DT_CLOCK_INFO_BY_NAME.
Signed-off-by: Guillaume Gautier <guillaume.gautier-ext@st.com>
The i.MX PWM block on the i.MX8M family had no Zephyr driver. The
existing `fsl,imx27-pwm` driver covers the same IP but is built on the
legacy device_imx.h HAL, which only supports i.MX6SX and i.MX7D.
Add a driver on top of the MCUX ipwm HAL, binding to `nxp,ipwm`. The
prescaler comes from devicetree and fixes the counter rate reported
by `pwm_get_cycles_per_sec()` polarity is mapped onto `PWMCR.POUTC`.
No interrupt is used, as a single PWMSAR write sustains the output.
`set_cycles()` only guards against a full sample FIFO, returning
`-EAGAIN` rather than blocking the caller. Changing the period or the
polarity stops the counter and drains the FIFO first, since queued
samples no longer match the new configuration.
Signed-off-by: Guilherme Freire <guilherme.almeida@toradex.com>
The i.MX8M PWM instances are fed by their own CCM target roots, which
the CCM driver could not resolve: the existing `IMX_CCM_PWM_CLK`
identifier belongs to the FlexPWM block on i.MX RT and returns the IPG
frequency.
Add `IMX_CCM_PWM1_CLK..PWM4_CLK` under a separate peripheral ID and
resolve them from `PWMn_CLK_ROOT`, decoding the mux and applying the
pre- and post-dividers.
`EXT_CLK_1/EXT_CLK_2` are board inputs whose rate the SoC cannot
report, so they return `-ENOTSUP` rather than a guess.
Signed-off-by: Guilherme Freire <guilherme.almeida@toradex.com>
aplic_init only directly calles aplic_msi_init or
aplic_direct_init, so we can set that function directly
as the init function.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
all these functions that are changed always
return 0, so change the return type to void,
as always returning 0 deliver no information.
Especially as the return value is already ignored
everywhere where these functions are used.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
use asserts for checks, as the irq configuration
comes from the devicetree and we don't need
that check in production, it should be enough
if it is checked in testing.
ALso most of these functions itself are used in
where the return value is quietly ignored, so
asserts actually help finding wrong configuration.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
if the prio is bigger than the max prio, use
the max prio as prio, just like we do in the
regular plic driver.
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
The STM32WL3 series uses the same implementation as STM32WB0 series and
thus supports level-triggered interrupts. Enable the capability at
driver level by loosening the allowlist.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
The AT25040 EEPROM chip is 512 bytes and the way it accepts the 9th
address bit is via the opcode. The 8 address bytes can only address
256 bytes. To address 512 bytes, you need the 9th address bit or'd
into the opcode
Signed-off-by: Gaurang Gunde <ggunde@axon.com>
sys_clock_driver_init() seeded the timer core's announce baseline from
the counter and only then enabled the timer. QEMU's Cortex-A9 global
timer model reports the time since machine start while the timer is
disabled and restarts the count from zero once it is enabled, so the
baseline ended up ahead of the counter for the first few milliseconds
of the run. Every sys_clock_elapsed() in that window computed a wrapped
delta that clamps to UINT32_MAX ticks, so a timeout queued then was
placed about 2^32 ticks out and never expired. Which timeouts land in
the window depends on the boot timing, so an unrelated change in code
layout made tests/net/lib/mqtt_sn_client hang in its first test case
on qemu_cortex_a9.
Enable the timer before timer_core_init() so the baseline is taken from
the running counter, and keep the compare interrupt masked until the
core has armed the first deadline.
Assisted-by: Claude Fable 5.1
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
File was missing a semicolon, without which it didn't compile if
CONFIG_FLASH_RENESAS_RA_HP_CHECK_BEFORE_READING was set
Signed-off-by: Paolo Bazzanella <pbazzanella@qubicaamf.com>
The write path wraps the same way: offset SIZE_MAX with size 1 passes the
offset + size check in every driver and corrupts the byte below the BBRAM
region. Run the same range check before the write is dispatched.
Signed-off-by: Flavio Ceolin <flavio@hubble.com>
A user thread picks both offset and size, and the drivers bound the access
with offset + size against the capacity, which wraps for large offsets and
lets the read land below the BBRAM region. Reject a range that does not fit
the device before the read is dispatched.
Signed-off-by: Flavio Ceolin <flavio@hubble.com>
ps8xxx_init_work_cb() ignored the result of gpio_add_callback(). When
the alert callback cannot be registered, the driver goes on to mark the
TCPC as initialized. Nothing reports the failure, and once the alert
work stops finding pending alerts, no later alert is ever serviced.
Reported by Coverity as CID 487607.
Log the error and abort the initialization instead. The TCPC then stays
marked as not initialized, so tcpc_init() returns -EAGAIN and the
Type-C layer does not start. The rt1715 and fusb307 drivers handle the
same failure this way.
Build-tested only; the error path was not exercised on PS8xxx hardware.
Fixes#84769
Signed-off-by: YunHung Hua <oliverhua.us@gmail.com>
Add Write-only mode where instead of copying from a real source, a
channel repeatedly writes a fixed pattern to the destination address.
Mode is selected via a new private channel_direction value
XILINX_ADMA_DIR_WRITE_ONLY.
Signed-off-by: Abin Joseph <abin.joseph@amd.com>
Remove usage of functions that query the state of `struct modem_chat`
from inside the callbacks. The required information is now available
directly from the callback arguments.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Update the type definition of `modem_chat_script_callback` to take a
pointer to a context variable. This context variable holds additional
internal information about the script that the callback might be
interested in.
The goal is to remove any need for the callback itself to query internal
state of the `modem_chat`, because anything it needs it has already
been given. Eventually, this will lead to callbacks being able to queue
a new script directly from the callback of the previous script.
Breaking API change.
Signed-off-by: Jordan Yates <jordan@embeint.com>
Read the input clock rate from the clock controller. Allow to
also define the clock rate via the device-tree.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Add a very basic clock control driver for the Aesc Silicon IP.
Right now, it's main purpose is to calculate the domain specific
frequency by reading the reference clock and the domain
multiplier/divider values.
Also update the v4.5 release notes and mention this new driver.
Signed-off-by: Daniel Schultz <dnltz@aesc-silicon.de>
Introduce a Kconfig option to let users configure the SysTick interrupt
priority like any other hardware interrupt in the system.
This allows adjusting the SysTick priority to reduce latency impact on
higher-priority interrupts when needed.
Note that the timekeeping code in the Systick driver tolerates at most
one counter wrap between updates, so the tick must not be held off longer
than the wrap period. The minimum timeout is now a fixed 10 us budget
(SYSTICK_MIN_DELAY_US) converted to cycles at the actual clock rate and
floored at two cycles, with zephyr,min-timeout-cycles on the systick node
still overriding it. Lowering SysTick below other interrupts makes its
worst-case hold-off the nested run time of every higher-priority
interrupt, and any missed wrap silently drops a full last_load of uptime
with no diagnostic.
This 10 us budget is far tighter than the older tick-based floor, so
non-default priorities are safe ONLY while the worst-case hold-off stays
below the wrap period, and in practice **must** be paired with a larger
zephyr,min-timeout-cycles on the systick node.
The default priority preserves the current behavior of using the highest
maskable/kernel IRQ priority (_IRQ_PRIO_OFFSET).
Signed-off-by: Marouen Ghodhbane <marouen.ghodhbane@nxp.com>
The U5 HAL programs the burst as (SrcBurstLength - 1U), so 0 underflows
and configures a 64 beat burst instead of a single one, making the SAI
DMA transfer fail on start. Set the burst length in the driver
Signed-off-by: Fabrice DJIATSA <fabrice.djiatsa-ext@st.com>
`pending_length` is supposed to be the "Pending length to be transferred
in bytes, HW specific", but the DMAC keeps track of a number of elements
remaning instead, and the driver returned this value verbatim.
Read the number of elements pending and multiply it by source data size
before returning it to comply with the API specification.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
Fixes various issues with Kconfigs, including:
- Using the wrong indentation
- Not having [EXPERIMENTAL] in the prompt, or not having it at
the end
- Wrongly stating the CONFIG_EXPERIMENTAL is needed to enable
an experimental Kconfig
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
Fixes various issues with Kconfigs, including:
- Redundent `default n` on bools
- Not select deprecated on supposed deprecated symbols
- Using the wrong indentation
- Not having [DEPRECATED] in the prompt, or not having it at the
end
Signed-off-by: Jamie McCrae <jamie.mccrae@nordicsemi.no>
use a mutex for the generic ethernet phy instead of a semaphore.
Benefit of the mutex is that it is recursive .
Signed-off-by: Fin Maaß <f.maass@vogl-electronic.com>
STM32MP13 uses a 32-bit AXI4 DMA bus master interface, not the 32-bit
AHB interface used by the other series with a 32-bit data bus. Reusing
the AHB DMA_SYSBUS_MODE value on STM32MP13 left the AXI4-only bits
(burst length and outstanding request limits) unset.
Signed-off-by: Tim Pambor <tim.pambor@codewrights.de>
Use LINKER_DT_NODE_REGION_NAME_TOKEN instead of LINKER_DT_NODE_REGION_NAME
for getting the section name in order to avoid doing twice stringify
on the section name. Indeed, LINKER_DT_NODE_REGION_NAME already
stringify the name, which is again stringify a 2nd time by
Z_GENERIC_SECTION, leading to section name such as "PSRAM" instead of
PSRAM.
Signed-off-by: Alain Volmat <alain.volmat@foss.st.com>
Add a set_buffer_property driver callback and the matching
fuel_gauge_set_buffer_prop() syscall so applications can write variable
length buffer properties, such as configuration images or manufacturer
defined data blocks, to a fuel gauge device. This mirrors the existing
fuel_gauge_get_buffer_prop() API.
The source is documented as an opaque, pointer-free byte buffer because
the syscall verifier can only validate the src/src_len range itself.
The callback is optional. The verifier checks the device object and the
source buffer only and leaves the callback check to
z_impl_fuel_gauge_set_buffer_prop(), so user mode callers get -ENOSYS
instead of a kernel oops when a driver does not implement it.
Signed-off-by: Johannes Schuler <jschuler@testo.de>
Assisted-by: Claude:claude-fable-5-1
Apply the same settling delay used on STM32WB0.
Clear BYPSHAD and wait for RSF before entering initialization mode,
to avoid the silicon errata ES0612 Rev 8 2.9.2:
"Calendar initialization may fail in case of consecutive INIT mode entry"
Without this, rtc_set_time() returns -ETIMEDOUT after any operation
that has written an RTC register, as INITF fails to assert within
RTC_TIMEOUT. The first synchronization after reset takes 35 to 40 ms
on the NUCLEO-WL33CC1, which the settling delay alone does not cover.
The series has no EXTI. External interrupts are handled by SYSCFG,
and RTC interrupts are directly connected to the NVIC,
so the EXTI calls in exti_enable_rtc_alarm_it() and
exti_clear_rtc_alarm_flag() are skipped.
Signed-off-by: Anders Frandsen <anfran@anfran.dk>
I2C_CR1_WUPEN is per device, not per series. STM32F030, F070, WB0 and
WL3 do not have it, so registering an I2C target failed to build there
with a declaration of LL_I2C_EnableWakeUpFromStop().
Use the same guard as the LL HAL (stm32f0xx_ll_i2c.h) instead of a
check for STM32F7.
Validated on STM32F0, F7, G0, WB0, WL and WL3 (Twister, no HW).
Signed-off-by: Anders Frandsen <anfran@anfran.dk>
bt_ipm_ble_init() logs an error when bt_ipm_set_addr() fails and
carries on regardless, so a controller that rejects
ACI_HAL_WRITE_CONFIG_DATA comes up with a silently different identity
address. Return the error instead, so that bt_enable() fails and the
caller learns that the controller is in an unexpected state.
The UID64 is factory programmed on every part, so bt_get_ble_addr()
returning NULL is not an expected case either and fails setup the same
way.
Assisted-by: Claude:claude-fable-5-1
Signed-off-by: Johan Hedberg <johan.hedberg@silabs.com>
- preserve buffer ownership on error paths, consistent with API
expectations [See also bt_hci_send documentation], preventing
double unref.
- fix the data length check as the pre-allocated event buffer
already carried the H:4 indicator, so its tailroom was one byte
short of the 71-byte Read Local Supported Commands response, and
smaller responses only passed because net_buf_reset() discarded
that byte before the copy.
- Factorize common code to improve maintainability, keeping flow
control only in the indication
Signed-off-by: Michele Sardo <msmttchr@gmail.com>
The WAIT_FOR timeout for RTC_SR_ACKUPD_Msk was set to 5000 us (5 ms),
which is far too short. The RTC acknowledges an update request at the
next second boundary after RTC_CR_UPDTIM/UPDCAL are written, so the
wait can be up to ~1 second. This caused rtc_mchp_set_time() to always
time out on sama5d2.
Increase the timeout to 1,100,000 us (1100 ms) to allow a full second
boundary to elapse with margin.
Fixes: 7cff6281d7 ("drivers: rtc: microchip: introduce G2 rtc driver")
Signed-off-by: Tony Han <tony.han@microchip.com>
In rtc_mchp_isr(), the second-tick event was tested using
RTC_SR_SEC_Msk against sr, which is mis-wrote to RTC_SCCR_SECCLR_Msk.
There is no runtime impact because the values for RTC_SCCR_SECCLR_Msk
and RTC_SR_SEC_Msk are the same.
Fixes: 7cff6281d7 ("drivers: rtc: microchip: introduce G2 rtc driver")
Signed-off-by: Tony Han <tony.han@microchip.com>
The SFR_CAN_SRAM_SEL register has one bit per hardware MCAN peripheral.
The driver was indexing that register with the DT enumeration index
(assigned by DT_INST_FOREACH_STATUS_OKAY) instead of the index by MCAN
hardware peripheral number. When the two values are not the same, the
wrong bits are set, causing the hardware to read CAN configuration from
the wrong 64 kB SRAM bank.
Fixes: bd15f36928 ("drivers: can: sam: update the can_sam driver for
sama7g5 MCAN")
Signed-off-by: Tony Han <tony.han@microchip.com>
Add a semihosted flash driver, which utilizes the semihosting interface
to write to a flash file on the host. The flash file will be created if
it does not exist, but otherwise an existing flash file is used. This
driver can therefore be used for testing flash in cases where the
contents need to be set before application startup (such as mcuboot)
Assisted-by: Claude:claude-haiku-4-5
Signed-off-by: Daniel DeGrasse <daniel.degrasse@analog.com>
Add driver for Silicon Labs Series 3 WDOG peripheral. The
driver supports window min/max as well as a warning interrupt
(multistage).
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
When spi_context_wait_for_completion() times out, the SDK transfer
handle is left busy and every later transfer on the bus fails with
kStatus_ECSPI_Busy until reboot.
Abort the transfer and deassert the chip select on error so the bus
recovers, as spi_nrfx_spim already does on -ETIMEDOUT.
ECSPI_MasterTransferHandleIRQ() does not check the handle state, so a
completion interrupt latched just before the abort would still run the
callback, start the next word and signal the context again. Disarm the
callback with a flag before aborting, with interrupts locked so the ISR
cannot interleave with the abort, and clear the completion signal
(ctx.sync, or ctx.ready without CONFIG_MULTITHREADING) to drop a
completion that raced in before the flag was set.
Signed-off-by: Ryomei Osaki <o.ryomei1020@gmail.com>
Add driver for Silicon Labs Series 3 EXTMEM flash controlled by
the SE. The initial version of the driver supports reading from
and getting the layout of the entire flash, but only writing
and erasing data regions.
Signed-off-by: Aksel Skauge Mellbye <aksel.mellbye@silabs.com>
On MCXW SoCs the EWM is clock gated. Until the MCXW clock control driver
was introduced, soc.c opened the gate unconditionally.
PR #101937 removed that hardcoded initialization and described the
gate in dts instead, but wdt_nxp_ewm never consumed the new "clocks"
property. The gate is left closed and the first register write in
nxp_ewm_init() takes a precise bus error.
Enable the clock during init for instances that describe one. SoCs that
do not gate the EWM have no "clocks" property and keep the previous
behaviour.
Signed-off-by: Yves Wang <zhengjia.wang@nxp.com>
The QTMR driver exposes every hardware channel of a TMR block as an
independent counter device with .channels = 1, so chan_id 0 is the only
alarm channel it accepts: counter_set_channel_alarm() and
counter_cancel_channel_alarm() reject anything else with -EINVAL, and the
counter API rejects it even earlier with -ENOTSUP.
The ISR, however, handed the callback config->channel, i.e. the hardware
channel index from the devicetree. On a device instantiated from
qtmr1_timer1 the alarm callback was therefore told chan_id 1, and an
application that fed that value straight back into
counter_cancel_channel_alarm() got -ENOTSUP.
Report 0 instead, which is what the capture path already does.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
Update the STM32 HAL module to new revision with updated STM32Cube
package for various series and update the RTC driver accordingly:
some function that was named differently in STM32CubeU3 vs. all other
series has been realigned to the usual name so an #if SERIES check in
that driver can - in fact, must - be dropped.
Signed-off-by: Mathieu Choplain <mathieu.choplain-ext@st.com>
