drivers: serial: uart_xlnx_uartlite: set irq flags per device tree
PG142 from AMD specifically says the uartlite IP generates a "rising-edge sensitive interrupt" when interrupts are enabled. When using this IP on a ZynqMP platform with CONFIG_UART_INTERRUPT_DRIVEN enabled, the GIC does not get configured correctly to detect these interrupts. Update driver to heed the flags set by the interrupts property in the device tree. Signed-off-by: Michael Estes <michael.estes@byteserv.io>
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1 changed files with 10 additions and 8 deletions
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@ -375,14 +375,16 @@ static DEVICE_API(uart, xlnx_uartlite_driver_api) = {
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};
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#ifdef CONFIG_UART_INTERRUPT_DRIVEN
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#define XLNX_UARTLITE_IRQ_INIT(n, i) \
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do { \
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IRQ_CONNECT(DT_INST_IRQN_BY_IDX(n, i), \
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DT_INST_IRQ_BY_IDX(n, i, priority), \
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xlnx_uartlite_isr, \
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DEVICE_DT_INST_GET(n), 0); \
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\
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irq_enable(DT_INST_IRQN_BY_IDX(n, i)); \
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#define XLNX_UARTLITE_IRQ_INIT(n, i) \
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do { \
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IRQ_CONNECT(DT_INST_IRQN_BY_IDX(n, i), \
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DT_INST_IRQ_BY_IDX(n, i, priority), \
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xlnx_uartlite_isr, DEVICE_DT_INST_GET(n), \
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COND_CODE_1(DT_INST_IRQ_HAS_CELL_AT_IDX(n, i, flags), \
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(DT_INST_IRQ_BY_IDX(n, i, flags)), \
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(0))); \
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\
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irq_enable(DT_INST_IRQN_BY_IDX(n, i)); \
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} while (false)
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#define XLNX_UARTLITE_CONFIG_FUNC(n) \
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static void xlnx_uartlite_config_func_##n(const struct device *dev) \
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