The accel and magn full-scale setters used an undeclared data pointer
when the respective FULL_SCALE_RUNTIME options are enabled. Declare
it from dev->data.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
lsm9ds0_gyro_set_fs_raw() used an undeclared data pointer when
CONFIG_LSM9DS0_GYRO_FULLSCALE_RUNTIME is enabled. Declare it from
dev->data.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
lsm9ds0_mfd_magn_set_odr() iterated the accelerometer ODR map instead
of the dedicated magnetometer map, producing out-of-range M_ODR codes
for frequencies above 100 Hz.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The sample rate was shifted with the bandwidth field shift, so the
value never intersected the DR mask and the requested ODR was always
programmed as zero. Use the DR field shift.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Minor improvements in the driver found when running UART stress test
(uart_async_dual). Mainly, preventing running RX timeout handler when
RX is already being disabled and missing barrier when reading CC TIMER
register.
Signed-off-by: Krzysztof Chruściński <krzysztof.chruscinski@nordicsemi.no>
Add clock control driver
Implement bootup clock initialization, on, off, configure and get_rate API
Signed-off-by: Sunil Abraham <Sunil.Abraham@microchip.com>
i2c_esp32_config_pin() reattaches the I2C peripheral to its pins after
i2c_master_clear_bus() has bit-banged them as GPIOs to clock a stuck
slave free. It did so with esp_rom_gpio_matrix_out/in(), passing
gpio_dt_spec::pin as the absolute GPIO number. That only holds for the
gpio0 bank (GPIO0..31).
On the original ESP32, GPIO32..39 are exposed through a second controller
(gpio1) where the pin index is 0..7. For an I2C bus whose SDA/SCL live on
gpio1, the reattach rerouted the I2C signals onto GPIO0/1 instead. GPIO1
is the default UART0 TX, so triggering bus recovery hijacked the console
and never restored the bus -- and the original ESP32 has no hardware
clear-bus, so this bit-bang path is the only recovery available.
Reapply the pinctrl default state instead, which restores exactly the mux
the driver installed at init, independent of the GPIO bank the pins are
on.
Signed-off-by: Richard Osterloh <richard.osterloh@gmail.com>
The window lookup indices are computed against the closest
achievable period, which can be smaller than the requested window
bounds, producing index 5 and reading one past the end of the
five-entry lookup tables. Clamp the indices so an out-of-range
start hits the invalid sentinel and the end saturates at 100%.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The TX path flushed a fixed CONFIG_NET_BUF_DATA_SIZE per fragment
though the DMA reads only frag->len. Flush only frag->len bytes.
Assisted-by: Claude:opus-4.8
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
net_pkt_get_len() was called for every fragment, walking the chain
each time. Compute the frame length once before the descriptor loop.
Assisted-by: Claude:opus-4.8
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Let's avoid a build warning/error in the spim interrupt handler mapping,
by being explicit about passing to it as parameter the address of
`nrfx_spim_t spim` data instead of knowing implicitly that it is the first
element of `struct driver_data`.
This avoid the following build warning/error:
nfx_spim.h:472:42: note: expected 'nrfx_spim_t *' but argument is of
type 'struct driver_data *'
Issue introduced in:
6f2829ea0c
Can be reproduced building
tests/arch/arm/arm_irq_vector_table for thingy53/nrf5340/cpuapp
with CONFIG_SPI_RTIO=y
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
Let's avoid a build warning/error in the spim interrupt handler mapping,
by being explicit about passing to it as parameter the address of
`nrfx_spim_t spim` data instead of knowing implicitly that it is the first
element of `struct driver_data`.
This avoid the following build warning/error:
nrfx_spim.h:472:42: note: expected 'nrfx_spim_t *' but argument is of
type 'struct driver_data *'
Issue introduced in:
e4d61fc472
Can be reproduced building
tests/arch/arm/arm_irq_vector_table for thingy53/nrf5340/cpuapp
Signed-off-by: Alberto Escolar Piedras <alberto.escolar.piedras@nordicsemi.no>
The last TX word must be written to FIFOWR as a full 32-bit write to
properly set the EOT (end-of-transfer) control bit at bit 20. Commit
7cb3fca changed the DMA block_size for the last word from
sizeof(uint32_t) to data->word_size_bytes, which meant only the lower
data bytes were transferred, missing the EOT flag entirely.
The issue #107484 mentions that this will cause the last
transfer to be incorrect width, but deep down in the NXP dma driver
there is a fix for this. See dma_mcux_lpc.c (line 262-273).
Fixes: #107484
Signed-off-by: Lars Jeppesen <lje@foss.dk>
Implement the counter capture API (capture_configure, enable_capture,
disable_capture) for both GPT input capture channels (CAPTURE1 and
CAPTURE2).
Supported trigger modes: rising edge, falling edge, both edges.
Single-shot capture disables the interrupt and resets the channel
after the first event; continuous capture leaves it armed.
Select COUNTER_SUPPORTS_CAPTURE in Kconfig so the generic counter
layer exposes the capture API to applications.
Signed-off-by: Jaro Van Landschoot <jaro.vanlandschoot@basalte.be>
Add optional pinctrl support so board files can mux GPT_CLK,
GPT_CAPTUREn, and GPT_COMPAREn pins via the standard pinctrl-0
property. The default state is applied early in driver init, before
GPT_Init. A missing pinctrl state (-ENOENT) is treated as optional
and silently ignored.
Signed-off-by: Jaro Van Landschoot <jaro.vanlandschoot@basalte.be>
Allow selecting from all five GPT clock sources (off, periph,
high-freq, ext, low-freq, osc) via a new clock-source DT property.
The ext source fixes the prescaler at 1 since the frequency
is unknown to software.
gptfreq is no longer required when clock-source = "ext", in which
case counter_get_freq() returns 0 and callers work in raw ticks.
Signed-off-by: Jaro Van Landschoot <jaro.vanlandschoot@basalte.be>
The NXP IRTC driver declared the RTC calibration ops but left both
set_calibration and get_calibration as -ENOTSUP stubs, even though
they are wired into the API table under CONFIG_RTC_CALIBRATION.
Implement them on top of the IRTC coarse compensation logic. With
fine compensation disabled, COMPEN[7:0] is a two's-complement count
of RTC source clock cycles added to / removed from the cycles used
to generate one 1 Hz tick, applied once per COMPEN[15:8]-second
interval. The source clock frequency is taken from the node's
clock-frequency property (16.384 kHz or 32.768 kHz) rather than
CTRL[CLK_SEL], because that field is not configured / readable on
every IRTC platform (e.g. RT700 does not set clock-src). Fixing the
interval at 1 s gives ppb = value * 1e9 / cycles; set() computes the
rounded register value, rejects values outside the -128..+127
register range with -EINVAL, and get() reports the programmed
(quantized) value so a set()/get() round-trips at the hardware
resolution.
A positive COMPEN value adds source clock cycles and slows the RTC
down (measured on MCXN236 hardware), while the RTC API defines
positive calibration as increasing the RTC frequency, so the value
is negated in both directions.
Per the RM, with CTRL[FINEEN] = 0 compensation must be disabled via
CTRL[COMP_EN] before COMPEN is changed for the first time, so the
update sequence always disables compensation around the COMPEN
write. get() reports 0 when compensation is disabled. Both ops
return -EPERM on a share-counter secondary instance, whose time
counters are owned by the primary IRTC. All register access reuses
the driver's existing write-protection unlock under irq_lock rather
than the MCUX HAL, which does not unlock write protection.
Validated on frdm_mcxn236 (16.384 kHz source):
tests/drivers/rtc/rtc_api with CONFIG_RTC_CALIBRATION=y passes 4/4,
and a differential second-edge timing measurement against the CPU
cycle counter confirms +max/-max calibration shortens/lengthens the
RTC second by the expected ~0.77%.
Link: MCX N23x Reference Manual, Rev. 4 - RTC chapter 43 (COMPEN 43.5.1.18)
Signed-off-by: Holt Sun <holt.sun@nxp.com>
nxp_irtc_update_set_callback() called ARG_UNUSED(calibration) on an
identifier that does not exist in that function, which would fail to
compile with CONFIG_RTC_UPDATE=y. Reference the actual unused
parameter (callback) instead.
Signed-off-by: Holt Sun <holt.sun@nxp.com>
The STM32H5 clock driver disabled PLL1 before reconfiguring it but
did not wait until PLL1RDY was cleared. On STM32H5 this can leave
PLL1 reconfiguration unreliable when switching to a high-frequency
system clock during early boot.
Wait for PLL1 to be fully disabled (PLL1RDY cleared) before
reconfiguring it, as required by the reference manual.
Signed-off-by: Liang Jiaxiang <moonbite233@gmail.com>
Introduce initial implementation of shell subcommands for the SCMI Base
protocol. This expands the existing `scmi` shell command with a new
`base` subcommand, allowing users to access SCMI Base operations from
the shell.
Previously, only clock protocol commands were available through the SCMI
shell interface. This change adds support for retrieving protocol
version and platform revision information, discovering agents,
configuring device permissions, and resetting agent configurations,
using base protocol.
The change also updates CMakeLists.txt to include the new 'base.c'
source file when SCMI Base helpers are enabled.
Signed-off-by: Grygorii Strashko <grygorii_strashko@epam.com>
Signed-off-by: Svitlana Drozd <svitlana_drozd@epam.com>
Refactor SCMI base protocol API by removing the version extraction from
the `scmi_base_get_revision_info` function and renaming to the
`scmi_base_get_platform_info`.
Previously, the implementation version (`impl_ver`) was not stored
in the platform info structure, resulting in incomplete data. Fix
this by assigning `impl_ver` after retrieving the implementation
version.
Add the new `scmi_base_get_num_agents` function to simplify
agent_id input validation, eliminating the need to call the larger
`scmi_base_get_revision_info` for simple check.
Signed-off-by: Svitlana Drozd <svitlana_drozd@epam.com>
Previously, flash parameters (size, erase/write block size) were
hardcoded for internal flash only.
Introduce struct flash_info and update_flash_info() to dynamically
resolve flash parameters based on the active flash target (internal,
external CS0/CS1).
Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
No logging level was defined for the WM8904 audio codec driver.
Set it to the audio codec log level, allowing for uniformized,
yet granular log level control.
Signed-off-by: Titouan Christophe <titouan.christophe@mind.be>
No logging level was defined for the PCM1681 audio codec driver.
Set it to the audio codec log level, allowing for uniformized,
yet granular log level control.
Signed-off-by: Titouan Christophe <titouan.christophe@mind.be>
No logging level was defined for the MAX98091 audio codec driver.
Set it to the audio codec log level, allowing for uniformized,
yet granular log level control.
Signed-off-by: Titouan Christophe <titouan.christophe@mind.be>
No logging level was defined for the CS43L22 audio codec driver.
Set it to the audio codec log level, allowing for uniformized,
yet granular log level control.
Signed-off-by: Titouan Christophe <titouan.christophe@mind.be>
SLIRCLR is write-1-to-clear, so writing zero clears nothing. Skip the
SPI write when slir is zero.
Assisted-by: Claude:opus-4.8
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Add a driver for the Hamamatsu S9706 digital RGB sensor using plain
GPIOs. All parameters (e.g. integration time and sensor range) are
runtime-configurable via sensor attributes.
Signed-off-by: Anton Puppe <anton-noel-flynn.puppe@zeiss.com>
Adjust defaults on nRF70 Series for a lower RAM footprint.
A 130 kB heap is too large for many applications.
Signed-off-by: Simon Duquennoy <simon.duquennoy@nordicsemi.no>
Store the return value of lc709203f_set_temp_mode() in ret so errors
during temperature mode configuration are properly logged and detected
rather than testing a stale return value.
Assisted-by: Antigravity:gemini-3.6-flash
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
LP IO wakeup sampling needs the independent LP IO clock enabled
when programming pin wakeup. Without it, the first deep sleep
cycle can draw excess current until sleep prepare force-enables
the clock. Enable/disable the clock with EXT1/GPIO wakeup setup.
Signed-off-by: Raffael Rostagno <raffael.rostagno@espressif.com>
After dynamic address assignment the code intends to release the
device's static address, but freed the newly assigned dynamic
address instead, undoing the reservation made just above and
allowing the same dynamic address to be handed out again.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
After dynamic address assignment the code intends to release the
device's static address, but freed the newly assigned dynamic
address instead, undoing the reservation made just above and
allowing the same dynamic address to be handed out again.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
After dynamic address assignment the code intends to release the
device's static address, but freed the newly assigned dynamic
address instead, undoing the reservation made just above and
allowing the same dynamic address to be handed out again.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
After dynamic address assignment the code intends to release the
device's static address, but freed the newly assigned dynamic
address instead, undoing the reservation made just above and
allowing the same dynamic address to be handed out again.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Setting the gender attribute wrote sub-index 0x08, which belongs to
age (height 0x06, weight 0x07, age 0x08), overwriting the age
setting. Use sub-index 0x09.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
The full-scale attribute passed MAX31875_DATA_FORMAT_SHIFT (a bit
position) as the register mask, clearing the conversion-rate bits and
never setting the data format. Use BIT(MAX31875_DATA_FORMAT_SHIFT).
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Before this change, the host performed half-duplex SPI transactions,
which caused frames that happen to be queued by ESP at the same time
of a TX transfer to be dropped. This is especially noticeable with
the new firmware.
Rework the driver so every SPI transaction is full-duplex: outgoing
frames are queued and the event task drains TX while simultaneously
capturing RX, so nothing is lost.
Other major improvements of the driver:
* Remove SPI bus semaphore, since only the event task uses the bus now.
* Reduce stack usage of all threads by 50% by refactoring data structures.
* Simplify event task by moving fragment validation and reassembly into
a utility function.
* Fix undefined behavior in checksum validation.
* Fix the reassembly overflow guard (was off by twice the header).
* Split TX/RX queue sizes into separate Kconfig options.
* Fix and improve error codes usage (use -ENOBUFS, -EMSGSIZE, etc).
Signed-off-by: Ibrahim Abdalkader <i.abdalkader@gmail.com>
The wait loop after enabling the PLL spun while the stable bit was
set, so it exited immediately while the PLL was still locking. Wait
until the stable bit becomes set.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
Starting the LXT passed the PWRCTL HIRC enable bit position as the
STATUS bit to poll, so LXT readiness was judged from an unrelated bit.
Pass CLK_STATUS_LXTSTB_Pos, matching the HXT and LIRC calls.
Assisted-by: Claude:fable-5
Signed-off-by: Benjamin Cabé <benjamin@zephyrproject.org>
This commit separates the stepper adi_tmc registers into separate headers
by series. It removes any dependencies between series in the register
definitions. See #105388.
Assisted-by: Claude:claude-opus-4.8
Signed-off-by: Perry Naseck <pnaseck@media.mit.edu>
Implement soc_secure_mem_read for flash driver to read secure memory,
access to the range of secure memory from non secure side should be
governed by tfm_platform allow list, implementation aligns to nrf_rram
driver secure memory read.
Signed-off-by: Travis Lam <travis.lam@nordicsemi.no>
